KR20010068538A - The method of forming test patterns for semiconductor devices - Google Patents

Abstract

PURPOSE: A method for forming a test pattern of a semiconductor device is provided to obviate problems generated when a test pattern formed on a scribe line is different from a test pattern formed within a cell. CONSTITUTION: The first structure(302) is etched on a chip region and the second structure(304) is etched on a test pattern region by using a PR mask to form patterns(310a,310b). The PR mask is removed. The operation pattern(310a) of a semiconductor device is formed on an upper part of the first structure. The test pattern(310b) is formed on an upper part of the second structure to test the semiconductor device. The operation pattern(310a) and the test pattern(310b) are formed to have the same size according to the PR pattern on the PR mask. The etching process is determined according to a process forming the first structure(302) and the second structure(304). A wet etching or a dry etching can be proceeded. Therefore, a difference of focus between the chip region and the test pattern region can be removed.

Description

Test pattern formation method of semiconductor device {THE METHOD OF FORMING TEST PATTERNS FOR SEMICONDUCTOR DEVICES}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a test pattern for testing electrical characteristics of a semiconductor device.

In general, a semiconductor substrate on which semiconductor devices are formed is divided into a chip region in which a plurality of cells are formed and a scribe line for dividing the chips. In this case, a plurality of semiconductor devices, for example, transistors, resistors, capacitors, and the like are formed on the chip area, whereas a semiconductor device is not formed on the scribe line.

On the other hand, the semiconductor devices formed on the semiconductor substrate are formed by successively and repeatedly proceeding a plurality of complicated and subsidiary processes such as a diffusion process, a deposition process, and a photo process. Therefore, it is very difficult to measure the characteristics of the semiconductor devices during the manufacturing process. Therefore, in order to test the characteristics of the semiconductor device, test elements, such as a test pattern, are separately formed on the semiconductor substrate. The region where such test elements are formed is called a TEG (Test Element Group) region. In this case, the TEG region may be formed on a separate TEG chip, but recently, it is formed on a scribe line to improve the yield of a semiconductor wafer.

Hereinafter, the test pattern forming method according to the conventional method will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a portion of a semiconductor substrate in which a chip region and a scribe line are divided, and FIGS. 2A to 2D sequentially cut the A1-A2 shown in FIG. 1 to sequentially perform a test pattern forming process according to a conventional method. The cross-sectional views are shown.

Referring to FIG. 1, a semiconductor substrate 100 in which a chip region 20 and a scribe line 30 are divided is prepared. The semiconductor substrate refers to a part of the wafer on which the semiconductor device is formed, and generally uses a silicon substrate. The chip region 20 includes a plurality of cells, and a plurality of semiconductor devices are electrically connected to the inside of the cell. On the other hand, the scribe line 30 is formed to distinguish between the chip regions, and no semiconductor device is formed on the scribe line 30. Accordingly, a step is generated between the chip region 20 and the scribe line 30 by the height of a structure including a semiconductor device formed on the chip region 20.

Referring to FIG. 2A, a structure 102 including a semiconductor device is formed on the chip region of the semiconductor substrate 100 in which the chip region and the scribe line are divided. Since the structure 102 is formed by depositing a plurality of films constituting the semiconductor device, the structure 102 is formed with a specific height difference with respect to the scribe line, that is, a step (T).

2B and 2C, a photoresist (hereinafter referred to as PR, 106) is conformally coated on the entire surface of the semiconductor substrate 100 including the structure 102. The PR 106 is patterned by exposing the PR 106 using a photo mask 108 to form a PR mask 106a on the structure 102. In general, ultraviolet rays formed from mercury and xenon lamps are generally used. A light source passing through the photo mask 106a absorbs light energy on the PR 106 to cause a photochemical reaction and forms a pattern to form a PR mask 106a. Is formed.

Referring to FIG. 2D, the structure 102 and the scribe line on the chip region are etched through the PR mask 106a. By the etching process, patterns 110a and 110b are formed on the structure 102 and the scribe line, and the PR mask 106a is removed. In this case, the etching method is determined according to the film quality and the processing process of the structure 102, and may be performed by wet etching or dry etching.

However, in the test pattern forming method according to the conventional method as described above, the step T is formed between the chip region and the scribe line by the height of the structure 102 due to the structure 102 formed on the chip region. do. Due to the step T, when the PR 106 on the semiconductor substrate 100 is exposed to form the test pattern 110b, a focus difference of a light source occurs between the chip region and the scribe line. The difference in focus on the two areas causes the sizes of the patterns 110a and 110b on the PR mask 106a respectively formed in the two areas to be different. That is, the size of the PR pattern formed on the PR mask 106a of the scribe line as compared to the size of the PR pattern (not shown) formed on the PR mask 106a of the chip region as shown in FIG. 2C. Increases or decreases (ref. A). Accordingly, the size of the pattern formed on the structure 102 and the scribe line is changed through a subsequent etching process. That is, the size of the test pattern 110b formed on the scribe line becomes larger or smaller than the size of the operation pattern 110a formed through the etching process on the structure 102 of the chip region, as shown in FIG. 2D. (Reference B).

In general, the test pattern for inspecting the electrical properties of the operation pattern is preferably formed under the same conditions as the operation pattern in order to ensure the accuracy and reliability of the inspection. However, the test pattern 110b of the semiconductor device formed as described above is formed on a scribe line having a step T having a predetermined height and the structure 102 on which the operation pattern 110a is formed. Different size than 110a). Accordingly, when the characteristics, for example, electrical characteristics, of the semiconductor device are inspected through the test pattern 110b, the test pattern 110b may not have the same condition as the operation pattern 110a of the semiconductor device. The problem arises that the accuracy, precision and reliability of the inspection used are deteriorated.

The present technology provides a method of forming a test pattern of a new semiconductor device that can solve the above problems caused by the size of the test pattern formed on the scribe line of the wafer different from that of the test pattern formed inside the cell. The purpose.

1 is a plan view illustrating a portion of a semiconductor substrate in which chip regions and scribe lines are divided.

2A to 2D are cross-sectional views sequentially illustrating a test pattern forming process according to a conventional method by cutting A1-A2 shown in FIG. 1.

3 is a plan view illustrating a part of a semiconductor substrate in which chip regions, scribe lines, and test pattern regions are divided.

4A to 4D are cross-sectional views sequentially illustrating a test pattern forming process according to the present invention by cutting B1-B2 shown in FIG. 3.

* Brief description of the main parts of the drawing

100, 300: semiconductor substrate 20, 50: chip area

30, 60: scribe line 70: test pattern area

102, 302: first structure 304: second structure

106 and 306 photoresist PR 106a and 306a photoresist mask

108, 308: photo mask

110a, 310a: operation pattern 110b, 310b: test pattern

In order to achieve the above object, a method of forming a test pattern of a semiconductor device disclosed in the present invention includes first and second structures on a semiconductor substrate, which are divided into a chip region, a scribe line, and a test pattern region defined within the scribe line. Wherein, the first structure is formed on the chip region and the second structure is formed on the test pattern region. Applying a photoresist on the entire surface of the semiconductor substrate including the first structure and the second structure and patterning the upper portion of the first structure and the second structure using the photoresist to form a test pattern on the second structure do.

In the present invention, the first structure and the second structure have the same height, and the first structure comprises a semiconductor device.

(Example)

Hereinafter, a test pattern forming method of a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a portion of a semiconductor substrate in which chip regions, scribe lines, and test pattern regions are divided, and FIGS. 4A to 4D are cutouts B1 to B2 shown in FIG. It is sectional drawing which shows a process sequentially.

Referring to FIG. 3, the chip region 50, the scribe line 60, and the test pattern region 70 are divided on the semiconductor substrate 300. The chip region 50 is composed of a plurality of cells, while a plurality of semiconductor devices are electrically connected to each other inside the cells, while the scribe line 60 is formed to distinguish between the chip regions. The semiconductor device is not formed on the scribe line 60. Meanwhile, the test pattern region 70 formed in the scribe line 60 is formed to have a smaller area than the scribe line in the scribe line 60, and the characteristics of the semiconductor device formed in the chip region 50 are defined. To form a test pattern for inspection. Here, the test pattern region refers to a region in which a test pattern is formed in a test element group (TEG) region in which test elements are separately formed in order to test characteristics of a semiconductor device.

Since a plurality of films are deposited on the chip region 50 to form semiconductor devices such as transistors and capacitors to form a first structure, the chip region 50 is formed to have a height greater than that of the scribe line 60. . Therefore, a step is generated between the chip region 50 and the scribe line 60 by the height of the first structure. The second structure having the same height as the first structure including the semiconductor device of the chip region 50 is formed on the test pattern region 70. Therefore, a step is generated between the test pattern region 70 and the scribe line 60 by the height of the second structure, and is formed on the first structure on the chip region 50 and the test pattern region 70. 2 structures are formed with the same height.

Referring to FIG. 4A, first, a first structure 302 including a semiconductor device is formed on a semiconductor substrate 300 where a chip region and a scribe line are divided. The first structure 302 may include a transistor, a capacitor, and the like, and may be formed by depositing a plurality of films constituting semiconductor devices. In this case, a second structure 304 is formed on the test pattern region, and the second structure 304 may be formed at the same time as the first structure 302, or may be separately formed after the first structure 302 is formed. It may be. However, if the second structure 304 is formed separately after the formation of the first structure 302, a separate process for forming the second structure 304 is required, so that the second structure is formed when the first structure 302 is formed. It is desirable to form the structure 304 at the same time. To this end, each of the process steps for forming the first structure 302 is performed, and the films are left inside the test pattern region without removing all of the films deposited in the scribe line. Accordingly, the second structure is formed simultaneously with the first structure, wherein the heights of the first structure 302 and the second structure 304 are between the chip region and the scribe line formed by the first structure 302. It is the same as the step T of.

4B and 4C, first, a PR 306 is conformally coated on the entire surface of the semiconductor substrate including the first structure 302 and the second structure 304. The PR 306 is then exposed and patterned using the photo mask 308 to form a PR mask 306a. Ultraviolet rays formed by mercury, xenon lamps, etc. are generally used as the light source of the exposure process, and the light source passing through the photo mask 306a absorbs light energy on the PR 306 to cause a photochemical reaction and form a PR pattern. The PR mask 306a is formed. At this time, as described above, the first structure and the second structure are formed at the same height so that the focus of the light source is the same during the exposure process. Therefore, the PR patterns formed through the exposure process are all formed in the same size.

Referring to FIG. 4D, patterns PR 310a and 310b are formed by etching the first structure 302 on the chip region and the second structure 304 on the test pattern region through the PR mask 306a. The mask 306a is removed. In this case, an operation pattern 310a of the semiconductor device is formed on the first structure, and a test pattern 310b for inspecting the semiconductor device is formed on the second structure. The operation pattern 310a and the test pattern 310b have the same size according to the PR pattern on the PR mask 306a. The etching process is determined according to a film quality and a processing process forming the first structure 302 and the second structure 304, and may perform wet etching or dry etching.

As described above, in the test pattern forming method of the semiconductor device according to the present invention, a step does not occur between the chip region and the test pattern region. Accordingly, the PR pattern on the first structure 302 and the PR pattern on the second structure 304 because the focus of the light source in the two regions, the chip region and the test pattern region, are matched during the photolithography process for pattern formation. It is formed at the same height, and the operation pattern 310a and the test pattern 310b are formed in the same size. As described above, the test pattern 310b formed to have the same size as the operation pattern 310a may improve inspection precision, accuracy, and reliability of the semiconductor device through inspection of the test pattern.

According to the present invention, the step difference between the chip region and the test pattern region is removed, so that the difference in focus between the chip region and the test pattern region can be eliminated during the photolithography process for forming the test pattern. Accordingly, a pattern having the same size may be formed in the chip region and the test pattern region, and the reliability of the inspection may be secured during the characteristic inspection of the semiconductor device through the test pattern.

Claims (3)

Forming a first structure and a second structure on a semiconductor substrate divided into a chip region, a scribe line, and a test pattern region defined within the scribe line, wherein the first structure is formed on the chip region and the second structure Forming on the test pattern region; Applying a photoresist to the entire surface of the semiconductor substrate including the first structure and the second structure; And forming a test pattern on the second structure by patterning the upper portion of the first structure and the second structure by using the photoresist. The method of claim 1, And wherein the first structure and the second structure have the same height. The method according to claim 1 or 2, And the first structure comprises a semiconductor device.