KR20010065913A - Method for forming flash memory device capable of preventing remain of etched materials - Google Patents
Method for forming flash memory device capable of preventing remain of etched materials Download PDFInfo
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- KR20010065913A KR20010065913A KR1019990066929A KR19990066929A KR20010065913A KR 20010065913 A KR20010065913 A KR 20010065913A KR 1019990066929 A KR1019990066929 A KR 1019990066929A KR 19990066929 A KR19990066929 A KR 19990066929A KR 20010065913 A KR20010065913 A KR 20010065913A
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- etching
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- photoresist pattern
- target layer
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 101150097381 Mtor gene Proteins 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 description 6
- 230000007547 defect Effects 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- Drying Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 메모리 소자 제조 분야에 관한 것으로, 특히 플래쉬 메모리 소자 제조 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of manufacturing a flash memory device.
높은 전압을 운용하는 플래쉬 메모리 소자의 경우는 소자간 분리를 위하여 약 4500 Å 정도의 두꺼운 필드산화막을 형성한다. 이와 같이 두꺼운 필드산화막은 2단의 모양으로 형성되기 때문에 단차를 갖게 되고, 이후 실시되는 적층 게이트 형성을 위한 식각 공정에서 질화막 및 폴리머 등의 식각잔여물이 단차 부분에 남게 된다.In the case of a flash memory device that operates at a high voltage, a thick field oxide film having a thickness of about 4500 Å is formed to separate the devices. Since the thick field oxide film is formed in a two-stage shape as described above, it has a step, and etching residues such as a nitride film and a polymer remain in the stepped portion in an etching process for forming a laminated gate.
첨부된 도면 도1은 종래 기술에 따른 플래쉬 메모리 소자의 적층 게이트 형성이 완료된 상태를 보이는 단면도로서, 필드산화막(11)이 형성된 실리콘 기판(10) 상에 게이트 산화막(12)을 형성하고, 제1 전도막(13), 산화막, 질화막 및 산화막으로 이루어지는 ONO 유전막(14), 제2 전도막(15)을 적층하고, 제2 전도막(15), ONO 유전막(14) 및 제1 전도막(13)을 선택적으로 식각하여 적층 게이트 패턴을 형성한 상태를 보이고 있다.1 is a cross-sectional view illustrating a state in which a stacked gate formation of a flash memory device according to the related art is completed. A gate oxide film 12 is formed on a silicon substrate 10 on which a field oxide film 11 is formed. The ONO dielectric film 14 and the second conductive film 15 each including the conductive film 13, the oxide film, the nitride film, and the oxide film are laminated, and the second conductive film 15, the ONO dielectric film 14, and the first conductive film 13 are stacked. ) Is selectively etched to form a stacked gate pattern.
전술한 식각과정은 실리콘 기판(10) 보호를 위해 게이트 산화막(12)이 실리콘 기판(10) 상에 잔류되도록 하여야 하는 매우 까다로운 공정이다. 이러한 과정에서 식각 방식으로는 이방성 식각을 실시하는데 1000 Å 이상의 단차가 발생한 상태에서 300 Å 미만의 얇은 ONO막을 식각이 이루어진다. 즉, 단차가 발생한 필드산화막(11) 영역과 평탄화된 영역의 식각 타겟(target)이 다르기 때문에 단차 영역에서는 도2a의 SEM 사진에서 보이는 바와 같이 식각시 발생된 폴리머가 잔류하게 될 뿐만 아니라, 질화막의 식각잔여물이 띠 형태(nitride stringer)로 남고 이후 완충산화식각제(buffered oxide etchant, 이하 BOE라 함)를 이용하여 실리콘 기판(10) 상에 잔류된 산화막을 제거하는 공정에서 도2b에 보이는 SEM 사진에서와 같이 머리카락 모양의 디펙트(hair defect)가 잔류하게 되어 소자의 신뢰성에 영향을 미치고 제조 수율을 저하시키는 문제점이 있다.The etching process described above is a very difficult process in which the gate oxide layer 12 must be left on the silicon substrate 10 to protect the silicon substrate 10. In this process, anisotropic etching is performed by etching, and a thin ONO film of less than 300 mW is etched with a step of 1000 mW or more. That is, since the etching targets of the stepped field oxide film 11 region and the planarized region are different from each other, the polymer generated during the etching may not only remain in the stepped region, but also the nitride film may be removed. The SEM residue shown in FIG. 2B in the process of removing the residue left on the silicon substrate 10 using a buffered oxide etchant (hereinafter referred to as BOE) after the etching residue remains in a nitride stringer (nitride stringer) As shown in the photograph, hair defects remain, which affects the reliability of the device and lowers the manufacturing yield.
상기와 같은 문제점을 해결하기 위한 본 발명은 플래쉬 메모리 소자 제조 공정 중 발생한 식각 잔여물을 효과적으로 제거할 수 있는 방법을 제공하는데 그 목적이 있다.An object of the present invention to solve the above problems is to provide a method that can effectively remove the etching residue generated during the flash memory device manufacturing process.
도1은 종래 기술에 따라 플래쉬 메모리 소자의 적층 게이트가 형성된 것을 보이는 공정 단면도,1 is a process cross-sectional view showing a stacked gate of a flash memory device according to the prior art;
도2a 및 도2b는 종래 기술에 따른 플래쉬 메모리 소자의 적층 게이트 형성 과정에서 폴리머와 결함이 발생한 것으로 보이는 SEM 사진,2A and 2B are SEM photographs showing that polymers and defects are generated in a process of forming a stacked gate of a flash memory device according to the prior art;
도3a 및 도3b는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 유전막 제거 공정 후의 상태를 보이는 SEM 사진.3A and 3B are SEM photographs showing a state after the dielectric film removing process of the flash memory device according to the embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
10: 반도체 기판 11: 필드산화막10: semiconductor substrate 11: field oxide film
12: 게이트 산화막 13: 제1 전도막12: gate oxide film 13: first conductive film
14: 유전막 PR: 제2 전도막14: dielectric film PR: second conductive film
상기와 같은 목적을 달성하기 위한 본 발명은 단차를 갖는 필드산화막 형성이 완료된 실리콘 기판 상에 식각대상막을 형성하는 제1 단계; 상기 식각대상막 상에 포토레지스트 패턴을 형성하는 제2 단계; 상기 포토레지스트 패턴을 식각마스크로 상기 식각대상막을 등방성 식각하는 제3 단계; 상기 제3 단계가 완료된 상기 실리콘 기판을 BOE 용액으로 처리하는 제4 단계; 상기 포토레지스트 패턴을 제거하는 제5 단계; 및 세정공정을 실시하는 제6 단계를 포함하는 반도체 메모리 소자 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming an etching target film on the silicon substrate is completed to form a field oxide film having a step; Forming a photoresist pattern on the etching target layer; A third step of isotropically etching the etching target layer using the photoresist pattern as an etching mask; A fourth step of treating the silicon substrate on which the third step is completed with a BOE solution; A fifth step of removing the photoresist pattern; And it provides a semiconductor memory device manufacturing method comprising a sixth step of performing a cleaning process.
본 발명은 단차를 갖는 필드산화막 형성이 완료된 반도체 기판 상에 형성된 식각대상층을 포토레지스트 패턴을 식각마스크로 등방성 식각하여 기판 상부에 잔류하는 산화막을 조절하면서 식각 중에 발생하는 폴리머 및 식각잔여물을 효과적으로 제거하는 특징이 있다. 이와 같은 등방성 식각 후에는 완충산화식각제로 처리한 다음 포토레지스트 패턴을 제거하고 세정 공정을 실시하는데 다른 특징이 있다. 상기 식각대상층은 ONO막을 포함한다.The present invention effectively removes polymers and etching residues generated during etching by isotropically etching a photoresist pattern with an etching mask on an etching target layer formed on a semiconductor substrate having a stepped field oxide film formed thereon with an etching mask. There is a characteristic. After such isotropic etching, there is another characteristic of treating with a buffered oxidation etchant, removing a photoresist pattern, and performing a cleaning process. The etching target layer includes an ONO layer.
본 발명의 제1 실시예에서는 상기 식각대상층을 등방성 건식식각하고, BOE 용액으로 처리한 다음, 식각마스크로 이용된 포토레지스트 패턴을 제거하고 세정 공정을 실시한다.In the first embodiment of the present invention, the etching target layer is isotropically dry etched, treated with a BOE solution, a photoresist pattern used as an etch mask is removed, and a cleaning process is performed.
본 발명의 제2 실시예에서는 습식식각 및 이방성 건식식각으로 식각대상층을 식각하고, BOE 용액으로 처리한 다음, 식각마스크로 이용된 포토레지스트 패턴을 제거하고 세정 공정을 실시한다. 예로서 ONO막을 식각하는 경우 제1 산화막은 BOE를 이용한 습식식각으로 제거하여 질화막에서 식각이 멈추도록 하고, 그 하부의 질화막 및 제2 산화막은 이방성 건식식각으로 제거하여 기판 상부에 잔류하는 산화막의 두께를 조절한다.In the second embodiment of the present invention, the etching target layer is etched by wet etching and anisotropic dry etching, treated with a BOE solution, and then a photoresist pattern used as an etching mask is removed and a cleaning process is performed. For example, when the ONO film is etched, the first oxide film is removed by wet etching using BOE to stop the etching from the nitride film, and the nitride film and the second oxide film below are removed by anisotropic dry etching, thereby remaining the thickness of the oxide film remaining on the substrate. Adjust
본 발명의 제3 실시예에서는 등방성 건식식각 및 이방성 건식식각을 인시튜(in-situ)로 실시하고, BOE 용액으로 처리한 다음, 식각마스크로 이용된 포토레지스트 패턴을 제거하고 세정 공정을 실시한다.In the third embodiment of the present invention, isotropic dry etching and anisotropic dry etching are performed in-situ, treated with a BOE solution, and then a photoresist pattern used as an etching mask is removed and a cleaning process is performed. .
전술한 본 발명의 제1 실시예 및 제3 실시예에서 등방성 건식식각은 ICP(inductively coupled plasma), 마이크로 웨이브 다운 스트림 (microwave downstream), ECR(electron cyclotron resonance), TCP(transformer coupled plasma) 또는 HELICAL 방식의 플라즈마 소스를 이용하여 실시하며, 식각가스로는 CF4, CHF3, C2F6, CH2F2, C3F8, C5F8, NF3등과 같은 불소계 가스를 주식각 가스로 이용한다. 상기 등방성 식각은 200 mTorr 내지 2000 mTorr의 압력, 0 ℃ 내지 100 ℃ 범위의 전극 온도 조건에서 50 sccm 내지 300 sccm의 CF4가스를 주입하고 100 W 내지 500 W 범위의 RF 전력을 인가하여 실시한다.In the above-described first and third embodiments of the present invention, the isotropic dry etching is performed by inductively coupled plasma (ICP), microwave downstream, electron cyclotron resonance (ECR), transformer coupled plasma (TCP) or HELICAL. It is carried out using a plasma method of the type, and as an etching gas, fluorine-based gas such as CF 4 , CHF 3 , C 2 F 6 , CH 2 F 2 , C 3 F 8 , C 5 F 8 , NF 3, etc. I use it. The isotropic etching is performed by injecting CF 4 gas of 50 sccm to 300 sccm at a pressure of 200 mTorr to 2000 mTorr and an electrode temperature of 0 ° C. to 100 ° C., and applying RF power in a range of 100 W to 500 W.
상기 식각대상막은 200 Å 내지 300 Å 두께의 ONO막일 수도 있으며, 이 경우 발생된 폴리머를 효과적으로 제거하기 위하여 상기 식각가스에 O2가스를 첨가할 수도 있다.The etching target film may be an ONO film having a thickness of 200 kPa to 300 kPa, and in this case, O 2 gas may be added to the etching gas in order to effectively remove the generated polymer.
한편, 상기 등방성 식각은 낮은 식각선택비에서 1차 식각을 실시하고, 실린콘 기판 상부의 산화막이 제거되지 않을 정도의 높은 식각선택비로 2차 식각 공정을 실시하여 1차 식각 공정에서 발생한 질화막 잔여물 또는 폴리머를 제거하기도 한다.On the other hand, the isotropic etching is performed by the first etching at a low etching selectivity, the second etching process at a high etching selectivity such that the oxide layer on the silicon substrate is not removed, the nitride film residues generated in the first etching process Or remove the polymer.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 식각잔여물 및 결함 발생을 효과적으로 억제할 수 있어 소자의 전기적 특성 향상, 수율증가 및 신뢰성 증대를 가져올 수 있다.The present invention made as described above can effectively suppress the occurrence of etching residues and defects can lead to improved electrical properties, increased yield and increased reliability of the device.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066929A KR20010065913A (en) | 1999-12-30 | 1999-12-30 | Method for forming flash memory device capable of preventing remain of etched materials |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990066929A KR20010065913A (en) | 1999-12-30 | 1999-12-30 | Method for forming flash memory device capable of preventing remain of etched materials |
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| KR20010065913A true KR20010065913A (en) | 2001-07-11 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100489535B1 (en) * | 2002-09-10 | 2005-05-16 | 동부아남반도체 주식회사 | Method for etching ono sidewall using helical resonance source |
| KR100661232B1 (en) * | 2004-12-31 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Method for removing the ONO residue in flash device |
-
1999
- 1999-12-30 KR KR1019990066929A patent/KR20010065913A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100489535B1 (en) * | 2002-09-10 | 2005-05-16 | 동부아남반도체 주식회사 | Method for etching ono sidewall using helical resonance source |
| KR100661232B1 (en) * | 2004-12-31 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Method for removing the ONO residue in flash device |
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