KR20010064518A - Low Data Delay Variation in Column Selection - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to improve the output speed by minimizing data variation due to delay on an Y cell select line(YSEL), even when the cell array is increased in a column direction. CONSTITUTION: The semiconductor memory device includes a plurality of bit line sense amplifiers(300), a plurality of memory cell arrays(310) and a cell array decoder(400). The bit line sense amplifiers and the memory cell arrays are allocated one by one in series ad cross with a plurality of Y cell select lines(YSEL) extended from an Y decoder. Word lines(WL) of the memory cell arrays are formed to cross the Y cell select lines extended from the Y decoder. The cell array decoder receives a cell array select signal(MAT) and outputs a cell array coding signal(MAT-X) to the bit line sense amplifiers. The cell array decoder further includes the first schmidt trigger, the first through (n-1)th OR gates and the second schmidt trigger.

Description

Semiconductor memory device {Low Data Delay Variation in Column Selection}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can effectively reduce the delay of data transfer that occurs when the degree of integration of a semiconductor cell increases.

In general, when the density of semiconductor cells is increased, the data transfer time is increased due to the increase in the resistance and capacitance of one column select line, and thus, the delay width is large when the distance of each selected cell is too long, resulting in an increase in overall data transfer. .

1 is a circuit diagram of a conventional semiconductor memory device, FIG. 2 is a detailed circuit diagram of the bit line connection unit of FIG. 1, and FIG. 3 is an operation waveform diagram of YSEL1 of a conventional semiconductor memory device.

In a conventional semiconductor memory device, a plurality of bit line sense amplifier units 10 and a plurality of memory cell arrays 20 are sequentially positioned to cross a plurality of Y cell select lines YSEL from the Y decoder unit 30. The plurality of memory cell arrays 20 are formed such that each word line WL intersects a plurality of Y cell select lines YSEL from the Y decoder unit 30. In this case, the number of bit line sense amplifier units 10 that each Y cell select line YSEL is responsible for is determined by the size of the semiconductor memory device.

A plurality of switching transistors S1 positioned at the bit line BLT connection portion 100 where the bit line sense amplifier unit 10 and the Y cell select line 1 YSEL1 meet each other may have a Y cell select line 1 (YSEL1) at a gate thereof. The bit line is connected to the source through each bit line sense amplifier (BLSA) and bit line (BIT) in the bit line sense amplifier unit 10, and the drain is connected to the data line (LIO).

Referring to the operation of the conventional semiconductor memory device, when the data of the memory cell array 20 selected by the word line 1 WL1 is loaded on the bit line BIT, the memory cell array having the word line 1 WL1 ( Based on the reference numeral 20), cell data is loaded on the upper and lower bit line sense amplifier units 10. When the bit line 1 (BIT-1) and the inverted bit line 1 (BITb-1) are opened, the read operation is performed to read the data in the sense amplifier unit 10 to the data line LIO. Done. At this time, when a read signal is input from the outside, the Y decoder unit 30 is coded to enable the Y cell select line YSELn to read and output data contained in the bit line 1 (BIT-1) to the data line LIO. do. That is, when the Y cell select line 1 (YSEL1) is selected, the plurality of switching transistors S1 positioned at the bit line BLT connection unit 100 are 'turned on' and the bit line 1 (BIT−) is applied to the data line 1 LIO-1. Pass the data of 1). In addition, even if word line 2 (WL2) or word line n (WLn) is selected, the plurality of switching transistors 2 (S2) or switching transistors n (Sn) selected by the Y-cell selection line 1 (YSEL1) are 'turned on' to thereby turn on the data line. The data of bit line 2 (BIT-2) is transferred to 2 (LIO-2) or the data of bit line n (BIT-n) is transferred to data line n (LIO-n).

However, in the related art, the difference between the data output when the word line 1 WL1 is selected and the word line n WLn is increased in proportion to the size of the gate load of the switching transistor. That is, as the array of memory cells grows larger, it becomes difficult to control data output through the data line LIO.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional device, and provides a semiconductor memory device capable of effectively controlling data output through a data line (LIO) even when an array of memory cells becomes larger and more integrated. have.

A semiconductor memory device according to the present invention for achieving the above object is a plurality of bit line sense amplifier unit, a plurality of memory cell array, the plurality of bit line sense amplifier unit and a plurality of memory cell array are sequentially positioned To cross the plurality of Y cell selection lines YSEL that are outputs of the Y decoder unit, and the word lines WL of the plurality of memory cell arrays cross the Y cell selection line YSEL of the Y decoder unit. And a cell array decoder configured to receive a cell array selection signal MAT and output a cell array coding signal MAT-X to the plurality of bit line sense amplifier units to control the Y cell selection line YSEL. To change the output of the data generated by the gate load of the switching transistor when different word lines WL are selected. There is provided a semiconductor memory device according to digestion.

1 is a circuit diagram of a conventional semiconductor memory device.

FIG. 2 is a detailed circuit diagram of the bit line connection unit of FIG. 1. FIG.

3 is an operation waveform diagram of YSEL1 of a conventional semiconductor memory device.

4 is a circuit diagram of a semiconductor memory device according to the present invention.

FIG. 5 is a detailed circuit diagram of the bit line connection unit of FIG. 4. FIG.

6 is an operation waveform diagram of YSEL1 of the semiconductor memory device according to the present invention;

Explanation of symbols on the main parts of the drawings

WL: Word Line

10, 300: bit line sense emulator part (BLSA)

20, 310: memory cell array 30, 400: Y decoder section

100, 200: Bit line (BLT) connection part BIT: Bit line

LIO: Data line YSEL: Y cell selection line

MAT: Cell Array Selection Signal MAT-X: Cell Array Coating Signal

STR1, STR2: Schmitt trigger OR1 to ORn-1: OR gate

S1-Sn: Switching Transistor J1-Jn: NMOS Transistor

Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a circuit diagram of a semiconductor memory device according to the present invention.

In the semiconductor memory device according to the present invention, n bit line sense amplifier units 300, n-1 memory cell arrays 310, and n bit line sense amplifier units 300 and n-1 units are provided. The Y decoder unit 400 having the memory cell array 310 sequentially intersects and outputs the Y cell selection line YSEL, and the plurality of bit line sense amplifier units 210 to the cell array selection signal ( And a cell array decoder 210 which receives a MAT and outputs cell array coding signals MAT-X to the plurality of bit line sense amplifier units 300, respectively.

The cell array decoder 210 receives a cell array selection signal 1 MAT1 and outputs a first Schmitt trigger STR1 for outputting a cell array coding signal 1 MAT-X1, and a cell array selection signal 1 MAT1. A first OR gate for receiving two cell array selection signals n (MATn) sequentially and outputting the cell array coding signals n-1 (MAT-Xn-1) to the cell array coding signals n-1 (MAT-Xn-1). OR1) to n-1 OR gates ORn-1 and a second Schmitt trigger STR2 that receives the cell array selection signal n (MATn) and outputs the cell array coding signal n (MAT-Xn). .

FIG. 5 is a detailed circuit diagram illustrating the bit line (BLT) connection of FIG. 4.

The source 200 is connected to the bit line BLT of the bit line sense amplifier unit 300 by crossing the data line with the data line LIO and the Y cell select line 1 YSEL1, and the drain is the bit line BIT. A plurality of switching transistors S1 connected to each other,

Y cell select line 1 (YSEL1) is connected to the source, cell array coding signal 1 (MAT-X1) is applied to the gate, and a plurality of NMOS transistors 1 (connected to the gates of the plurality of switching transistors S1, respectively). J1).

In addition, the voltage level of the cell array coding signal 1 (MAT-X1) is applied at a level equal to or higher than the threshold voltage of the NMOS transistor higher than the Y cell select line 1 (YSEL1), and the size of the NMOS transistor 1 (J1) is the switching transistor S1. Form about 1/3 of the size.

6 is an operational waveform diagram of YSEL1 of the semiconductor memory device according to the present invention.

An operation process of the semiconductor memory device according to the present invention is as follows. When data of the memory cell array 310 selected by the word line 1 WL1 is loaded on the bit line BIT, the upper and lower bit lines based on the memory cell array 310 having the word line 1 WL1. Cell data is loaded onto the sense amplifier unit 300 to be amplified and stored. When the bit line 1 (BIT-1) and the inverted bit line 1 (BITb-1) are opened, a read operation for reading data in the sense amplifier unit 300 to the data line LIO is performed. . In this case, only the cell array coding signal 1 MAT-X1 and the cell array coding signal 2 MAT-X2 are enabled by receiving the cell array selection signal 1 MAT1 for selecting one memory cell array 310. The NMOS transistors 1 J1 and the NMOS transistors 2 J2 are 'turned on' by the cell array coding signal 1 (MAT-X1) and the cell array coding signal 2 (MAT-X2).

Next, when a read signal is input from the outside and the Y cell selection line 1 (YSEL1) is selected, the plurality of switching transistors S1 positioned at the bit line BLT connection unit 200 are 'turned on' to the data line 1 (LIO-1). The data of bit line 1 (BIT-1) is transferred. The Y cell select line 1 (YSEL1) has only a load from the plurality of NMOS transistors 3 J3 to the plurality of NMOS transistors n (Jn). That is, the NMOS transistor J is smaller than the switching transistor S by one-third in size, so that the load of the NMOS transistor is reduced (1/9) in proportion to the square of the size, thereby reducing the variation of the output data.

Therefore, the present invention has the effect of minimizing data variation due to delay of the Y cell select line YSEL and improving the output speed even when the cell array increases toward the column.

Claims (4)

A plurality of bit line sense amplifier units and a plurality of memory cell arrays are sequentially positioned to cross the plurality of Y cell select lines YSEL from the Y decoder unit, and the word lines WL of the plurality of memory cell arrays are Y. In the semiconductor memory device formed to intersect the Y cell select line (YSEL) from the decoder unit, A cell array decoder for receiving a cell array selection signal MAT and outputting a cell array coding signal MAT-X to the plurality of bit line sense amplifier units is further provided to control the Y cell selection line YSEL. A semiconductor memory device characterized in that. The method of claim 1, wherein the cell array decoder unit A first Schmitt trigger STR1 for receiving the cell array selection signal 1 MAT1 and outputting the cell array coding signal 1 MAT-X1; Two cell array selection signals n (MATn) are sequentially input from the cell array selection signal 1 (MAT1) to the cell array coding signals 2 (MAT-X2) to cell array coding signals n-1 (MAT-Xn-1). First OR gate OR1 to n-1 OR gates ORn-1 for outputting And a second Schmitt trigger (STR2) for receiving the cell array selection signal n (MATn) and outputting the cell array coding signal n (MAT-Xn). The method of claim 1, wherein the bit line sense emperor unit The source is connected to the data line (LIO) and the Y cell select line (YSEL) cross-connected, the drain is a bit line (BIT) and a plurality of switching transistors, The Y cell select line YSE1 is connected to the source, the cell array coding signal MAT-X is applied to the gate, and the drain includes a plurality of NMOS transistors connected to the gates of the plurality of switching transistors, respectively. Semiconductor memory device. The method of claim 3, wherein the plurality of NMOS transistors A semiconductor memory device characterized in that formed about one third the size of the switching transistor.