KR20010064411A - Tft-lcd - Google Patents

Abstract

PURPOSE: A TFT-LCD is provided to be capable of preventing the spot defect. CONSTITUTION: A plurality of gate bus lines(21) are arranged to transversely cross unit pixel spaces defined on an array substrate. A plurality of data bus lines(26) are arranged on the array substrate to lengthwise cross the unit pixel spaces while crossing the gate bus lines. Storage electrodes(22) are parallel to the gate bus lines, and are respectively arranged between a pair of adjacent bate bus lines. Pixel electrodes(27) are arranged in the unit pixel spaces to be partially overlapped with the storage electrodes. Four TFTs(TFT1-4) are arranged near cross points between the gate bus lines and the data bus lines, and are formed on left/right and upper/lower sides of the gate and data bus lines to be contacted to one pixel electrode.

Description

Thin film transistor-liquid crystal display device {TFT-LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor-liquid crystal display device, and more particularly, to a thin film transistor-liquid crystal display device (hereinafter referred to as TFT-LCD) capable of preventing variations in pixel voltage variation and improving image quality characteristics. .

An active matrix liquid crystal display device in which a thin film transistor is used as an active device is thin, light, and has a large number of pixels, and thus has an image quality characteristic comparable to that of a CRT.

1 is a plan view of a general TFT-LCD.

As shown in the figure, a plurality of gate bus lines 12 are disposed on the array substrate 10 at equal intervals. A plurality of data bus lines 14 are disposed on the array substrate 10 so as to intersect with the gate bus lines 12 so that unit pixels are defined. The thin film transistors 15 are disposed at the intersections of the gate bus line 12 and the data bus line 14, respectively. In this case, the thin film transistor 15 may include a gate electrode 12a extending from the gate bus line 12 to a unit pixel region, a channel layer 16 disposed on the gate electrode 12a, and a data bus line 14. ) And a source electrode 14a extending to overlap one side of the channel layer 16 and a drain electrode 14b formed to overlap the other side of the channel layer 16. The pixel electrode 18 is formed in each unit pixel region so as to be in contact with the drain electrode 14b of the thin film transistor 15.

However, in the conventional TFT-LCD, as shown in FIG. 1, one pixel electrode 18 is switched by one thin film transistor 15 provided at the intersection of the gate bus line 12 and the data bus line 14. It was configured to be. Accordingly, due to the height of the gate bus line 12 of the thin film transistor 15, a short occurs frequently in the source and drain electrodes 14a and 14b in the manufacturing process. For this reason, when the thin film transistor 15 is short-circuited, a signal is not transmitted to the pixel electrode 18, and a point defect arises.

Accordingly, it is an object of the present invention to provide a thin film transistor-liquid crystal display device capable of preventing the occurrence of point defects.

1 is a plan view of a typical thin film transistor-liquid crystal display element.

2 is a plan view of a thin film transistor-liquid crystal display device according to an embodiment of the present invention.

3 is a plan view of a thin film transistor-liquid crystal display device according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

20-Array Board 21-Gate Bus Line

21a-gate electrode 22-storage electrode

26-data bus line 26a-drain electrode

26b-source electrode 27,270-pixel electrode

In order to achieve the above object of the present invention, the present invention provides an array substrate having a limited unit pixel space; A plurality of gate bus lines arranged on the array substrate to traverse unit pixel spaces, respectively; A plurality of data bus lines arranged on an array substrate to cross the gate bus lines and terminate the unit pixel space; A storage electrode parallel to the gate bus line and disposed between a pair of adjacent gate bus lines; A pixel electrode partially overlapping the storage electrode and disposed in the unit pixel space; And four thin film transistors disposed at intersections of the gate bus line and the data bus line, and formed in up, down, left, and right directions with respect to the gate bus line and the data bus line, respectively and contacted with one pixel electrode. The pixel electrode is connected to two thin film transistors formed on one circumferential surface of the gate bus line, the first pixel electrode disposed on one side of the gate bus line, and the other two thin film transistors formed on the migration surface of the gate bus line. And a second pixel electrode disposed on the other side of the gate bus line.

In addition, the present invention provides an array substrate having a limited unit pixel space; A plurality of gate bus lines arranged on the array substrate to traverse unit pixel spaces, respectively; A plurality of data bus lines arranged on an array substrate to cross the gate bus lines and terminate the unit pixel space; A storage electrode parallel to the gate bus line and disposed between the adjacent pair of gate bus lines; a pixel electrode partially overlapping the storage electrode and disposed in the unit pixel space; And four thin film transistors disposed at intersections of the gate bus line and the data bus line, and formed in up, down, left, and right directions with respect to the gate bus line and the data bus line, respectively and contacted with one pixel electrode. The pixel electrode includes four pixel electrodes individually connected to each thin film transistor.

According to the present invention, at the center of the unit pixel, as a switching element for controlling one pixel electrode, four TFTs having a common drain electrode are formed, and at least two or more pixel electrodes in the unit pixel so as to be connected to each of these TFTs. Is formed.

Accordingly, even if a fail occurs in any one TFT, the pixel electrode can be selectively operated by a TFT in which the remaining fail does not occur. Accordingly, the screen defect can be prevented.

(Example)

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view of a TFT-LCD for explaining an embodiment of the present invention, and FIG. 3 is a plan view of a TFT-LCD for explaining another embodiment of the present invention.

First, referring to FIG. 2, a plurality of gate bus lines 21 and storage electrodes 22 extend parallel to each other in the x direction of the drawing on an array substrate 20 on which unit pixels pix are defined. The storage electrodes 22 are disposed between a pair of adjacent gate bus lines 21, and the gate bus lines 21 are disposed between the storage electrodes 22, respectively. That is, the gate bus line 21 traverses each unit pixel pix in the x direction, and the storage electrode 22 borders the unit pixel pix in the y direction. In this case, the gate bus line 21 includes a gate electrode portion 21a that will serve as a gate electrode of the thin film transistor, and the gate electrode portion 21a has a wider line width than other gate bus line 21 portions. . In addition, a channel layer (not shown) is provided on the gate electrode 21a.

The data bus line 26 is arranged to intersect with the gate bus line 21. In this case, in particular, the data bus line 26 passes through the gate electrode portion 21a of the gate bus line 21, terminates the inside of the unit pixel pix, and is electrically insulated from the gate bus line 21. The drain electrode 26a is branched from the data bus line 26, and is disposed to intersect the data bus line 26 at a portion where the data bus line 26 and the gate electrode portion 21a intersect with each other. That is, the length is shorter than the gate electrode portion 21a. The source electrode 26b is formed at the same time as the data bus line 26 and the drain electrode 26a, and is referred to both sides of the drain electrode 26a, preferably based on the drain electrode 26a and the data bus line 26. It is formed to overlap the edge of the gate electrode portion 21 while being disposed up, down, left and right. At this time, as described above, the source electrode 26b is disposed at four diagonal portions at the intersection of the data bus line 26 and the drain electrode 26a, respectively, so that the gate bus line 21 and the data bus line are located. Four TFTs (TFT1 to 4) are formed near the intersection point of (26).

The pixel electrodes 27 are formed in the unit pixel space of the matrix form on the array substrate 20, respectively. The pixel electrode 27 contacts the first and second TFTs TFT1 and TFT2 provided on the upper side of the gate electrode 21a, preferably the first pixel electrode 27a that contacts the source electrode 26b of each TFT. ) And a second pixel electrode 27b contacting the third and fourth TFTs TFT3 and TFT4 provided below the gate electrode 21a, preferably the source electrode 26b of each TFT. do. In addition, the first and second pixel electrodes 27a and 27b are symmetrical with respect to the gate bus line 21, and are spaced apart from the gate bus line 21 by a predetermined distance. In addition, the first and second pixel electrodes 27a and 27b are electrically insulated from the gate bus line 21 and the data bus line 26, and the first and second electrodes 27a and 27b are electrically insulated from each other. do.

At this time, the y-direction boundary surfaces of the pixel electrodes 27a and 27b overlap a predetermined portion of the pair of adjacent storage electrodes 22 to form a storage capacitor. Preferably, the width at which the first and second pixel electrodes 27a and 27b overlap with one storage electrode 22 is about 1/2 or less of the width of the storage electrode 22.

When the thin film transistor-liquid crystal display element is constituted as described above, the first and second pixel electrodes 27a and 27b are divided and formed in one unit pixel, and each pixel electrode 27a and 27b is formed of two TFTs and one TFT. Since it is connected, even if a defect occurs in any one of the TFTs TFT1 to TFT4, the other TFT in which the defect does not occur acts as a switching element, thereby preventing the pixel electrode from failing due to the TFT failing.

Referring to Fig. 3, another embodiment of the present invention will be described.

Since the embodiment has the same shape as the gate bus line 21, the data bus line 26, the drain electrode 26a, the source electrode 26b, and the storage electrode 22, the present embodiment is similar to this embodiment. The redundant description will be omitted, and only the pixel electrode structure different from the above embodiment will be described.

In the present exemplary embodiment, the pixel electrode 270 includes a first pixel electrode 270a in contact with each of the first TFTs TFT1, a second pixel electrode 270b in contact with the second TFT TFT2, And a third pixel electrode 270c in contact with the third TFT (TFT3) and a fourth pixel electrode 270d in contact with the fourth TFT (TFT4), and the first to fourth pixel electrodes 270a to 270d are all It is arranged in a unit pixel. In this case, the first to fourth pixel electrodes 270a to 270d are symmetrical with respect to the data bus line 26 while being symmetrical with respect to the gate bus line 21. In addition, the first to fourth pixel electrodes 270a to 270d are electrically insulated from the gate bus line 21 and the data bus line 26 by a predetermined distance. In addition, each of the first to fourth pixel electrodes 270a to 270d is also insulated from each other.

In addition, the y-direction boundary surfaces of the first to fourth pixel electrodes 270a to 270d partially overlap with a pair of adjacent storage electrodes 22 to form a storage capacitor. Preferably, the width at which the first and second pixel electrodes 27a and 27b overlap with one storage electrode 22 is about 1/2 or less of the width of the storage electrode 22.

When the pixel electrode 270 is constituted in this manner, since the pixel electrodes in the unit pixel pix are divided into four, even if any TFT is shorted, the remaining three TFTs are operated and the pixel electrodes connected to them are operated. . At this time, since the human eye is not delicate enough to identify the unit pixel, even if a quarter of all the pixel electrodes are not operated, it is difficult to recognize it, and thus it is not seen as caustic.

As described in detail above, according to the present invention, in the center of the unit pixel, as a switching element for controlling one pixel electrode, four TFTs having a common drain electrode are formed, and the unit is connected to each of these TFTs. At least two or more pixel electrodes are formed in the pixel.

Accordingly, even if a fail occurs in any one TFT, the pixel electrode can be selectively operated by a TFT in which the remaining fail does not occur. Accordingly, the screen defect can be prevented.

Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (12)

An array substrate having a unit pixel space defined therein; A plurality of gate bus lines arranged on the array substrate to traverse unit pixel spaces, respectively; A plurality of data bus lines arranged on an array substrate to cross the gate bus lines and terminate the unit pixel space; A storage electrode parallel to the gate bus line and disposed between a pair of adjacent gate bus lines; A pixel electrode partially overlapping the storage electrode and disposed in the unit pixel space; Is disposed at the intersection of the gate bus line and the data bus line, and includes four thin film transistors which are formed in the vertical and horizontal directions with respect to the gate bus line and the data bus line, respectively, and are in contact with one pixel electrode. The pixel electrode is connected to two thin film transistors formed on one circumferential surface of the gate bus line, and is connected to a first pixel electrode disposed on one side of the gate bus line and the other two thin film transistors formed on the migration surface of the gate bus line. And a second pixel electrode disposed on the other side of the gate bus line. The semiconductor device of claim 1, wherein the four thin film transistors include: a channel layer overlapping a predetermined portion of a gate bus line; A drain electrode extending from the data bus line in parallel with a gate bus line and disposed in the center of the channel layer; Four source electrodes formed on both sides of the drain electrode to be in contact with the channel layer and the pixel electrode, wherein the drain electrode has a length shorter than a long width of a rectangular groove, and the source electrode has a drain electrode and a data bus line. The thin film transistor-liquid crystal display element which is arrange | positioned respectively up, down, left, and right as a reference. 3. The thin film transistor-liquid crystal display device of claim 2, wherein the gate bus line on which the channel layer is formed is a gate electrode of the thin film transistor, and has a relatively wider width than the gate bus line on which the channel layer is not formed. 2. The thin film transistor-liquid crystal of claim 1, wherein portions of one side of the first and second pixel electrodes overlap by a width equal to or less than one-half the width of the line width of the pair of adjacent storage electrodes and the storage electrode. Display elements. The thin film transistor-liquid crystal display device of claim 1, wherein the first and second pixel electrodes are symmetrically disposed with respect to a gate bus line. 6. The thin film transistor-liquid crystal display device according to claim 5, wherein the first and second pixel electrodes are electrically insulated. An array substrate having a unit pixel space defined therein; A plurality of gate bus lines arranged on the array substrate to traverse unit pixel spaces, respectively; A plurality of data bus lines arranged on an array substrate to cross the gate bus lines and terminate the unit pixel space; A storage electrode parallel to the gate bus line and disposed between a pair of adjacent gate bus lines; A pixel electrode partially overlapping the storage electrode and disposed in the unit pixel space; Is disposed at the intersection of the gate bus line and the data bus line, and includes four thin film transistors which are formed in the vertical and horizontal directions with respect to the gate bus line and the data bus line, respectively, and are in contact with one pixel electrode. And the pixel electrode includes four pixel electrodes individually connected to each of the thin film transistors. 8. The semiconductor device of claim 7, wherein the four thin film transistors comprise: a channel layer overlapping a predetermined portion of a gate bus line; A drain electrode extending from the data bus line in parallel with a gate bus line and disposed in the center of the channel layer; Four source electrodes formed on both sides of the drain electrode to be in contact with the channel layer and the pixel electrode, wherein the drain electrode has a length shorter than a long width of a rectangular groove, and the source electrode has a drain electrode and a data bus line. The thin film transistor-liquid crystal display element which is arrange | positioned respectively up, down, left, and right as a reference. 9. The thin film transistor-liquid crystal display device according to claim 8, wherein the gate bus line on which the channel layer is formed is a gate electrode of the thin film transistor, and has a relatively wider width than the gate bus line on which the channel layer is not formed. 8. The liquid crystal display of claim 7, wherein each of the four pixel electrodes overlaps one pair of storage electrodes adjacent to one end thereof by a width equal to or less than half the line width of the storage electrode. device. 8. The thin film transistor-liquid crystal display device according to claim 7, wherein the four pixel electrodes are symmetrical with respect to the data bus line while being symmetrical with respect to the gate bus line. 12. The thin film transistor-liquid crystal display device according to claim 11, wherein the four pixel electrodes are electrically insulated from each other.