KR20010064313A - Optical Disc Recording/Reproducing Apparatus - Google Patents

Abstract

PURPOSE: An optical disk recorder/reproducer is provided to reproduce channel clock and channel bit stream by using a signal track to indicate a same phase and a different phase alternatively. CONSTITUTION: A wobble signal detecting part(22) detects wobble signal of same phase from an optical disk which has a signal track formed to have a same phase and a different phase alternatively. A phase synchronization loop has a frequency phase comparison device(30) to generate oscillation clock that follows frequency and phase of wobble signal of same phase from the wobble signal detecting part. A control part makes a disable the frequency phase comparison device(30) periodically responding wobble signal of same phase from the wobble signal detecting part(22). A synchronization part restores a channel bit stream and a channel bit clock from the wobble signal using the oscillation clock. The optical recording/regeneration apparatus of frame wobbling method has a wobble signal detector(22), an edge detector(24), and the first and the second delay device(26,28) to be connected commonly with the edge detector(24).

Description

Optical Disc Recording / Reproducing Apparatus

The present invention relates to a recording / reproducing apparatus for accessing an optical disc, and more particularly, to an optical disc recording / reproducing apparatus suitable for accessing an optical disc of a frame wobbling method in which an in-phase wobbling region and a two-phase wobble region are formed in a track. .

Recently, optical recording media, magneto-optical recording media, and the like have been developed and commercialized as recording media for recording various kinds of information such as video and audio information. Among them, optical recording media include discs for reproduction such as CD-ROM and DVD-ROM, including generalized CD, WORM (Write Once Read Memory) type such as CD-R and DVD-R, CD-RW and DVD- Recordable discs, such as RAM, have been popularized or developed.

In a conventional recordable disc, identification information including address information or the like is recorded in advance so that information can be recorded in a desired position. In fact, an optical disc such as a CD-R is provided with a mountain signal track and a valley signal track, and the signal track of the valley is wobbling in accordance with a carrier signal in which identification information including address information and the like is frequency-modulated. It is formatted. Thus, address information can be read from the wobbled area on the signal track of the goal, and information can be recorded at a desired position on the disc based on the address information. However, in this type of disc, since the information can be recorded only on the signal track of the goal, the recording capacity of the information is limited.

In contrast, optical discs such as DVD-RAM allow information to be recorded on both mountain and valley signal tracks. The disc includes recording areas consisting of signal tracks of peaks and valleys wobbling in phase with header areas in which ID information including address information and the like is recorded in the form of prepit rows. In this type of disc, since the information cannot be recorded in the header field consisting of the prepit rows, the recording capacity is limited.

In order to prevent the recording capacity from being limited in this way, the present applicant has proposed a frame wobbling type optical disc through Korean Patent Application No. "98-32977". In the optical disc disclosed in Korean Patent Application No. 98-32977, the in-phase wobbling area 14A and the out-of-phase wobbling area 14B are alternately shown on each of the mountain and valley signal tracks 10 and 12 as shown in FIG. do. The in-phase wobbling area 14A and the out-of-phase wobbling area 14B appear once in the unit information recording area (i.e., sector or frame section). In the in-phase wobbling area, identification information indicating the position of the unit information recording area is read out, and the in-phase wobbling area 14A and the two-phase wobbling area 14B included in the unit information recording area by this identification information Information can be recorded in all of them. Therefore, an optical disc of frame wobbling type increases the recording capacity.

Such a frame wobbling type optical disc has a phase in wobbling area 14A and an out of phase wobble area 14B alternately appearing on both the mountain and valley signal tracks 10 and 12 during recording and playback. The reference clock indicative of the data transmission rate cannot be generated stably. For this reason, the frame wobbled optical disc is difficult to record / reproduce by an existing optical disc recording / reproducing apparatus for accessing CD-R, DVD-RAM and the like.

Accordingly, it is an object of the present invention to provide an optical disc recording / reproducing apparatus suitable for accessing a recording medium of frame wobbling.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically showing a signal track structure of an optical disc of a frame wobbling method.

2 is a diagram schematically showing an optical disc recording / reproducing apparatus according to an embodiment of the present invention.

3 is a detailed block diagram showing details of the synchronizer shown in FIG.

4 is a waveform diagram illustrating output signals of respective parts of FIGS. 2 and 3;

5 is a diagram schematically showing an optical disc recording / reproducing apparatus according to another embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: track of the mountain 12: track of the goal

14A: In-phase wobbling area 14B: In-phase wobbling area

20: Pick 22: Wobble signal detector

24: edge detector 26,28: first and second delay

30,44: frequency / phase comparator 32,46: charge pump

34,48: VCO 36,42: Frequency divider

38: synchronizer 40: sync detector

C1 to C3: Capacitors R1, R2: Resistance

INV1 to INV3: Inverter FF1 to FF7: Flip-flop

EOX1, EOX2: Exclusive OR Gate NAD: NAND Gate

In order to achieve the above object, an optical disc recording / reproducing apparatus according to the present invention is capable of detecting a wobble signal having the same phase from an optical disc having signal tracks formed so that both sides have the same phase and different phases alternately. A phase-locked loop having a frequency-phase comparator for generating signal detection means, an oscillation clock that follows the frequency and phase of the wobble signal of the same phase, and the frequency-phase comparator periodically in response to the wobble signal of the same phase And control means for activating and synchronizing means for recovering the channel bit stream and the channel bit clock from the wobble signal using the oscillation clock.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 5.

Referring to Fig. 2, the frame wobbled optical disc recording / reproducing apparatus according to the present invention is common to the wobble signal detector 22 and the edge detector 24 and the edge detector 16 connected in series with the pickup 20. And first and second delayers 26 and 28 connected. The pickup 20 irradiates a laser beam onto the optical disk of the frame wobbling method as shown in FIG. 1 and converts the laser beam reflected by the optical disk into an electrical signal. In order to generate this electrical signal, the pickup 20 has a two or four split photodetection element. The electrical signals from these photodetecting elements are processed such as filtering, adding and subtracting to generate a radio frequency signal and a wobble signal as shown in FIG. As shown in Fig. 1, an optical disc of frame wobbling method is provided with the phase wobble signal and the same phase wobble signal which are alternately arranged along the traveling direction of the track to each of the signal tracks 10 and 12 of the hill and valley. Have. This phase wobble signal is generated by a portion (i.e., this phase wobbling region) in which both sides of the mountain and valley signal tracks 10 and 12 are formed to be periodically provided with different phases. The phase wobble signal is generated by a portion (i.e., the phase phase wobbling region) in which both sides of the mountain and valley signal tracks 10 and 12 are formed to be periodically provided with the same phase. When the user information is recorded, that is, when the recording marks (or recording pits) are formed along the center line of the signal tracks 10 and 12 of the hill and valley, the high frequency signal includes the user information. This user information is located in a higher frequency band than the wobble signal. In addition, the high frequency signal includes a wobble signal together with user information. At this time, the high frequency signal has only the same phase wobble signal detected in the same phase wobble region. This is because this phase wobble signal detected in this phase wobbling area is canceled by the addition of electrical signals from the photodetecting element.

The wobble signal detector 22 processes electrical signals from the pickup 20 to detect the wobble signal WDI as shown in FIG. This wobble signal WDI becomes the in-phase wobble signal detected in the in-phase wobbling region. Therefore, the wobble signal WDI appears repeatedly every half frame period. In order to detect the wobble signal WDI, the wobble signal detector 22 performs filtering and addition operations of electrical signals from the photodetecting device of the pickup 20. This is due to the cancellation of this phase wobble signal detected in this phase wobbling region by the addition of the electrical signals. Alternatively, the wobble signal detector 22 may detect the in-phase wobble signal from the high frequency signal. In this case, the wobble signal detector 22 only performs the filtering operation on the high frequency signal.

The edge detector 24 detects edges (ie, rising and falling edges) of the in-phase wobble signal WDI from the wobble signal detector 22. Edge detector 24 generates a pulse of constant width each time an edge is detected. The edge detector 24 generates an edge detection signal having a frequency twice that of the in-phase wobble signal WDI.

The edge detection signal EDS generated by the edge detector 24 is supplied to the first and second delayers 26 and 28. The second delayer 28 delays the edge detection signal EDS from the edge detector 24 by a period corresponding to half of the code cells, thereby delaying the edge detection signal EDS as shown in FIG. ). The second delay unit 28 delays the edge detection signal from the edge detector 24 by a period corresponding to one code cell. One code cell period corresponds to one-half period of the wobble signal.

An optical disc recording / reproducing apparatus of a frame wobbling method includes a frequency / phase comparator 30 for inputting edge detection signals delayed by the first and second delayers 26 and 28, and the frequency / phase comparator 30. And a charge pump 32, a voltage controlled oscillator 34 ("VCO") 34 and a frequency divider 36, which are sequentially connected to form a loop. The frequency-phase comparator 30 selectively performs the frequency and phase comparison operation depending on whether the edge detection signal is applied from the second delay unit 28 toward its enable terminal. In other words, the frequency-phase comparator 30 performs the comparison operation of frequency and phase in the period in which the edge detection signal is applied from the second delayer 28, while the frequency and phase comparator 30 is not applied. Hold without performing the phase comparison operation. In this comparison operation, the frequency-phase comparator 30 adjusts the frequency and phase differences between the edge detection signal EDS delayed by the first retarder 26 and the first divided clock from the frequency divider 36. And generate a frequency difference signal and a phase difference signal accordingly.

The charge pump 32 is connected between the input terminal of the VCO 34 and the ground voltage line GNDL in response to the frequency difference signal and the phase difference signal detected by the frequency and phase comparator 30. To charge the voltage. The voltage charged by the charge pump 32 to the charge capacitor C1 changes in correspondence with or in proportion to the voltage levels of the frequency difference signal and the phase difference signal. The resistor R1 connected to the input terminal of the VCO 34 and the charging capacitor C1 limits the current signal charged in the charging capacitor C1 and the current discharged toward the VCO 34 from the charging capacitor C1. .

The VCO 34 generates an oscillation clock whose frequency and phase change according to the voltage level charged in the charging capacitor C1, and supplies the oscillation clock to the frequency divider 36. The frequency and phase of the oscillation clock generated by the VCO 34 are changed so that the frequency and phase of the divided clock output from the frequency divider 36 coincide with the edge detection signal delayed by the first delay unit 26. .

The frequency divider 36 divides the oscillation clock by an integer "N" rather than "0" to generate a first division clock having a frequency corresponding to "1 / N" of the frequency of the oscillation clock. The period 36 divides the oscillation clock into " 2N " to generate a second divided clock having a frequency corresponding to " 1 / 2N " of the frequency of the oscillation clock. The first divided clock is supplied to the frequency / phase comparator 30 and the synchronizer 38, and the second divided clock is supplied only to the synchronizer 38.

The synchronizer 38 detects the channel bit string CHBS and the channel bit clock CHCK in the wobble signal from the wobble signal detector 22 using the first and second divided clocks. To this end, the synchronizer 38 may be configured as shown in FIG.

Referring to FIG. 3, the synchronizer 38 includes a first inverter INV1 and a first flip-flop FF1 for inputting first and second divided clocks from the frequency divider 36, and a first flip-flop, respectively. A second inverter INV2 connected between the output terminal Q1 and the input terminal D1 of FF1 is provided. The first inverter INV1 inverts the first divided clock from the frequency divider 36, and supplies the inverted first divided clock to the clear terminal CLR1 of the first flip-flop FF1. The first flip-flop FF1 causes the signal on the output terminal Q1 to generate a low logic signal every time a low logic pulse is applied from the first inverter INV1 toward the clear terminal CLR1. In addition, the first flip-flop FF1 transfers a logic signal on the output terminal Q1 from high logic to low logic at each rising edge of the second divided clock applied from the frequency divider 36 toward its clock terminal. It will reverse from logic to high logic. In the output terminal of the first flip-flop FF1 which performs this operation, a clock signal having the same frequency as the second divided clock is generated and supplied to the second inverter INV2. The second inverter INV2 inverts the clock signal from the first flip-flop FF1 and provides the inverted clock signal as the master clock MCK as shown in FIG. For convenience of description, the clock signal generated at the output terminal Q1 of the first flip-flop FF1 is defined as "inverted master clock / MCK."

The synchronizer 38 outputs the second and third flip-flops FF2 and FF3 and the third flip-flop FF3 in response to the wobble signal WDI from the wobble signal detector 22 of FIG. 2. The fourth flip-flop FF4 and the first exclusive OR gate EOX1 are commonly connected to the terminal Q3. The second flip-flop FF2 outputs a wobble signal WDI supplied to its input terminal D2 at each rising edge of the master clock MCK applied from the second inverter INV2 toward its clock terminal. The data is transmitted to the input terminal D3 of the third flip-flop FF3 through the terminal Q2. In other words, the second flip-flop FF2 generates the primary synchronization wobble signal FWDI as shown in FIG. 4 in which the wobble signal WDI is synchronized with the master clock MCK. The third flip-flop FF3 is supplied toward its input terminal D3 at each rising edge of the inverted master clock / MCK applied from the output terminal Q1 of the first flip-flop FF1 toward its clock terminal. The first synchronized wobble signal FWDI is supplied to the output terminal Q4 and the first exclusive OR gate EOX1 of the fourth flip-flop FF4 via its output terminal Q3. The wobble signal output from the output terminal Q3 of the third flip-flop FF3 becomes the secondary synchronized wobble signal SWDI as shown in FIG. 4 synchronized with the inverted master clock / MCK.

The fourth flip-flop FF4 is supplied toward its input terminal D3 at each rising edge of the inverted master clock / MCK applied from the output terminal Q1 of the first flip-flop FF1 toward its clock terminal. The second synchronized wobble signal SWDI is supplied to the first exclusive OR gate EOX1 via its output terminal Q4. That is, the fourth flip-flop FF4 delays the second synchronized wobble signal SWDI by a period of the master clock MCK to generate the delayed wobble signal DWDI as shown in FIG. 4. Then, the first exclusive OR gate EOX1 has the secondary synchronized wobble signal SWDI from the output terminal Q3 of the third flip-flop FF3 and the output terminal Q4 of the fourth flip-flop FF4. And compares the logic value of the delayed wobble signal DWDI from &lt; RTI ID = 0.0 &gt;), &lt; / RTI &gt; As shown in Fig. 4, the mask signal MKS draws high logic when the logic value of the secondary synchronized wobble signal SWDI is the same as that of the delayed wobble signal DWDI, and the two wobble signals SWDI and DWDI. Have different logic values. The mask signal MKS thus generated indicates a phase change point in the wobble signal. As a result, the fourth flip-flop FF4 and the first exclusive OR gate EOX1 may be referred to as phase shift detection units that detect a phase shift point of the wobble signal.

The synchronizer 38 also clocks the NAND gate NAD in response to the mask signal MKS from the first exclusive OR gate EOX1 and the master clock MCK from the second inverter INV2. And a fifth flip-flop FF5 input to the terminal. The NAND gate NAD moves the bit clock BCK on the output terminal Q5 of the fifth flip-flop FF5 toward the input terminal D5 of the fifth flip-flop FF5 according to the logic value of the mask signal MKS. Will be sent selectively. In detail, the NAND gate NAD causes the mask signal MKS to be supplied to the input terminal D5 of the fifth flip-flop FF5 while the bit clock BCK is inverted in a period in which the mask signal MKS has a high logic. In the period in which the mask signal MKS has a low logic, the high logic is supplied to the input terminal D5 of the fifth flip-flop FF5. The fifth flip-flop FF5 latches the output signal of the NAND gate NAD toward its output terminal Q5 at each rising edge of the master clock MCK from the second inverter INV2, thereby causing the bit clock BCK to become a bit. Occurs.

Furthermore, the synchronizer 38 may include the sixth flip-flop FF6, the second exclusive OR gate EOX2, and the sync detector 40 that are cascaded to the output terminal Q3 of the third flip-flop FF3. Equipped. The sixth flip-flop FF6 is applied to the input terminal D6 from the output terminal Q3 of the third flip-flop FF3 at each rising edge of the master clock MCK from the second inverter INV2. The differentially synchronized wobble signal SWDI is supplied to the second exclusive OR gate EOX2 via its output terminal Q6. In other words, the sixth flip-flop FF6 generates the third-order synchronized wobble signal TWDI as shown in FIG. 4 in which the second-synchronized wobble signal SWDI is synchronized to the master clock MCK again. The second exclusive OR gate EOX2 is connected from the third-order synchronized wobble signal TWDI from the output terminal Q6 of the sixth flip-flop FF6 and from the output terminal Q5 of the fifth flip-flop FF5. By comparing the logic values of the bit clock BCK, the channel bit stream CHBS as shown in FIG. 4 is detected. In detail, the second exclusive OR gate EOX2 draws a logic signal of a high logic when the logic value of the third-order synchronized wobble signal TWDI is equal to the logic value of the bit clock BCK, and the third-synchronized wobble. When the logic value of the signal TWDI and the logic value of the bit clock BCK are different, the logic signal of the low logic is generated. The channel bitstream CHBS detected by the second exclusive OR gate EOX2 is supplied to the sync detector 40.

The sync detector 40 is configured such that the channel bit stream input from the second exclusive OR gate EOX2 matches a bit clock BCK from the output terminal Q5 of the fifth flip-flop FF5 with a specific logic value pattern. By checking whether there is a match, the synchronization signal is detected. That is, the sync detector 40 determines that the sync signal has been read when the channel bit stream CHBS matches a specific logical value pattern stored in advance. At this time, the sync detector 40 generates a sync detection signal SYNC as shown in FIG. 4 and supplies it to the preset terminal PRS of the seventh flip-flop FF7.

The seventh flip-flop FF7, which receives the sync detection signal SYNC from the sync detector 40, forms a two-division circuit together with the third inverter INV3. At this time, the third inverter INV3 inverts the channel bit clock CHCK on the output terminal Q7 of the seventh flip-flop FF7 and converts the inverted channel bit clock into the input terminal of the seventh flip-flop FF7. Return to (D7). The seventh flip-flop FF7 latches the output signal of the third inverter INV3 toward its output terminal Q7 at each rising edge of the master clock MCK from the second inverter INV2. In addition, the seventh flip-flop FF7 has a high logic on its output terminal Q7 whenever a low logic synchronization detection signal SYNC is applied from the synchronization detector 40 toward its preset terminal PRS7. The logic signal of appears. By performing this operation, the seventh flip-flop FF7 generates the channel bit clock CHCK as shown in FIG.

5 shows an optical disc recording / reproducing apparatus of a frame wobbling method according to another embodiment of the present invention. The optical disk recording / reproducing apparatus of the frame wobbling method of FIG. 5 is connected to a frequency / phase comparator 30, a VCO 34, and a frequency divider 36 in the recording / reproducing apparatus shown in FIG. The frequency divider 42, the second frequency phase comparator 44, the second charge pump 46, and the second VCO 48 are further provided.

The first frequency-phase comparator 30, the first charge pump 32, the first VCO 34, and the second frequency divider 42 constitute a primary phase locked loop. This first phase locked loop generates a first oscillating clock that follows the frequency and phase of the delayed edge detection signal EDS from the first delay 26.

In addition, the second frequency-phase comparator 44, the second charge pump 46, the second VCO 48, and the first frequency divider 36 constitute a secondary phase locked loop. This secondary phase locked loop generates first and second divided clocks that follow the frequency and phase of the primary oscillation clock generated by the primary phase locked loop.

This cascaded two phase locked loop allows the first and second divided clocks to quickly follow the frequency and phase of the delayed edge detection signal without transient frequency and phase transients.

As described above, the optical disc recording / reproducing apparatus of the frame wobbling method according to the present invention can reproduce the channel clock and the channel bit stream from a signal track in which parts having different phases with the same phase on both sides alternately appear. Accordingly, an optical disc recording / reproducing apparatus of a frame wobbling method according to the present invention can search an area to be recorded and / or reproduced by a channel bit stream, and can also record and reproduce user information by using a channel bit clock. Let's do it.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

Wobble signal detection means for detecting a wobble signal of the same phase from an optical disc having signal tracks formed so that both sides have the same phase and different phases alternately; A phase locked loop having a frequency-phase comparator for generating an oscillation clock that follows the frequency and phase of the wobble signal of the same phase from the wobble signal detecting means; Control means for periodically disabling said frequency-phase comparator in response to a wobble signal of the same phase from said wobble signal detecting means; And synchronization means for recovering a channel bit stream and a channel bit clock from the wobble signal using the oscillation clock. The method of claim 1, The synchronization means, Phase change detection means for detecting a phase change period of the in-phase wobble signal using the oscillation clock; Bit clock recovery means for restoring the bit clock included in the wobble signal by combining the output signal of the phase change detection means and the oscillation clock; Data recovery means for recovering a channel bit stream included in the wobble signal by using the bit clock; And a synchronization detecting means for detecting a synchronization signal from the channel bit stream. The method of claim 2, And the bit clock recovery means selectively changes the phase of the oscillation clock in response to an output signal of the phase change detection means. The method of claim 2, The synchronizing means further comprises channel bit clock generating means for generating a channel bit clock by frequency-dividing the oscillating clock and adjusting a phase of an output signal in response to a synchronizing signal detected by the synchronizing detection means. A method of manufacturing an optical recording medium.