KR20010062663A - In situ deposition and integration of silicon nitride in a high density plasma reactor - Google Patents

Abstract

PURPOSE: To provide a method including a step for depositing a silicon oxide layer on a substrate and a step for deposition a dielectric film on the substrate constituted of a step processing a dielectric layer with oxygen. CONSTITUTION: The layer of FSG which is deposited in HDP-CVD and whose fluorine content is 7% or above when it is compared in peak high ratio, is processed with oxygen plasma. Thus, a film is stabilized or the thin layer ( < 1,000 angstroms) of substance, such as silicon nitride is deposited on the FSG layer using low-pressure strike. Low pressure strike is performed by making a process gas flow, so that pressure in a chamber becomes the range of 5 to 100 millitorrs and turning on a bias voltage for time sufficient for establishing a weak plasma, which is capacitively connected. Thus, a source voltage is turned on, and the bias voltage is turned off.

Description

In situ deposition and integration of silicon nitride in a high density plasma reactor {IN SITU DEPOSITION AND INTEGRATION OF SILICON NITRIDE IN A HIGH DENSITY PLASMA REACTOR}

The present invention relates to a process and apparatus for depositing a dielectric layer during semiconductor substrate processing. More specifically, the present invention relates to a method of depositing and integrating fluorosilicate glass and silicon nitride in a high density plasma chemical vapor deposition reactor.

The size of the semiconductor device continues to decrease, providing more and faster devices per fabricated wafer. Since the introduction of semiconductor integrated circuits decades ago, integrated circuits typically use a new generation of devices, with more transistors taking up less space. Currently, some devices are manufactured with less than 0.25 μm spacing between features. In some cases, the space between device features is 0.18 μm or less. Examples of these features are wires or traces patterned on the metal layer. Aluminum has generally been used in these traces. Recently, a technique for depositing a trace made of copper has been developed. Copper is preferred for this trace because it is a more conductive material than aluminum.

Nonconductive layers of dielectric material, such as silicon dioxide, are often deposited between and on the patterned metal layers. This dielectric layer can be used for a variety of purposes to insulate the metal layer from other metal layers, to isolate the conductive features in the metal layer from each other, and to protect the metal layer and / or features from physical or chemical damage. The smaller the gap or gap between conductive features, the greater the capacitance of the formed device. Increased capacitance can reduce the operating speed of the integrated circuit. One way to reduce capacitance is to use an insulating material with a low dielectric constant. Such materials are often referred to as low k dielectrics.

One way to fill the gap by depositing a low dielectric is to bond halogen atoms to the silicon dioxide layer. Examples of halogen bonds are described in U.S. Patent Application Nos. 08 / 548,391 filed Oct. 25, 1995 and "Methods and Devices for Improving Film Stability of Halogen-Doped Silicon Dioxide Films," The use of SiF ₄ to deposit stable F-doped films is disclosed in 08 / 538,696, which is incorporated herein by reference. Halogen dopants such as fluorine lower the dielectric constant of the silicon dioxide film because halogen is a negative electron atom that reduces the polarity of the entire SiOF network. Fluorine doped silicon dioxide films are often referred to as fluorosilicate glass (FSG) films.

The fluorine content generally determines the characteristics of the FSG layer, such as the dielectric constant. The fluorine content of FSG is measured by Fourier Transform Infrared Spectroscopy (FTIR) in terms of the ratio of the height of the two absorption peak values. The height of the first (SiF) peak value generally indicates the presence of a Si-F bond. The height of the second (SiO) peak generally indicates the presence of a Si-O bond. The average fluorine concentration of the FSG is determined by the following percentage peak height ratio (% PHR):

Direct measurements of the fluorine content of the FSG show that% PHR is approximately proportional to the atomic% fluorine (atomic% F) of the FSG layer. The atom% F is often approximated by the formula:

Atomic% F = (% PHR) × K,

Where K is a constant determined experimentally. The fluorine concentration (atomic% F) can be determined by methods such as second ion mass spectroscopy (SIMS), attenuated total reflection (ATR), or component analysis.

One method of depositing a dielectric layer is a deposition method by chemical reaction of glass. This deposition process is called chemical vapor deposition (CVD). The thermal CVD process supplies a reactive gas to the substrate surface, where heat-induced chemical reactions occur to form the desired film. The high temperatures at which some thermal CVD processes operate can damage the metal layers of the device structure. Plasma enhanced CVD (PECVD) processes, on the other hand, facilitate excitation and / or separation of the reaction gas by capacitively coupling high frequency (RF) energy to a reaction zone adjacent the substrate surface, thereby promoting plasma of highly reactive species. Create The high reactivity of the released species reduces the energy required for chemical reactions to occur and thus lowers the temperature required for such CVD processes. Unfortunately, some PECVD processes vary the deposition rate depending on the shape of the underlying features. These phenomena can create voids at the bottom of the gap.

Improved gap fillers can be obtained with high density plasma CVD (HDP-CVD) systems. In HDP-CVD, the RF coil generates an inductively coupled plasma under low pressure conditions. The density of this plasma is approximately twice as large as that of capacitively coupled PECVD plasma. The low pressure chamber used in the HDP-CVD system provides a long average free path to the active species. The long average free path combined with high density allows a significant number of plasma components to reach the deepest portion of the most closely spaced gaps, providing excellent gap filling capability to the film. Due to the high density associated with HDP-CVD, sputtering also increases during deposition. Sputtering slows the deposition on top of the gap and prevents the gap from closing too quickly.

There are several problems associated with the FSG layer that undesirably separate the copper conductive traces. The first problem is that copper has a very high diffusivity in dielectric materials such as FSG. In addition, an incompletely formed FSG layer may absorb humidity from the temperature or reaction product associated with the deposition process. Copper diffusion and moisture absorption can be prevented by depositing a silicon nitride (Si ₃ N ₄ ) thin film layer on top of the FSG or between the FSG layer and the copper layer. Silicon nitride acts as a diffusion barrier. Copper has a diffusion length of silicon nitride between approximately 150 and 200 angstroms. Thus, a Si ₃ N ₄ layer with a thickness of 200 angstroms or more can sufficiently prevent copper from diffusing into the bottom or top Si ₃ N ₄ dielectric layer. Undesirably, fluorine tends to exit the FSG at a temperature of approximately 350 ° C. The released fluorine forms a "bubble" in the upper Si ₃ N ₄ layer. At this time, the bubble causes Si ₃ N ₄ to be thinly divided.

One common sequence for depositing thin films using HDP-CVD is that argon flows into the chamber and then strikes the argon plasma at a pressure of approximately 40 millitorr. Once the plasma is struck, the pressure in the chamber is reduced to approximately 5 millitorr (eg by opening the throttle valve) and then the deposition gas is inserted into the chamber to deposit the film. Undesirably, during the first few seconds of deposition in this way, the deposition gas does not flow uniformly because each gas nozzle is at a different pressure. If the plasma is already on when the deposition gas starts to flow, deposition occurs immediately. Thus, an initial burst of gas with a plasma that is already on reacts with a non-uniform initial layer that is several hundred angstroms thick. Non-uniformity of the membrane is usually determined by measuring the thickness of the membrane at multiple (eg 49) equidistant points and making the width of the thickness distribution formed half the maximum. Thin films deposited as described above generally exhibit approximately 4.75% non-uniformity, which strikes the plasma within approximately 10 seconds. The nonuniformity can be reduced to about 3.5% after about 30 seconds and slowly increased to about 4% after about 60 seconds.

This is not a problem for thick films (i.e., approximately 1000 mm 3 or more) since the thickness of the initial non-uniform layer usually occupies a small proportion to the total film thickness. For example, suppose that a 10,000 mm thick film has a non-uniform initial layer of 300 mm thick. The non-uniform initial layer then accounts for only 3 percent of the total film thickness. However, for films with a thickness of less than 1000 mm 3, the same 300 mm non-uniform layer accounts for at least 30 percent of the total film thickness. This nonuniformity is often undesirable in the cap layer.

Accordingly, it is an object of the present invention to achieve a stable low dielectric constant FSG film having a silicon nitride cap layer strongly adhered at high temperature and a deposition method thereof.

1A is a schematic diagram of one embodiment of a high density plasma chemical vapor deposition system according to the present invention.

1B is a schematic cross-sectional view of a gas ring that may be used in the CVD processing chamber of FIG. 1A.

1C is a schematic diagram of a monitor and light pen that may be used in the CVD processing chamber of FIG. 1A.

FIG. 1D is a flowchart of an implementation process control computer program product used to control the CVD processing chamber of FIG. 1A.

2 is a cross-sectional view of a structure including an embodiment of a dielectric layer in accordance with the present invention.

3 is a cross-sectional view of a film having a low dielectric constant according to the present invention.

4 is an embodiment flow diagram of a method of depositing a film having a low dielectric constant in accordance with the present invention.

5 is an embodiment flow diagram of a method of depositing an upper layer in accordance with the present invention.

6A-6H are cross-sectional views of partially formed integrated circuits operating a combined dual-damascene process in accordance with an embodiment of the present invention.

7A-7H show thermal vapor deposition spectroscopy for films with low dielectric constants.

* Description of symbols on the main parts of the drawings *

10: HDP-CVD system 13: chamber

14 dome 16: plasma treatment area

17, 18: substrate 21: base portion of the substrate

22 body member 23 heating plate

24: cold plate 25: throttle body

26: Throttle Valve 27: Gate Valve

28 turbo-molecular pump 29, 30 coil

The method of the present invention comprises depositing a silicon oxide layer (eg, FSG) on a substrate; Overcoming the disadvantages of the prior art by treating the dielectric layer with oxygen prior to forming a silicon nitride cap on this layer. Oxygenation stabilizes the FSG. In one embodiment of the present invention, the FSG layer having a fluorine content of about 7% or more measured by the peak height ratio is deposited by HDP-CVD and treated with an oxygen plasma. A thin film (<1000 mm thick) layer of silicon nitride is deposited on the FSG layer using a low pressure strike described in more detail below.

The first dielectric may be deposited by introducing a silicon-containing gas, a fluorine-containing gas and an oxygen-containing gas into the deposition chamber to generate a first plasma and deposit the first dielectric layer using the first plasma. The second dielectric layer may be deposited by introducing one or more process gases into the deposition chamber, low pressure strike to initiate the plasma, and depositing the second dielectric layer with the second plasma. Low pressure strike can be achieved by introducing a process gas such that the pressure in the chamber is between 5 and 100 millitorr, turning on the bias voltage for a period of time sufficient to form a weak plasma. Weak plasma may be capacitively coupled. After the weak plasma is formed, the source voltage is turned on and then the bias voltage is turned off.

Optionally, the low dielectric constant film deposits fluorosilicate glass (FSG) at a first atomic ratio of fluorine to oxygen, treats the FSG to reduce the ratio of fluorine to oxygen, and then deposits silicon nitride on top of the FSG layer. It can be formed by. Preferably, the FSG deposition, oxygen treatment and silicon nitride treatment are all performed in the same chamber without removing the substrate from the chamber.

In another embodiment, the low dielectric constant film has an FSG layer formed between two silicon nitride layers. Each silicon nitride layer is formed using low pressure strike and the FSG layer is treated with oxygen to improve the stability of the film.

Various modifications of the invention can be embodied as program code for controlling a semiconductor processing system. This program code may be stored in a suitable computer readable storage medium. The program code may be configured to control a deposition apparatus including a deposition chamber, a gas panel coupled to the chamber, a plasma generation system coupled to the chamber, a controller coupled to the gas panel, a source power supply, and a bias power supply. Can be. The controller generally includes a computer readable storage medium having the program code.

Films deposited according to various embodiments of the present invention exhibit low dielectric constants, good thermal stability, and strong adhesion. In addition, process integration can be improved by depositing both films by in-situ HDP-CVD. Embodiments of the present invention are particularly useful in copper damascene applications.

I. Introduction

An embodiment of the method of the present invention is to deposit a stable multilayer dielectric film having a low dielectric constant. The film is stabilized by treatment with oxygen and covered with a layer of silicon nitride having a uniform thickness of less than 1000 mW. A particular embodiment of the method of the present invention is the deposition of fluorosilicate glass (FSG). The fluorine content of FSG is measured by Fourier transform infrared spectroscopy (FTIR) in terms of% PHR. SiF peak values generally have a wave number of approximately 890 cm ⁻¹ . SiO peaks generally have a wave number of approximately 1040-1100 cm ⁻¹ . The fluorine concentration of FSG is measured in percent peak height ratio (% PHR) as described above. In certain embodiments, the FSG layer has a fluorine content measured by% PHR of approximately 7% or more.

Low pressure strike provides high uniformity to the thin film layers by stabilizing the inflow of the desired gas before striking the plasma. These two layers can be deposited successively using HDP-CVD, thereby improving the integration of the process.

II. Typical Substrate Processing System

1A illustrates one embodiment of a high density plasma chemical vapor deposition (HDP-CVD) system 10 in which a dielectric layer may be deposited in accordance with the present invention. The system 10 includes a chamber 13, a vacuum system 70, a source plasma system 80A, a bias plasma system 80B, a gas delivery system 33, and a remote plasma cleaning system 50.

The top of the chamber 13 includes a dome 14 made of a ceramic dielectric material, such as aluminum oxide or aluminum nitride. The dome 14 forms the upper boundary of the plasma processing region 16. The plasma processing region 16 is bounded by the top surface of the substrate 17 and the substrate support member 18 on the bottom.

The heating plate 23 and the cooling plate 24 cover the dome 14 and are thermally coupled with the dome 14. The heating plate 23 and the cooling plate 24 can control the dome temperature within about ± 10 ° C in the range of about 100 ° C to about 200 ° C. This can optimize the dome temperature for various treatments. For example, it may be desirable to maintain the dome at a higher temperature for cleaning or etching processes than for deposition processes. Accurate dome temperature control also reduces the number of pieces or particles in the chamber to improve adhesion between the deposited layer and the substrate.

The lower part of the chamber 13 includes a body member 22 connecting the chamber to a vacuum system. The base portion 21 of the substrate support member 18 is mounted on the body member 22 and forms a continuous inner surface with the body member 22. The substrate is moved by the robot blade (not shown) into the chamber 13 and out of the chamber 13 through an insertion / removal opening (not shown) on the side of the chamber 13. A lift pin (not shown) is raised and descends upon motor (not shown) control to move the substrate from the robotic blade in the upper loading position 57 to the lower processing position 56, where the substrate is It is located on the substrate receiving portion 19 of the substrate support member 18. The substrate receiving portion 19 includes an electrostatic chuck 20 that secures the substrate to the substrate support member 18 during substrate processing. In a preferred embodiment, substrate support member 18 is obtained from an aluminum oxide or aluminum ceramic material. The substrate support member 18 is generally equipped with heating and cooling elements that adjust the temperature of the substrate 17. For example, substrate support member 18 may include a heating element, such as a resistive heater. Optionally, the substrate 17 may be heated in whole or in part by collision with energy from the ions from the plasma in the chamber 13. The substrate support member 18 often includes a heat exchange element such as a cooling fluid tube. The substrate receiving portion 19 may include grooves or channels for distributing heat transfer media such as backside gas (eg, helium). This heat transfer medium has a higher thermal conductivity than in vacuum, which facilitates heat transfer between the substrate support member 18 and the substrate 17.

The vacuum gauge 70 includes a throttle body 25 that receives the twin-blade throttle valve 26 and is attached to the gate valve 27 and the turbo-molecular pump 28. As described in US patent application Ser. No. 08 / 574,839, filed Dec. 12, 1995, and incorporated herein by reference, the throttle body 25 minimizes gas ingress and Allow symmetrical pumping. Gate valve 27 may isolate pump 28 from throttle body 25 and may limit chamber pressure by limiting discharge inflow when throttle valve 26 is fully open. Throttle valves, gate valves, and turbo-molecular pump arrangements enable accurate and stable control of chamber pressure between approximately 1 millitorr and approximately 2 torr.

The source plasma system 80A includes an upper coil 29 and a side coil 30 mounted to the dome 14. Symmetric ground shields (not shown) reduce electrical coupling between coils. The upper coil 29 is powered by the upper source RF (SRF) generator 31A, while the side coil 30 is powered by the side SRF generator 31B, so that each coil has an independent power level. And operating frequency. This dual coil system allows control of the radial ion density of the chamber 13, thereby improving plasma uniformity. Side coil 30 and top coil 29 are generally inductively driven, which does not require complementary electrodes. In a particular embodiment, the upper source RF generator 31A nominally provides up to 2500 watts of RF power at 2 MHz and the side source RF generator 31B has nominally 1.8 to 2.2 MHz and nominally up to 5000 MHz at 2 MHz. Provides wattage RF power. The operating frequencies of the top and side RF generators can be offset at nominal operating frequencies (eg, up to 1.7-1.9 MHz and 1.9-2.1 MHz, respectively) to improve plasma-generating efficiency.

The bias plasma system 80B includes a bias RF (BRF) generator 31C and a bias matching network 32C. The bias plasma system 80B inductively couples the substrate portion 17 to a body member 22 that acts as a complementary electrode. The bias plasma system 80B increases the movement of plasma species (eg, ions) generated on the substrate surface by the source plasma system 80A. BRF generator 31C provides RF power at frequencies in the range of approximately 1-100. In a particular embodiment, the BRF generator 31C provides up to 5000 Watts of RF power at 13.56 MHz.

RF generators 31A and 31B include digitally controlled synthesizers and operate in a frequency range between approximately 1.8 and approximately 2.2 MHz. As is well known by those skilled in the art, each generator includes an RF control circuit (not shown) that measures the power reflected from the chamber and the coil fed back to the generator and adjusts the operating frequency to obtain the lowest reflected power. RF generators are typically designed to operate at a load with a characteristic impedance of 50 ohms. RF power may be reflected from a load with a different characteristic impedance than the generator. This can reduce the power transferred to the load. In addition, overloads due to power reflected back from the load to the generator can damage the generator. Since the impedance of the plasma can range from less than 5 ohms to more than 900 ohms, depending on the plasma ion density among other elements, and the reflected power can be a function of frequency, adjusting the generator frequency in accordance with the reflected power As a result, the power transferred from the RF generator to the plasma is increased to protect the generator. Another way to reduce reflected power and increase efficiency is with a matching network.

Matching networks 32A and 32B match the output impedance of generators 31A and 31B having coils 29 and 30, respectively. The RF control circuit can tune the two matching networks by changing the value of the capacitor in the matching network to match the generator to the load as the load changes. When the power reflected back from the load to the generator exceeds a certain limit, the RF control circuit can tune the matching network. One way to provide constant matching and effectively prevent the tuning of the matching network by the RF control circuitry is to set the reflected power limit above the anticipated reflected power. This may help to stabilize the plasma by accommodating a constant matching network at some of the most recent conditions.

Other measurements can also stabilize the plasma. For example, an RF control circuit can be used to determine the power delivered to the load (plasma) and can increase or decrease the generator output power to keep the power delivered constant during the layer deposition process.

Gas delivery system 33 provides a chamber for processing gas from various sources 34A-34F through gas delivery line 38 (only shown). As will be appreciated by those skilled in the art, the actual connection of the actual source and delivery line 38 and the chamber 13 used for the sources 34A-34F will vary depending on the deposition and cleaning processes performed within the chamber 13. . Gas is inserted into the chamber 13 through the gas ring 37 and / or the upper nozzle 45. 1B is a simplified partial cross-sectional view of the chamber 13 showing additional details of the gas ring 37.

In one embodiment, the first and second gas sources 34A and 34B, and the first and second gas inlet controllers 35A 'and 35B', are connected via a gas delivery line 38 (some shown). Gas is supplied to the ring plenum 36 at 37. Gas ring 37 has a plurality of first source gas nozzles 39 (only a portion of which is shown for purposes of illustration) that supply a uniform inflow of gas to the substrate. The length and angle of the nozzle can be varied to accommodate uniform size and gas utilization efficiency for a particular process within the individual chamber. In a preferred embodiment, the gas ring 37 has twelve source gas nozzles obtained from aluminum oxide ceramics.

The gas ring 37 is also co-planar with the first source gas nozzle 39 in a preferred embodiment, shorter than this nozzle and in one embodiment, a plurality of second to obtain gas from the body plenum 41. Has a source gas nozzle 40 (only one of which is shown). In some embodiments, it is desirable not to mix different types of source gases before injecting the gases into the chamber 13. In another embodiment, the source gas may be mixed before injecting the gas into the chamber 13 by providing a hole (not shown) between the body plenum 41 and the gas ring plenum 36. In one embodiment, third and fourth gas sources 34C and 34D, and third and fourth gas inlet controllers 35C and 35D 'provide gas to the body plenum via gas delivery line 38. . The nitrogen source 34F provides nitrogen gas N ₂ to the second source gas nozzle 40 of the gas ring for the chamber during the processing step using the nitrogen plasma. Optionally, nitrogen gas may be delivered to the chamber through another or additional inlet, such as upper nozzle 45, through gas inlet controller 35F '. Additional valves, such as 43B (other valves not shown), shut off gas from the inlet controller to the chamber.

In embodiments where flammable, toxic or corrosive gases are used, it is desirable to remove the gas remaining in the gas induction line after deposition. This is accomplished by using a three-way valve, such as valve 43B, to isolate the chamber 13 from the induction line 38A and proceed from the induction line 38A to the vacuum foreline 44. As shown in FIG. 1A, other similar valves, such as 43A and 43C, may be integrated on other gas induction lines. The three-way valve is arranged close to the chamber 13 to maximize the volume of the practically leaking gas induction line (between the three-way valve and the mover). In addition, a two-way (on-off) valve (not shown) is disposed between the mass inlet controller (“MFC”) and the chamber or between the gas source and the MFC.

Referring again to FIG. 1A, the chamber 13 has an upper nozzle 45 and an upper vent 46. The upper nozzle 45 and the upper vent 46 allow independent control of the top and side inflow of the gas, improving film uniformity and finely controlling film deposition and doping parameters. The upper vent 46 is an annular opening around the upper nozzle 45. In one embodiment, the first gas source 34a is provided to the source gas nozzle 39 and the upper nozzle 45. The source nozzle MFC 35A 'controls the amount of gas delivered to the source gas nozzle 39 and the upper nozzle MFC 35A controls the amount of gas delivered to the upper gas nozzle 45. Similarly, two MFCs 35B and 35B 'may be used to control the inflow of gas from a single source, such as source 34B, to upper vent 46 and second source gas nozzle 40. The gas supplied to the upper gas nozzle 45 and the upper vent 46 is kept separate before flowing the gas into the chamber 13, or the gas is mixed in the upper plenum 48 before flowing into the chamber 13. Separate sources of the same gas are used to supply different parts of the chamber.

A remote microwave-generated plasma cleaning system 50 is provided for periodically cleaning deposition residues from chamber components. The cleaning system includes a remote microwave generator 51 which forms a plasma from the cleaning gas source 34E (eg, molecular fluorine, nitrogen trifluoride, other fluorocarbons or equivalents) in the reactor cavity 53. do. The reactive species resulting from this plasma are delivered to the chamber 13 through the applicator tube 55 and the cleaning gas supply port 54. Materials used to contain the cleaning plasma (eg, cavity 53 and applicator tube 55) resist attack by the plasma. The distance between the reactor cavity 53 and the feed port 54 should be kept substantially short because the concentration of the desired plasma species is lowered with distance from the reactor cavity 53. Generating a cleaning plasma in the remote cavity allows the use of an efficient microwave generator and ensures that the chamber is not affected by the bumping of the glow discharges that may be present in the plasma formed at temperature, radiation, or in situ. As a result, relatively sensitive components such as the electrostatic chuck 20 need not be covered or protected with the dummy wafer as required with the appropriate plasma cleaning process.

System controller 60 controls the operation of system 10. In a preferred embodiment, the controller 60 includes a hard disk drive, a floppy disk drive (not shown), and a memory 62 such as a card rack coupled to the processor 61. The card rack may include a single board computer (SBC) (not shown), analog and digital input / output boards (not shown), interface boards (not shown), and stepper motor controller boards (not shown). have. The system controller conforms to the Versa Modular European (VME) standard, which defines board, card cage, and connector sizes and shapes. The VME standard defines the bus structure as having a 16 bit data bus and a 24 bit address bus. The system controller 31 operates under the control of a computer program stored on a hard disk drive or through another computer program such as a program stored on a remote disk. The computer program dictates, for example, parameters of timing, gas mixture, RF power level and other specific processes. The interface between the user and the system controller is through a monitor, such as a cathode ray tube (CRT) 65, and a light pen 66, as shown in FIG. 1C.

1C illustrates a portion of an example system user interface used in connection with the example CVD processing chamber of FIG. 1A. System controller 60 includes a processor 61 coupled to computer readable memory 62. Preferably, memory 62 is a hard disk drive, but memory 62 may be a type of other memory, such as a ROM, PROM, or the like.

System controller 60 operates under the control of computer program 63 stored in a computer readable format in memory 62. The computer program indicates timing, temperature, gas inlet, RF power level and other specific processing parameters. The interface between the user and the system controller is through the CRT monitor 65 and the light pen 66 as shown in FIG. 1C. In a preferred embodiment, two monitors 65 and 65A, and two light pens 66 and 66A are used, one mounted to the cleaning room wall 65 for the operator and the other wall 65A for the service technician. ) Is mounted on the back. Both monitors display the same information at the same time, but only one light pen (eg, 66) is enabled. To select a particular screen or function, the operator contacts the display screen area and presses a button on the pen (not shown). The contacted area is selected by the light pen, for example by changing color or displaying a new menu.

The computer program code may be written in any conventional computer readable programming language, such as 68000 assembly language, C, C ++, Fortran, Physical or other languages. Appropriate program code can be entered into a single file or multiple files using conventional text editors and stored or used on a computer used medium, such as a computer's memory system. If the entered code text is a high level language, the code is compiled and the resulting compiler code is linked to the object code of the precompiled Windows library routines. To execute the linked compilation object code, the system user calls the object code for the computer system to load the code in memory. The CPU reads the code from the memory and executes the code to perform the tasks identified in the program.

1D shows a block diagram of a metrology control structure of a computer program 70. The user enters the process set number and process chamber number into the process selector subroutine 73 in response to a menu or screen displayed on the CRT monitor by using the light pen interface. A processing set is a predetermined set of processing parameters required for performing a specific processing, and is identified by a predetermined set number. The process selected subroutine 73 identifies (i) the desired processing chamber of the multichamber system, and (ii) the desired set of processing parameters needed to operate the processing chamber to perform the desired processing. Process parameters for performing a particular process relate to process gas composition and conditions such as flow rate, substrate temperature, pressure, plasma power conditions such as RF power level and chamber dome temperature and are provided to the user in the form of usage. The parameters described by usage are entered using the light pen / CRT monitor interface.

Signals for monitoring the processing are provided by the analog and digital input boards of the system controller 60, and signals for controlling the processing are output on the analog and digital output boards of the system controller 60.

Process sequencer subroutine 75 includes program code for receiving a set of process parameters from defined process chambers and process selection subroutines 73 and for controlling the operation of the various process chambers. Multiple users can enter a process set number and process chamber number or a single user can enter multiple process numbers and process chamber numbers; Sequencer subroutine 75 schedules selected processes in a given sequence. Preferably, the sequencer subroutine 75 comprises (i) monitoring the operation of the processing chamber to determine if the chamber is in use, (ii) determining what processing is performed in the chamber used, and (iii) Program code for performing a step of executing a predetermined process based on the availability of the processing chamber and the type of processing to be performed. Conventional methods of monitoring the processing chamber can be used like polling. When scheduling which processing is to be performed, sequencer subroutine 75 may compare the " age of a specific user input request &quot; or the current condition of the processing chamber or system programmer used with the selected processing conditions for the selected processing. It may be designed taking into account any other relative factors that it wishes to include to determine predetermined priorities.

After sequencer subroutine 75 determines which chamber and process set combination will be executed next, sequencer subroutine 75 may return chamber 13 and possibly other chambers in accordance with the process set transmitted by sequencer subroutine 75. The execution of a process set is initiated by passing certain process set parameters to chamber management subroutines 77a-c that control multiple processing tasks (not shown). In particular, chamber management subroutine 77a controls the CVD chamber, such as HDP-CVD chamber 13 of FIG. 1A.

Examples of chamber configuration subroutines are substrate positioning subroutine 80, process gas control subroutine 83, pressure control subroutine 85, plasma control subroutine 87, and plasma control subroutine 90. Those skilled in the art will understand that other chamber control subroutines may be included depending on which process is selected to be performed in chamber 13. In operation, chamber management subroutine 77a optionally schedules or invokes a process configuration subroutine associated with the particular process to be executed. The chamber management subroutine 77a schedules the process configuration subroutine in the same way that the sequencer subroutine 75 schedules the process chamber and the process to execute. Typically, chamber management subroutine 77a is responsible for monitoring various chamber elements, determining which elements need to be actuated based on process parameters for the process set to be executed, and responding to the monitoring and determining steps. Causing execution of the chamber configuration subroutine.

The operation of certain chamber element subroutines will be described with reference to FIGS. 1A and 1D. Substrate positioning subroutine 140 includes program code for controlling the chamber elements used to load the substrate onto substrate support number 18. Substrate positioning subroutine 140 may control the transport of the substrate to the chamber 13 from, for example, a PECVD reactor or other reactor in a multi-chamber system after other processing is completed.

Process gas control subroutine 83 has program code for controlling process gas configuration and flow rate. Subroutine 83 controls the open / close position of the safe shut-off valve to achieve the desired gas flow rate and ramps up / ramps down the media inlet controller. All chamber element subroutines, including process gas control subroutine 83, are called by chamber manager subroutine 77a. Subroutine 83 receives processing parameters from chamber management subroutine 77a associated with a given gas flow rate ratio.

Typically, the process gas control subroutine 83 opens the gas supply line, repeatedly (i) reads the required medium inlet controller, and (ii) the desired flow rate and reading result received from the chamber management subroutine 77a. (I) adjust the flow rate of the gas supply line as necessary. Furthermore, process gas control subroutine 83 includes the steps for monitoring the gas flow rate for activating an unsafe rate and a safe shut-off valve when an unsafe condition is detected.

In certain processes, an inert gas, such as argon, is flowed into the chamber 13 to stabilize the pressure in the chamber before the active process gas is induced. For this process, process gas control subroutine 83 includes flowing an inert gas into chamber 13 corresponding to the amount of time required to stabilize the pressure in the chamber. The steps described above may then be executed.

In addition, the processing gas is for example tetraoxosilane (TEOS: tetraethylorthos).

When evaporated from a liquid precursor, such as ilane, the process gas control subroutine 83 includes bubbling a carrier gas, such as helium, through the liquid precursor in a bubble assembly, or inducing helium into the liquid injection valve. do. For this type of treatment, process gas control subroutine 83 adjusts the inlet of the carrier gas, the pressure in the bubbler and the bubbler temperature to achieve the desired process gas flow rate. As described above, the predetermined gas flow rate is delivered to the process gas control subroutine 83 as process parameters.

Moreover, process gas control subroutine 83 includes a step for obtaining a carrier gas flow rate, bubbler pressure, and bubbler temperature by accessing a stored table containing the necessary values for a given process gas flow rate. Once the required values are obtained, the carrier gas flow rate, bubbler pressure and bubbler temperature are monitored and compared with the required values and adjusted accordingly.

The process gas control subroutine 83 may control the inflow of a heat transfer gas such as helium through the inner and outer passages in a wafer chuck with an independent helium control (IHC) subroutine (not shown). The gas inlet thermally couples the substrate to the chuck. In conventional processing, the wafer is heated by plasma and chemical reactions to form a layer, He cools the substrate through the chuck, and water cooling is also possible. This keeps the substrate below a temperature that could damage the shape already present on the substrate.

The pressure control subroutine 85 includes program code for controlling the pressure of the chamber 13 by adjusting the size of the opening of the throttle valve 26 at the outlet portion of the chamber. There are at least two ways to control the chamber with a throttle valve. The first method consists in characterizing chamber pressure in relation to the overall process gas inlet, process chamber size and pumping capacity, among others. The first method sets the throttle valve 26 to a fixed position. The throttle valve 26 set to the fixed position eventually results in a steady state pressure.

Alternatively, the chamber pressure may be measured with a manometer, for example, and the position of the throttle valve 26 indicates that the pressure control subroutine indicates that the control position is within the boundary set by the gas inlet and exhaust capacities ( 85). The former method may result in a faster chamber pressure change since the measurements, comparisons and calculations associated with the latter method are not called. The former method is preferred when precise control of chamber pressure is not required, while the latter method is preferred when accurate, repeatable and stable pressure is required during layer deposition.

When the pressure control subroutine 85 is implemented, the target, or target pressure level, is received as a parameter from the chamber manager subroutine 77a. The pressure control subroutine 85 measures the pressure in the chamber 13 by reading one or more conventional manometers connected to the chamber; Compare the target pressure with the measured value (s); The proportional, integral, and derivative (PID) values are obtained from the stored pressure table corresponding to the target pressure, and the throttle valve 26 is adjusted according to the PID values obtained from the pressure table. Alternatively, the pressure control subroutine 85 may open or close the throttle valve 26 to a specific aperture size to regulate the pressure in the chamber 13 to the desired pressure or pressure range.

The heater control subroutine 87 includes program code for controlling the temperature of the substrate 17 and / or the temperature of the chamber 13. There are at least two basic ways of controlling the chamber temperature. The first method relies on characterizing the substrate temperature as among other things related to the total power delivered by the plasma. The first method adjusts the level of source RF power and / or bias RF power. Increasing the power level generally increases the substrate temperature. As the power level decreases, the substrate temperature generally decreases. The first method can also be used to control the temperature of the chamber 13.

Optionally, the chamber or substrate temperature can be measured with a thermocouple or pyrometer, for example, and controlled by a separate temperature control unit. Such a temperature control unit can comprise a heater element, a cooling element or both. This heating / cooling element may be coupled to the substrate support member 18, the chamber 13, or both. Some chambers include a separate temperature control unit for the dome 14.

When temperature control subroutine 87 is desired, the desired or target pressure level is received as a parameter from chamber management subroutine 77a. The temperature control subroutine 87 measures the temperature of the chamber 13 and / or substrate 17 by reading one or more conventional temperature sensors connected to the chamber and / or the substrate, and the target temperature and measured values (values) Are compared to obtain the ratio, integral, and difference (PID) values from the stored pressure table corresponding to the target temperature, and according to the PID values obtained from the pressure table, the source RF generator 31A, the bias RF generator 31B, and It operates to regulate some combination of heating / cooling elements of the chamber / substrate. Optionally, temperature control subroutine 87 may set source RF generator 31A and / or bias RF generator 31B to a specific power level to adjust the temperature of substrate 17 to a desired temperature or temperature range.

The plasma control subroutine 90 includes program code for adjusting the frequency of the RF generators 31A and 31B, setting the output power and turning the matching network 32A and 32B. The plasma control subroutine 90 is implemented by the chamber manager subroutine 77a, similar to the chamber component subroutine described above. Those skilled in the art will appreciate that the substrate temperature is controlled by the control of the plasma, and that the temperature control subroutine 87 may be mounted, in whole or in part, in the plasma control subroutine 90.

An example of a system that may include some or all of the subsystems and routines described above is a ULTIMA ^™ system manufactured by Applied Materials, Inc., located in Santa Clara, California, configured to practice the invention. A more detailed description of this system is herein incorporated by reference and as co-inventors Fred C. Redeker, Farhad Moghadam, Hirogi Hanawa, Tetsuya Ishikawa, Dan Maydan, Shijian Li, Brian Lue, Robert Steger, Yaxin Wang, Manus Wong and Ashok Sinha, which is disclosed in US patent application 08 / 679,927, filed July 15, 1996, entitled "Symmetric Tunable Inductively-Coupled HDP-CVD Reactor."

III. Example structure

2 shows a simplified cross-sectional view of an integrated circuit 200 that can be constructed using the present invention. As shown, the integrated circuit 200 includes NMOS and PMOS transistors 203 and 206 that are separated from each other and electrically isolated by the field oxidation regions 220. Each transistor 203, 206 includes a source region 212, a drain region 215, and a gate region 118.

A premetal dielectric (PMD) layer 221 connects between the metal layer 240 and a transistor composed of a contact 224 to separate the transistors 203 and 206 from the metal layer 240. The metal layer 240 is one of four metal layers 240, 242, 244, and 246 included in the integrated circuit 200. Each of the metal layers 240, 242, 244 and 246 is separated from adjacent metal layers by each of the inter-metal dielectric (IMD) layers 227, 228 and 229. Adjacent metal layers are connected to the openings selected by vias 226. A protective layer 230 deposited over the metal layer 246 is planarized, which includes, for example, a barrier layer 230a, a gap fill layer 230b, and a cap layer 230c.

Preferably, at least one of the gap fill layers 227b, 228b, 229b and 230b comprises an FSG treated with oxygen according to the first embodiment of the present invention. More preferably, at least one of the cap fill layers 227c, 228c, 229c and 230c is deposited using low pressure strike in accordance with a second embodiment of the present invention. It is most preferable to deposit the cap layer according to the second embodiment of the present invention on the gap fill layer treated with oxygen according to the first embodiment of the present invention.

The layers of the present invention can be used in each of the dielectric layers shown in integrated circuit 200. The layer may also be used in damascene layers included in some integrated circuits. In the damascene layer, a blank layer is deposited over the substrate, selectively etched into the substrate, then filled with metal and backetched or polished to form a metal contact, such as 224. After the metal layer is deposited, a second blank deposition is performed to selectively etch. At this time the etched region is filled with metal and polished to form vias such as 226.

It will be appreciated that the simplified integrated circuit 100 is for illustration only. One of ordinary skill in the art would be able to practice the invention in connection with the manufacture of other integrated circuits such as microprocessors, application specific integrated circuits (ASICs), memory devices, and the like.

Ⅳ. Typical Low-k Constant Membrane

The dielectric film deposited according to the embodiment of the present invention generally has a low dielectric constant. Low dielectric constant in the present invention refers to the dielectric constant less than the dielectric constant for the undoped silicon oxide film. In general, silicon oxide (Si _x O _y ) has a dielectric constant k of approximately four. Films with k less than 4 are called low-k films. Membranes with k of 4 or more are called high-k membranes. Low dielectric constants arise from fluorine atoms that combine with the silicon dioxide layer of the film to form a fluorosilicate glass (FSG) layer. This dielectric film can be used as a dielectric (IMD) layer between metals or as another type of dielectric layer. The specific examples described below describe IMD layers formed on copper traces that can have an aspect ratio of at least 4: 1 in proximity to 0.25 microns. The film includes a thin layer of silicon nitride that is strongly attached to the FSG. The silicon nitride layer acts as a diffusion barrier between the copper and FSG layers. Thus, this layer lowers the dielectric constant, has excellent gap-filling properties, and is compatible with pre-implemented copper structures on semiconductor substrates.

3 is a simplified cross-sectional view of an embodiment of the present invention having a silicon dioxide double layer 300. An HDP-CVD layer of silicon nitride, for example Si ₃ N ₄ , is deposited over the conductive traces 304, 305 and the substrate 306. Substrate 306 may be, for example, a silicon wafer or a silicon wafer on which a substrate or layer is present. This silicon nitride layer acts as a diffusion barrier and improves the reliability of the underlying metal traces and is a compressive layer against metal cracking and electron transfer failures. Silicon nitride layer 302 may be deposited in accordance with a second embodiment of the present invention. An HDP-CVD layer 308 of the FSG is deposited on the surface of the silicon nitride layer 302. Preferably, the FSG layer 308 is treated with oxygen 312 after being deposited by conventional HDP-CVD. An optional capping layer 314 may be deposited to seal the FSG layer and provide a surface compatible with general later semiconductor processing. Preferably, the capping layer 314 is a silicon nitride layer deposited according to the second embodiment of the present invention.

Ⅴ. Low Dielectric Constant Film Deposition

4 is a flow chart of one embodiment of a deposition method according to the present invention, wherein oxygen treatment improves the stability of the FSG layer. In this embodiment, this treatment takes place in a single treatment chamber, but this process may be applied to a multichamber system or may be performed in a series of other chambers or systems. Similarly, the process parameters described below are for 8 inch process wafers, but this process can be modified to accommodate other wafers, such as 10 inch wafers.

The wafer is loaded onto the substrate support member through a vacuum-lock door or slit valve in the processing chamber (step 402) and moved to the desired processing position. A processing gas comprising a silicon source, a fluorine source, and an oxygen source is inserted into the chamber and a high density plasma is formed to deposit a layer of FSG (step 404) over the wafer. In a preferred embodiment, the silicon source is monosilane (SiH ₄ ), the fluorine source is tetrafluorosilane (SiF ₄ ), which can also be considered as a silicon source, and the oxygen source is biatomic coral (O ₂ ). Alternatively, TEOS or other silanes having the general formula Si _x H _y such as disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), tetrasilane (Si ₄ H ₁₀ ) can be used as the silicon source. . Similarly, other gases such as F ₂ can be replaced as the fluorine source. Ozone (O ₃ ) can be used as an optional oxygen source. The plasma may optionally include an inert gas such as helium or argon. It is generally easier to strike an argon plasma than a helium plasma. Although krypton and xenon are more expensive than helium and argon, other inert gases such as neon, krypton, or xenon may also be used.

These gases are provided at flow rates between 90 and 94 reference cubic centimeters per minute (sccm) for SiF ₄ , between 50 and 54 sccm for SiH ₄ , and between 155 and 165 sccm for O ₂ . Gas flow rates are more preferably approximately 94 cubic centimeters per minute (sccm) for SiF ₄ , 50 sccm for SiH ₄ , and 160 sccm for O ₂ . The pressure in the chamber is generally set to be maintained between approximately 3.5 to 6 millitorr, preferably approximately 4 millitorr. The plasma may be formed by the application of single or mixed RF power. In general, the SRF generator 31A provides an RF power upper coil 29 at a power level of between approximately 1.7 and 1.9 Hz, preferably between approximately 1.8 Hz and between 800 and 1000 W, preferably approximately 800 W. SRF generator 31B provides the side coil 30 with an RF power of approximately 2500 to 3500 W, preferably approximately 3000 W at a frequency between 2.0 MHz and 2.1 MHz. The bias RF power is provided to the substrate 17 at a power of approximately 13.56 MHz and approximately 800-2000 W, preferably approximately 1800 W. Wafer temperature is generally maintained between 380 and 400 ° C. The chamber temperature is generally maintained between about 70 and 75 ° C, preferably about 75 ° C.

The process conditions are maintained for a sufficient time to form an FSG layer having a thickness of approximately 6,000 kPa to 12,000 kPa, preferably approximately 8,000-10,000 kPa. The actual deposition time depends on the chamber used. For example, the chambers of FIGS. 1A-1D can deposit an FSG layer 8000 μs after approximately 90 seconds using this parameter. In this step, the FSG film deposited under the above conditions has a relatively high atomic ratio of fluorine to oxygen. In a preferred embodiment, the FSG layer has a fluorine concentration of between about 7.8% and about 8.0% measured by% PHR before treating the FSG layer with oxygen. Generally the O ₂ / Si ratio is between about 1.0 and 1.2, preferably about 1.1. The O ₂ / Si ratio generally depends on the flow rates of O ₂ , SiF ₄ and SiH ₄ as follows:

O ₂ / Si = O ₂ / (SiF ₄ + SiH ₄ )

In general, the SiF ₄ / SiH ₄ flow rate ratio is between about 1.7 and 1.8, preferably 1.75. The actual flow rate will depend on the chamber used.

The dielectric constant k and refractive index n of the FSG layer depend on the fluorine atom ratio of the FSG film. In general, the higher the fluorine content, the lower the values of k and n. FSG films having an atomic percentage of zero, ie, a fluorine content of undoped silicate glass (USG), generally have a k value of approximately 4 and a refractive index of approximately 1.46. When the FSG film is doped with 10% atomic fluorine, the refractive index is between 3.4 and 3.7 and the refractive index is between 1.40 and 1.43. The dielectric constant of the film is generally determined by capacitance and voltage (C-V) probe measurements of the deposited film and a known k reference film.

In addition to the methods described above for depositing FSG, several different processes for forming silicon fluoride glass (FSG) have been processed. One alternative process uses triepoxyfluorosilane (TEFS) with tetraepoxysilane (TEOS) in a PECVD deposition process. Another optional process for forming the FSG film uses C ₂ F ₆ as the fluorine source in the PECVD process. This FSG deposition process is described in US patent application Ser. No. 09 / 075,592, assigned to Applied Materials.

After forming the FSG layer, the surface of the FSG layer is treated with oxygen stage 406 to reduce the ratio of fluorine to oxygen. Oxygen treatment may be established, for example, by heating the FSG layer while impacting oxygen ions or energetic neutral oxygen atoms and exposing them to oxygen or ozone. In a preferred embodiment, the FSG layer is bombarded with oxygen ions from the plasma in the same chamber 13 in which it is deposited. Typically the SiF ₄ and SiH ₄ inlet is stopped at the end of the FSG deposition but the oxygen flow rate remains approximately the same as in step 404. The plasma is maintained using approximately the same power and frequency set for the source RF used during deposition. The bias RF frequency generally has the same value during oxygen treatment for FSG deposition, but the BRF power generally increases to almost one third or more of the value used during deposition. In a more preferred embodiment, the BRF power is between approximately 1500-1800 W during oxygen treatment.

During the oxygen treatment, the wafer temperature is maintained at approximately 420 ° C. The chamber pressure is maintained at about 1.8 to 2.5 millitorr, preferably about 2 millitorr for about 10 seconds to about 1 minute, preferably for about 20 seconds. Higher yields of wafers through the processing system are desirable, so the processing time should be kept as short as possible, but sufficient oxygen treatment should continue to be provided. The exact time required will depend on a number of factors, including how the HDP-CVD process described above is performed. Oxygen passes into the FSG layer, where the FSG layer reacts with fluorine to form a more stable film. The FSG layer has fluorine having a fluorine concentration measured by% PHR between about 7.5% and about 7.8% after oxygen treatment.

Optionally, a silicon nitride cap layer may be deposited over the FSG layer (step 408). The cap layer is not necessary to obtain the lower dielectric constant of the underlying layer, but may make the FSG layer more compatible with the next integrated circuit processing step. The FSG layer may be planarized or densified prior to the formation of the cap layer. This cap layer can be formed using an HDP-CVD process similar to the process described above. However, in order to control the ultra-thin film, i.e., 1000 mV or less, special low pressure strikes are necessary to initiate the plasma.

Ⅵ. Deposition of Cap Layer Using Low Pressure Strike

It is preferable to deposit a thin film cap layer of silicon nitride on the FSG film. In damascene applications, silicon nitride deposited on copper may serve as a barrier to prevent copper from diffusing to the top or bottom of the layer. Optionally, silicon nitride deposited on a dielectric layer such as FSG can stop the etching. The thin film layer of silicon nitride has a k value of approximately 7 compared to 3.4 for FSG comprising approximately 10 atomic percent F. The effective dielectric constant of the composite dielectric film depends on the thickness and dielectric constant of each layer including the film. In general, for a film composed of two layers each having dielectric constants k ₁ and k ₂ and thicknesses d ₁ and d ₂ , the effective dielectric constant k _eff depends on the thickness and dielectric constant for each layer. In general, thicker layers are more affected by the effective dielectric constant of the membrane. Thus, even if silicon nitride has a much higher dielectric constant than FSG, if the silicon nitride layer is sufficiently thin compared to the overall film thickness, the effective dielectric constant of the film can be similar to that of FSG.

In addition to being thin, the silicon nitride layer should generally be uniform. In order to deposit a uniform thin silicon nitride layer after FSG deposition, it is often desirable to strike the plasma and flow the deposition gas. 5 is a flowchart of an embodiment of a method of depositing a cap layer of the present invention using low pressure strike. The low pressure strike method is described in the co-assigned US patent application of document number AMAT / 3272 / PDD / KPU3 / JW entitled “Low Pressure Strike in HDP-CVD Chamber” filed concurrently with this application and used herein by reference. Described. The embodiment of the method shown in FIG. 5 is a preferred embodiment of step 408 of FIG. 4. The method 500 begins after step 406 of FIG. 4, that is, after oxygen treatment of the FSG layer described above. Optionally, the cap layer may be deposited by method 500 after step 404. The method begins at step 502 by turning off the fluorine, silicon and oxygen sources. However, any inflow of inert gas is maintained. If no inert gas was used in the previous step, the introduction of the inert gas is achieved before blocking other gases. That is, the plasma of the inert gas is made in the chamber. In a preferred embodiment, the inert gas is argon provided at a flow rate between 180 and 200 sccm. Source RF is generally maintained at frequencies between 1.8 Hz and 2.07 Hz for the top and side coils, respectively. The source RF power is maintained between approximately 4000 and 5000W, preferably 4500W. The bias RF is turned off in step 504 to reduce the kinetic energy ionized from the inert plasma that impacts the film.

The substrate temperature is established at step 506. In the cap layer of silicon nitride (Si _x N _y ), a substrate temperature of approximately 430 ° C. is generally achieved prior to deposition. Inert plasma can be used to heat the substrate, for example by exposing the substrate to the plasma. The exposure time depends on the temperature rise required for the substrate. In general, the hotter the substrate, the less time is required to heat the substrate. In order to increase throughput, it is generally desirable to deposit the cap layer as soon as possible after the underlying layer is deposited, ie when the wafer is already warmed. For example, if the cap layer should be deposited immediately after FSG deposition, the substrate is already very hot. Under these circumstances, exposing the substrate to an inert plasma for approximately 10 seconds is generally sufficient to heat the substrate to the desired temperature for deposition of the cap layer. Optionally, heating the elements of the substrate support may be used alone or in combination with a plasma heating the substrate. Once the temperature required for deposition is reached, the source RF is turned off in step 508, but the inert gas continues to flow. Without the source RF, no plasma is present in the chamber. When the source RF is turned off, the deposition gas is inserted into the chamber to mix with the inert gas.

In the Si _x N _y cap layer, the deposition gases typically include a silicon source and a nitrogen source. In a preferred embodiment, the silicon source is SiH ₄ and the nitrogen source is divalent nitrogen (N ₂ ). Alternatively, other organo-silanes such as Si ₂ H ₆ can be used as the silicon source and other nitrogen containing gases such as ammonia (NH ₃ ) can be used as the nitrogen source.

In step 510 a flow rate of the deposition gas is achieved. In a preferred embodiment of Si _x N _y deposition, the flow rate of SiH ₄ is between 16 and 20 sccm and the flow rate of N ₂ is between 230 and 270 sccm. In general, it is necessary to wait for 3-6 seconds for the mass inlet controller in the gas delivery system to achieve the setpoint flow rate. The exact amount of time depends on the individual mass inflow controller of the gas delivery system. Chamber pressure is also established at this point. For low pressure strikes, the chamber pressure is generally between 1 and 100 millitorr. Preferably, the chamber pressure is present at about 40 millitorr or less. In silicon nitride deposition, the chamber pressure is typically between 4 and 7 millitorr at this stage.

Steps 502 through 508 are optional. These steps are used in certain cases where low pressure strike is used to deposit the cap layer continuously while simultaneously depositing the bottom layer of the same chamber. Optionally, the low pressure strike method may begin at gas flow rate and chamber pressure at step 510.

Once the flow rate and chamber pressure have stabilized, a weak plasma can be established in the chamber at step 512. In general, at pressures of approximately 40 millitorr or less, capacitively coupled plasmas are more readily established than inductively coupled plasmas. After the weak plasma is established, the source RF is turned on to establish the deposition plasma in step 514. With the weak plasma, the plasma is low enough to prevent damage to the device formed on the substrate. This capacitively coupled weak plasma can be achieved by applying a direct current (DC) or RF bias to the substrate support member 18 to establish an electric field. In one particular embodiment, the capacitively coupled weak plasma is subjected to substrate bias (eg, BRF generator 31C) at a power between 300W and 1000W, typically between 0.5 and 1.0 seconds, for a bias period of up to 1.0 seconds. Is established by turning on. The actual power depends to some extent on the size of the substrate being processed. For example, for 200 mm substrates the bias power is preferably between 1500 and 2000 W, more preferably approximately 1800 W. The corresponding power density is preferably between 4.8 and 6.4 W / cm ² , more preferably approximately 5.7 W / cm ² . For larger or smaller bias power, the bias power density is approximately the same range and the bias power scale is approximately proportional to the wafer surface area.

Once a weak plasma is established, the source RF is turned on to establish the deposition plasma in step 514 and the substrate bias is turned off at the same time as the source RF is turned on. If the substrate bias is turned off before the source RF is turned on, the plasma is usually turned off undesirably. Thus, there is some overlapping period while both the source RF and bias RF are turned on. In general, this overlapping period generally includes almost the second half of the bias period. For example, if the substrate bias is turned on for a bias period of 0.5 to 1.0 seconds, the source RF is turned on for a time period that overlaps the last 0.25 to 0.5 seconds when the substrate bias is turned on. In general, it is desirable to keep the bias period and overlapping period as short as possible. The lower limit of the bias period and overlapping period usually depends on the response speed of the generator and the electronics providing the substrate bias and source RF signal.

The cap layer is deposited in step 516 using a deposition plasma. In general, the substrate bias is not turned on during silicon nitride deposition. Bias RF is often used during other deposition processes such as silicon dioxide. For a given gas flow rate and a predetermined RF setting, and chamber pressure, the thickness of the deposited cap layer is almost dependent on the deposition time. In general, the longer the deposition time, the thicker the film. Since the flow rate of the deposition gas has already been established prior to plasma strike, the initial deposition is more uniform in the prior art. Therefore, a film of very uniform thickness of 1000 mW or less can be deposited. In the most preferred embodiment, the flow rate is approximately 200 sccm for Ar, 18 sccm for SiH ₄ , and 250 sccm for N ₂ , the source RF is at a total power of approximately 4500 W, and the chamber pressure is approximately 7-8 millimeters. Exists between Thor. Under these conditions, a deposition time between 50 seconds and 60 seconds forms a Si _x N _y film having a thickness between approximately 800 ms and 1000 ms. The silicon nitride film deposited using the low pressure strike described above in the present invention exhibits nonuniformity as low as 2.25%. This is more uniform than the prior art. In addition, the nonuniformity of the low pressure strike deposited film remains approximately constant until at least 65 seconds before deposition begins. Thus, even thin films deposited using low pressure strike (eg, approximately 300 Hz) are quite uniform.

While an embodiment of the method of the present invention has been described above with respect to depositing a silicon nitride cap layer of an FSG layer, other and further embodiments of the present invention can be devised without departing from the basic scope of the present invention. The order of the FSG and the silicon nitride deposition steps may be reversed. That is, a thin film (<1000 μs) silicon nitride layer may be deposited on the substrate using low pressure strike as described above with respect to FIG. 5 and then an FSG layer or other material may be nitrided, for example using HDP-CVD. May be deposited on top of silicon. Silicon nitride acts as a barrier between the FSG and the underlying substrate. In addition, another thin film silicon nitride layer may be deposited as a cap layer on top of the FSG layer using a second low pressure strike. Thus, the FSG will be “sandwiched” between two silicon nitride thin film layers that effectively represent the fragments of the FSG from the underlying substrate and represent the fragments of all layers above the FSG. Such "sandwich" structures are preferred, for example, in damascene applications.

Ⅴ. Typical damascene process

An example of a dual damascene process integration design using the lower k barrier layer deposition described above to form an IMD layer is shown in FIGS. 5 (a) -5 (h). The dual damascene process begins with the deposition of oxide layer 502 on silicon substrate 500 as shown in FIG. 5 (a). The first Si-CH lower k barrier layer 504 is deposited over the oxide layer 502 using, for example, the alkane / silane deposition process described above by HDP-CVD using SiH ₄ and CH ₄ . do. In some applications layer 504 acts as a hardmask or etch stop layer. The first FSG layer 506 is deposited and covered with a patterned photoresist layer 508 during first photolithography as shown in FIG. 5 (b). The first FSG layer 506 may be deposited by the same chamber to enhance process integration. In FIG. 5C, the first etch forms a first set of gaps 510 from the first FSG layer 506 to the hardmask layer 504.

After the first etch, photoresist 508 is stripped, for example, by ashing in an oxidizing environment. The gap 501 and the first FSG layer 506 are covered with a layer such as aluminum or copper. In the case of copper, a seed layer 512 (FIG. 5C) arrives over the gap 501 and the first FSG layer 506. The first bulk copper layer 514 arrives to fill the gap 501 as shown in FIG. 5D. In some applications, a barrier layer (not shown) arrives on the first FSG layer 516 and the gap 510 prior to arrival of the seed layer 512. The barrier layer prevents mixed diffusion of copper and FSG. The copper layer 514 is planarized, for example by CMP. Planarization of the copper layer 514 forms, for example, the first set of copper lines in the interconnect structure.

After planarization of the copper layer 514, the second barrier layer 516, the second FSG layer 518, the third barrier layer 520, and the third FSG layer 522, the IMD layer 521 is formed as shown in FIG. 5E. To arrive. Layers 518, 520 and 522 arrive in the same chamber, such as HDP-CVD, to enhance processing integration to form IMD layer 521. The second resource trap and etching creates a bias 524 through the layers 516, 518, 520 and 522 to the copper layer 514 as shown in FIG. 5F. In FIG. 5 (g), a second set of gaps 526 are created, which are the third lithography and etching. The gap 526 creates a second set of metal lines, and the bias 524 produces a second set of metal lines and an interconnect set of the first set of metal lines made by the gap 510 and the copper layer 514. Bias 524 and gap 526 are filled with a second bulk copper layer and are annealed and planarized as shown in FIG. 5H. The gap 526 creates a second set of metal lines 528 and the bias 524 creates an interconnect set 525 between the second set of metal lines 528 and the first set of metal lines 515.

Since there is currently no available method for etching copper, damascene treatment is used in devices using copper interconnects. Structures formed by damascene treatment do not require a gap fill dielectric and generally provide a lower RC delay than similar structures formed by lowering the metal line aluminum, tungsten, titanium or other metals. In addition, higher gaps are used in damascene processing because gap filling is not an important issue. Any of the barrier layers 506, 516 and 520 may be arrived using the alkane silane barrier layer arrival described above with respect to FIGS. 2, 3 (a), 3 (b), 4 (a) and 4 (b). . Likewise, it is desirable to arrive at one or more barrier layers 506, 516 and 520 as the silicon nitride layer. Since silicon nitride, like FSG and barrier layers, can be arrived by HDP-CVD, this is advantageous in terms of process integration.

Iii. Test results and measurements

In the experiment, a low k film with an FSG layer was deposited on a silicon wafer with and without oxygen treatment. Some films were deposited with and without the silicon nitride cap layer to determine the effect of low pressure strike on the adhesive properties of the silicon nitride cap layer. Umtima manufactured by Applied Materials, Inc. of Santa Clara, California^TMIt was deposited in the HDP-CVD chamber. The chamber comes with a 200mm wafer and is manufactured by Applied Materials.It is disposed in a multichamber substrate processing system. The average fluorine content of the FSG layer was measured in% PHR using an ECO RE series FTIR spectrometer manufactured by Nicolet Instruments of Madison, Wisconsin. Alternatively a Spectrum 2000 FTIR spectrometer manufactured by Perkin-Elmer, Norwalk, Connecticut, may be used. SiO peaks are typically approximately 1090 cm^-OneTo approximately 2005 cm^-OneBetween, preferably about 1097 cm^-OneOccurs with the number of waves. SiF peak values are typically approximately 930 cm^-OneTo approximately 940 cm^-OneBetween, preferably about 935 cm^-OneOccurs with the number of waves.

The stability of the deposited film was determined by thermal desorption spectroscopy (TDS). Samples were cut from each wafer and placed in sample tubes. The sample tube containing the sample is placed in a TDS machine and heated in vacuum to gradually increasing temperatures while measuring the concentration of the various gases released from the sample. The stability of the membrane with the silicon nitride cap layer was confirmed qualitatively by observing the smoke or droplet form. The adhesion properties of the film were determined by the Studd pull test. The film was also tested for stability and adhesion length by chemical mechanical polishing (CMP). Wafers were stored for approximately two weeks to approximately two months under ambient conditions prior to TDS measurements.

In the first and second experiments, the FSG layer was deposited without oxygen treatment or silicon nitride capping. In the first experiment the FSG layer was deposited with a fluorine content of approximately 3.6% PHR. The TDS spectrum for the first experiment is shown in FIG. 7A. In the second experiment, the FSG layer was deposited with a fluorine content of 7.1% PHR. The TDS spectrum for the second experiment is shown in FIG. 7b. Fluorine concentrations were determined by conventional Fourier transform infrared (FTIR) measurements. In the third experiment, the FSG layer was deposited in a two step process with oxygen treatment, as described above. However, no silicon nitride cap layer was deposited on the FSG layer. In a fourth experiment, the FSG layer was deposited in a two step process with oxygen treatment, as described above, and then capped with silicon nitride using low pressure strike. The TDS spectrum for the fourth experiment is shown in FIG. 7d.

The following two experiments compare the effect on oxygen treatment on FSG films capped with silicon nitride using low pressure strike. In each of these two experiments, the TDS sample tube was heated to 1000 ° C., without a wafer sample, to determine the background signal from the gas desorbed from the sample tube. In the fifth and sixth experiments, the FSG layer was deposited and capped with silicon nitride according to the method described above. The fluorine content of the FSG layer, measured in% PHR, was approximately 8.0% in the fifth and sixth experiments. The film in the fifth experiment was deposited without oxygen treatment. The fifth experimental background TDS spectrum is shown in FIG. 7E. Sample TDS spectra and TDS spectra for the fifth experiment are shown in FIG. 7F. The fifth experiment was distinguished from the fifth experiment that the FSG film in the sixth experiment was treated with oxygen before the cap layer of silicon nitride was deposited on top of the FSG layer according to the low pressure strike described above. A sixth experimental background TDS spectrum is shown in FIG. 7G. Sample TDS spectra for the sixth experiment are shown in FIG. 7H.

The TDS spectra shown in the graphs of FIGS. 7A-7H are plots of partial pressures for various gases as a function of wafer temperature. In Figs. 7A-7H, each gas is identified by the atomic mass number indicated in Table I below.

Table I

Mass gas 2 Hydrogen (H ₂ ) 18 Water vapor (H ₂ O) 19 Fluorine (F) 20 Hydrogen Fluoride (HF) 38 Fluorine (F ₂ ) 40 Argon (Ar) 85 Trifluorosilane (SiF ₃ ) 104 Tetrafluorosilane (SiF ₄ )

In experiments 1 to 6, the sample tube containing the wafer sample was slowly heated to approximately 800 ° C. and the partial pressure of desorbed gas was determined using a mass spectrometer. Without the silicon nitride cap layer, a significant amount of gas was released, especially at mass numbers 20 and 19. The TDS schematics for the various gases in FIGS. 7A and 7B show that the gas emissions are significantly higher than the fluorine content of the FSG membrane. In addition, gas emissions are highly dependent on temperature. Gas emissions and temperature dependencies are both stronger in FIG. 7B. This is believed to be due to the higher fluorine content of the FSG layer deposited in the fifth experiment. 7C shows that the oxygen treated film somewhat reduces gas emissions and that the FSG film is relatively stable without the silicon nitride cap layer. There are considerably less off-gases of fluorine shown by the state of the schematic for mass numbers 19, 20, 38, 85 and 104 as compared to FIGS. 7A and 7B. More importantly, there is little fluorine gas emissions in FIG. 7C because the dependence on temperature is quite small. The TDS schematic of FIG. 7D indicates that the film is more stable with a silicon nitride layer. The fluorine off gas is much smaller in FIG. 7D than in FIG. 7C. In addition, there is little emission gas because there is little dependence on temperature.

Even without oxygen treatment, FIGS. 7E and 7F show that the capped FSG membrane shows little or no exhaust gas up to approximately 500 ° C. FIG. 7F shows that signals for various gases are indistinguishable from noise levels even when water vapor (mass 18) present in the background spectrum of FIG. 7E is folded. If FIG. 7F is considered to be the result of the experiment, sharp spikes are present in the mass number 104 at approximately 800 ° C. Similarly, FIGS. 7G and 7H show that the level of the exhaust gas is about the same as the membrane not treated with oxygen and the membrane not treated with oxygen. In addition, any of the exhaust gases which could be generated in FIGS. 7G and 7H was insufficient to cause desorption of the upper silicon nitride cap on the corresponding FSG film.

The adhesion of the film was tested by thermal cycling. For each cycle, the wafer was heated to 400 ° C. under ambient nitrogen. After six cycles, the wafer was observed for desorption of the film. If no desorption was observed, the wafer passed. No desorption caused the adhesion test to fail. The adhesion test results for FIGS. 7A-7D and 7H are summarized in Table II below.

Table II

Experiment Degree Atomic% F O ₂ SI _X N _Y Adhesive force (P / F) One 7a 5 N N Pass 2 7b 10 N N Pass 3 7c 10 Y N Pass 4 7d 10 Y Y Pass 6 7e 10 Y Y Pass

To qualitatively compare the oxygen treatment effects, four wafers with oxygenated silicon nitride caps and four wafers with unoxygenated silicon nitride caps were prepared. Studd pull measurements were performed on the sample yarn of each wafer. The results are listed in Table III below.

Table III

Sample O ₂ Force (LBS) Stress (PSI) One N 101.92 11548.88 2 N 88.16 9990.05 3 N 96.95 10986.34 4 N 103.59 11738.65 5 Y 107.90 12226.63 6 Y 106.58 12077.52 7 Y 106.16 12030.08 8 Y 98.57 11169.33

On average, the silicon nitride capped FSG film deposited by oxygen treatment exhibits higher stability (measured by film stress) than the silicon nitride capped FSG film deposited without oxygen treatment. The difference is not big, but it is nevertheless statistically important.

This result indicates that the method of the present invention can deposit a stable and strongly bonded FSG film having a fluorine concentration of at least 7% as measured by% PHR. In addition, in the integration method of the present invention, the FSG film and the silicon nitride cap layer can be deposited continuously without removing the substrate from the deposition chamber, thereby preferably improving the throughput. Such films may also be used in applications of premetal dielectrics (PMD) and intermetal dielectrics (IMD). It should be appreciated that low pressure striking solves a significant problem with the deposition of layers with thicknesses below 1000 kW using HDP-CVD. Thin film layers deposited by low pressure strike may be used in further applications as barrier layers in gap-filling processes.

Thus far, the present invention has been described with reference to preferred and specific embodiments. Optional embodiments and alternatives will be apparent to those skilled in the art. Accordingly, the invention is limited only by the appended claims.

The present invention has the effect that the silicon nitride layer deposited using low pressure strike exhibits excellent uniformity, strong adhesion and prevents the gas emitted from the lower layer.

Claims (27)

In the method of depositing a multilayer dielectric film on a substrate, Depositing a layer of fluorosilicate glass (FSG) on the substrate; Exposing the FSG layer to an oxygen environment; And Depositing a silicon nitride layer on said FSG layer. The method of claim 1, Wherein said FSG layer contains a fluorine atom concentration of at least about 7.0%, as measured by% peak height ratio (% PHR). The method of claim 1, The oxygen environment is an oxygen plasma. The method of claim 1, wherein depositing the fluorosilicate glass layer comprises: Introducing a silicon containing gas, a fluorine containing gas and an oxygen containing gas into the deposition chamber; Generating a plasma with the silicon containing gas, the fluorine containing gas and the oxygen containing gas; And Depositing the first dielectric layer using the plasma. The method of claim 1, Wherein said FSG layer is deposited using high density plasma chemical vapor deposition (HDP-CVD). The method of claim 1, wherein the silicon nitride layer is: Introducing one or more process gases into the deposition chamber; Striking at low pressure to initiate a plasma with the one or more process gases; And Depositing the second dielectric layer using the plasma. The method of claim 6, wherein the strike at low pressure comprises: Introducing the one or more process gases such that the pressure in the deposition chamber is between 5 and 100 millitorr; Turning on a bias voltage for a period of time sufficient to form a weak plasma in the deposition chamber; After forming the plasma, turning on a source voltage; And After turning on the source voltage, turning off the bias voltage. The method of claim 7, wherein The weak plasma is a capacitively coupled plasma. In the method of depositing a dielectric film on a substrate, Depositing a layer of fluorosilicate glass (FSG) on the substrate at a first atomic ratio of fluorine to oxygen; Exposing the FSG layer to an oxygen environment to stabilize the FSG layer; And Depositing a silicon nitride layer on top of the FSG layer, The FSG deposition, oxygenation, and silicon nitride deposition steps are all performed in the same chamber without removing the substrate from the same chamber. The method of claim 9, And wherein the silicon nitride layer has a thickness of about 1000 GPa or less. The method of claim 9, And wherein said FSG layer is deposited using high density plasma chemical vapor deposition. The method of claim 11, Wherein said dielectric layer contains at least about 7.0% fluorine concentration as measured by% peak height ratio. The method of claim 11, Wherein the FSG layer contains a fluorine concentration between 7.0% and 8.0% as measured by% peak height ratio. The method of claim 11, The FSG layer is exposed to the oxygen environment using an oxygen plasma. The method of claim 9, wherein depositing the dielectric layer comprises: Introducing a silicon containing gas, a fluorine containing gas and an oxygen containing gas into the deposition chamber; Applying a source voltage to the chamber and a bias voltage to the substrate to generate a high density plasma having the silicon containing gas, the fluorine containing gas and the oxygen containing gas; And Depositing the dielectric layer using the high density plasma. 10. The method of claim 9, wherein the silicon nitride layer is: Introducing a silicon containing gas and a nitrogen containing gas into the deposition chamber; Striking at low pressure to initialize the plasma; And Depositing the silicon nitride using the plasma. 17. The method of claim 16, wherein the low pressure strike is: Introducing the silicon containing gas, the nitrogen containing gas and the inert gas such that the pressure of the deposition chamber is between 1 and 100 millitorr; Turning on the bias voltage for a period of time sufficient to form a plasma in the deposition chamber; After forming the plasma, turning on the source voltage; And After turning on the source voltage, turning off the bias voltage. The method of claim 17, The bias voltage is turned on for a bias period of up to 1.0 second. The method of claim 18, Wherein both the source voltage and the bias voltage are turned on during an overlapping period that includes nearly half a half of the bias period. In the method of depositing a dielectric film on a substrate, Introducing a silicon containing gas and a nitrogen containing gas into the deposition chamber; Striking at a first low pressure to initialize the first plasma; Depositing a first silicon nitride layer on the substrate using the first plasma; Depositing a layer of material on the first silicon nitride layer; Introducing a silicon-containing gas and a nitrogen-containing gas into the deposition chamber; Striking at a second low pressure to initialize a second plasma; And Depositing a second layer of silicon nitride on the material layer using the second plasma. The method of claim 20, Wherein the thickness of at least one of the first and second silicon nitride layers is approximately 1000 GPa or less. The method of claim 20, wherein at least one of the first and second low pressure strikes is: Introducing the silicon containing gas, the nitrogen containing gas, and the inert gas such that the pressure in the deposition chamber is between 5 and 100 millitorr; Turning on the bias voltage for a period of time sufficient to form a weak plasma in the deposition chamber; After forming the weak plasma, turning on a source voltage; And After turning on the source voltage, turning off the bias voltage. The method of claim 20, And the material layer comprises fluorosilicate glass (FSG). The method of claim 23, wherein Treating the FSG layer with oxygen. Depositing a layer of fluorosilicate glass (FSG) on the substrate; Exposing the FSG layer to an oxygen environment; And A semiconductor comprising a chamber, a silicon containing gas source, an oxygen containing gas source, a source power supply, and a bias power supply to deposit a low dielectric constant film on a wafer in the chamber according to depositing a silicon nitride layer on the FSG layer. A computer-readable storage medium having embedded program code for controlling a wafer processing system. An apparatus for depositing a low dielectric constant film on a substrate, A deposition chamber; A gas panel coupled to the deposition chamber; A plasma generation system coupled to the chamber; And A controller coupled to the gas panel, the source power supply and the bias power supply, the controller having a computer readable storage medium having embedded program code, wherein the program code includes: Depositing a fluorosilicate glass (FSG) layer on the substrate; Depositing the FSG layer in an oxygen environment; And And controlling the device by depositing a silicon nitride layer on the FSG layer. An apparatus for depositing a low dielectric constant film on a substrate deposited in a deposition chamber, Means for depositing a first dielectric layer on the substrate; And And means for depositing a second dielectric layer having a uniform thickness of about 1000 GPa or less.