KR20010061561A - A etching method of organic-based interlayer dielectric - Google Patents
A etching method of organic-based interlayer dielectric Download PDFInfo
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- KR20010061561A KR20010061561A KR1019990064057A KR19990064057A KR20010061561A KR 20010061561 A KR20010061561 A KR 20010061561A KR 1019990064057 A KR1019990064057 A KR 1019990064057A KR 19990064057 A KR19990064057 A KR 19990064057A KR 20010061561 A KR20010061561 A KR 20010061561A
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- insulating film
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- 238000005530 etching Methods 0.000 title claims abstract description 38
- 239000011229 interlayer Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 14
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000011368 organic material Substances 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 9
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000012044 organic layer Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 층간절연막 관련 기술에 관한 것이며, 더 자세히는 유기물계 층간절연막의 식각 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a technology related to an interlayer insulating film of a semiconductor device, and more particularly, to an etching process of an organic material interlayer insulating film.
반도체 메모리를 비롯한 반도체 소자는 통상 다층 구조로 이루어지는데, 각각의 층을 이루는 전도층 간의 절연을 위하여 층간절연막이 사용되고 있다. 층간절연막으로는 대부분 실리콘산화막 계열의 절연막이 사용되고 있다.BACKGROUND Semiconductor devices, including semiconductor memories, generally have a multilayer structure, and an interlayer insulating film is used to insulate the conductive layers constituting each layer. As the interlayer insulating film, an insulating film based on a silicon oxide film is mostly used.
한편, 반도체 소자의 고집적화가 가속되어 차세대 초고집적 반도체 소자는 그 디자인 룰(design rule)이 0.13㎛ 이하에 이르고 있다. 이와 같은 초미세 디자인 룰을 가지는 반도체 소자에서는 배선간의 피치(pitch)가 매우 작아짐에 따라 배선간 정전용량이 커지는 문제점이 있으며, 이러한 배선간 정전용량의 증가는 RC-지연의 증가를 가져와 소자의 동작 속도를 떨어뜨리는 요인이 되고 있다.On the other hand, high integration of semiconductor devices has accelerated, and the design rules of the next generation ultra high density semiconductor devices have reached 0.13 µm or less. In the semiconductor device having such an ultra-fine design rule, there is a problem in that the capacitance between wires increases as the pitch between wires becomes very small. Such an increase in the capacitance between wires leads to an increase in RC-delay, resulting in operation of the device. It is a factor that slows down.
최근, 이러한 배선의 RC-지연을 줄이기 위한 하나의 방법으로 실리콘산화막에 비해 유전율이 매우 낮은 저유전율 층간절연막을 사용하는 기술이 제안되었다. 이러한 저유전율 층간절연막으로 C-H 체인과 산소(O)의 결합으로 이루어진 폴리머 성분의 유기물계 산화막이 주류를 이루고 있으며, 향후 초고집적 소자 개발의 핵심 기술로 대두되고 있다.Recently, a technique of using a low dielectric constant interlayer insulating film having a very low dielectric constant compared with a silicon oxide film has been proposed as one method for reducing the RC-delay of such wiring. As such a low dielectric constant interlayer insulating film, a polymer-based organic oxide film composed of a combination of C-H chain and oxygen (O) is the mainstream, and has emerged as a core technology for the development of ultra-high density devices in the future.
이러한 유기물계 층간절연막을 사용하는 경우, 콘택홀 식각 공정이나 대머신 금속배선 공정을 위한 트렌치 식각시에 불소계 가스를 식각제로 사용하는데, 이 식각제에 의해 하드 마스크로 사용된 절연막이 함께 식각되어 층간절연막의 손실(loss)을 유발하는 문제점이 발생한다.In the case of using such an organic interlayer insulating film, a fluorine-based gas is used as an etchant in the trench etching for the contact hole etching process or the metallization process of the damascene. A problem that causes loss of the insulating film occurs.
또한, 식각시 유기물계 층간절연막의 측면(lateral) 식각이 유발되어 콘택홀 또는 트렌치 측벽의 네거티브 경사(negative slope)를 유발하거나, 후속 금속 매립시 보이드(void)를 유발하여 반도체 소자의 신뢰도를 저하시키는 문제점이 있었다. 이러한 측면 식각 특성은 고온 식각 공정에서 심하게 나타나기 때문에 통상 상온에서 공정을 진행하는데, 이 경우에도 측면 식각 특성은 완전히 제거되지 않아 해결 과제로 남아 있다.In addition, the sidewall etching of the organic interlayer insulating layer may be caused during etching to cause a negative slope of the contact hole or trench sidewalls, or to cause voids during subsequent metal filling, thereby lowering the reliability of the semiconductor device. There was a problem letting. Since the side etch characteristics are severely shown in the high temperature etching process, the process is usually performed at room temperature. In this case, the side etch characteristics are not completely removed and remain a problem.
첨부된 도면 도 1은 종래기술에 따른 듀얼 대머신 타입 금속배선 형성 공정 중 층간절연막 식각 후의 단면을 도시한 것으로, 측면 식각이 발생하는 지역을 예시하고 있다. 미설명 도면 부호 '10'은 하부 전도층, '11', '13'은 유기물계 층간절연막, '12', '14'는 하드 마스크를 각각 나타낸 것이다.1 is a cross-sectional view after the interlayer dielectric layer is etched during the dual damascene type metallization forming process according to the prior art, illustrating an area where side etching occurs. Reference numeral '10' denotes a lower conductive layer, '11', '13' denotes an organic interlayer insulating layer, and '12' and '14' denote hard masks, respectively.
한편, 첨부된 도면 도 2는 종래기술에 따른 유기물계 층간절연막 식각 후의 단면 SEM(scanning electron microscope) 사진을 도시한 것으로, 유기물계 층간절연막(low-k)의 측면 식각이 발생한 상태를 확인할 수 있다.On the other hand, Figure 2 is a cross-sectional SEM (electron scanning electron microscope) photograph after etching the organic interlayer insulating film according to the prior art, it can be confirmed that the side etching of the organic interlayer insulating film (low-k) occurs. .
본 발명은 하드 마스크의 식각에 의한 유기물계 층간절연막의 손실과 유기물계 층간절연막의 측면 식각 현상을 방지할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing loss of an organic interlayer insulating film due to etching of a hard mask and side etching of the organic interlayer insulating film.
도 1은 종래기술에 따른 듀얼 대머신 타입 금속배선 형성 공정 중 층간절연막 식각 후의 단면도.1 is a cross-sectional view after etching the interlayer insulating film during the dual damascene type metal wiring forming process according to the prior art.
도 2는 종래기술에 따른 유기물계 층간절연막 식각 후의 단면 SEM(scanning electron microscope) 사진.Figure 2 is a scanning electron microscope (SEM) photograph of a cross section after etching an organic interlayer insulating film according to the prior art.
도 3은 본 발명의 일 실시예에 따른 층간절연막 식각 후의 단면 SEM 사진.3 is a cross-sectional SEM photograph after etching the interlayer insulating film according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10 : 하부 전도층10: lower conductive layer
11, 13 : 유기물계 층간절연막11, 13: organic material interlayer insulating film
12, 14 : 하드 마스크12, 14: hard mask
상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자 제조방법은, 소정의 하부층 상에 유기물계 층간절연막을 형성하는 제1 단계와, O2, N2, SO2혼합 가스를 사용하여 -30℃∼0℃의 공정 온도로 상기 유기물계 층간절연막을 선택 식각하는 제2 단계를 포함하여 이루어진다.The characteristic semiconductor device manufacturing method of the present invention for solving the above technical problem, the first step of forming an organic interlayer insulating film on a predetermined lower layer, and using a mixed gas of O 2 , N 2 , SO 2- And a second step of selectively etching the organic-based interlayer insulating film at a process temperature of 30 ° C. to 0 ° C.
즉, 본 발명은 유기물계 층간절연막 식각 공정시 식각제로 종래의 불소계 가스를 대신하여 O2, N2, SO2혼합 가스를 사용하며, 식각시 공정 온도를 0℃ 이하의 저온에서 진행한다. 이때, 적절한 전력 조건을 사용하는 것이 바람직하며, TCP 챔버의 경우 300∼700W의 탑 파워, 50∼200W의 바텀 파워를 사용한다.That is, the present invention uses O 2 , N 2 , SO 2 mixed gas in place of the conventional fluorine-based gas as an etchant during the organic-based interlayer insulating film etching process, the process temperature during etching proceeds at a low temperature of 0 ℃ or less. At this time, it is preferable to use suitable power conditions, and in the case of the TCP chamber, 300-700W of top power and 50-200W of bottom power are used.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
본 실시예에 따른 공정은 우선, 소정의 하부층이 형성된 반도체 기판 상에 유기물계 층간절연막을 증착하고, 그 상부에 하드 마스크층을 증착한다.In the process according to the present embodiment, first, an organic-based interlayer insulating film is deposited on a semiconductor substrate on which a predetermined lower layer is formed, and then a hard mask layer is deposited thereon.
다음으로, 사진 및 식각 공정을 실시하여 하드 마스크층을 패터닝하고, 하드 마스크를 식각 장벽으로 하여 유기물계 층간절연막을 콘택홀 식각을 실시한다.Next, a photomask and an etching process are performed to pattern the hard mask layer, and a contact hole etching is performed on the organic interlayer insulating layer using the hard mask as an etching barrier.
이때, 콘택홀 식각 공정은 TCP(transformer-coupled plasma) 챔버에서 수행하며, 식각 가스로는 O2, N2, SO2혼합 가스를 사용하되 SO2가스의 비율을 전체 가스량의 5∼20%로 제한한다. 또한, 식각시 공정 온도는 -30℃∼0℃가 바람직하며,300∼700W의 탑(top) 파워, 50∼200W의 바텀(bottom) 파워를 사용한다.In this case, the contact hole etching process is performed in a transformer-coupled plasma (TCP) chamber, and as an etching gas, O 2 , N 2 and SO 2 mixed gases are used, but the ratio of SO 2 gas is limited to 5-20% of the total gas amount. do. In the etching process, the process temperature is preferably -30 ° C to 0 ° C, and a top power of 300 to 700W and a bottom power of 50 to 200W are used.
상기와 같이 유기물계 층간절연막의 식각을 실시하는 경우, SiO2가스의 사용과 저온 공정의 적용으로 측면 식각 특성을 최소화할 수 있으며, 하드 마스크의 식각 선택비를 확보할 수 있다.When etching the organic layer-based interlayer insulating film as described above, the side etching characteristics can be minimized by using SiO 2 gas and applying a low temperature process, it is possible to secure the etching selectivity of the hard mask.
첨부된 도면 도 3은 본 발명의 일 실시예에 따른 층간절연막 식각 후의 단면 SEM 사진을 도시한 것으로, 유기물계 층간절연막의 측면 식각이 나타나지 않음을 확인할 수 있다.3 is a cross-sectional SEM photograph after etching an interlayer insulating film according to an embodiment of the present invention, and it can be seen that side etching of the organic-based interlayer insulating film does not appear.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예컨대, 전술한 실시예에서는 유기물계 층간절연막의 식각을 TCP 챔버에서 실시하는 경우를 일례로 들어 설명하였으나, 본 발명은 ICP(inductively-coupled plasma) 챔버와 같이 플라즈마 식각 방식을 사용하는 챔버에서 식각을 진행하는 모든 경우에 적용될 수 있다.For example, in the above-described embodiment, the organic layer-based insulating film is etched in the TCP chamber as an example, but the present invention uses the plasma etching method as in the inductively-coupled plasma (ICP) chamber. Applicable in all cases in which it proceeds.
전술한 본 발명은 유기물계 층간절연막의 측면 식각 특성을 억제하여 콘택홀 또는 트렌치 측벽의 네거티브 경사 발생을 억제하는 효과가 있으며, 하드 마스크의선택비를 확보하여 유기물계 층간절연막의 손실을 방지하는 효과가 있다. 또한, 본 발명은 유기물계 층간절연막 공정의 안정화를 통해 초고집적 소자 개발 기간을 단축할 수 있는 효과가 있다.The present invention described above has the effect of suppressing the side etch characteristics of the organic interlayer insulating film to suppress the occurrence of negative inclination of the contact hole or trench sidewalls, and to secure the selectivity of the hard mask to prevent the loss of the organic interlayer insulating film. There is. In addition, the present invention has the effect of shortening the development period of the ultra-high integrated device through the stabilization of the organic-based interlayer insulating film process.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990064057A KR20010061561A (en) | 1999-12-28 | 1999-12-28 | A etching method of organic-based interlayer dielectric |
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| KR1019990064057A KR20010061561A (en) | 1999-12-28 | 1999-12-28 | A etching method of organic-based interlayer dielectric |
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