KR20010061297A - Bus line driver for high-speed and low power - Google Patents

Abstract

PURPOSE: A bus line driver circuit is provided to reduce a power dissipation by driving a bus line so as to have a voltage swing width of a less magnitude and to secure a rapid driving speed by making a node be charged or discharged. CONSTITUTION: A PMOS transistor(MP1) has a gate connected to receive an input signal, a source connected to an A node and a drain connected to a C node. An NMOS transistor(MN1) has a gate connected to receive the input signal. The source and drain of the transistor(MN1) are connected to C and B nodes, respectively. An inverter inverts a signal of the C node to drive a bus line with the inverted signal. An inverter inverts an output signal of the inverter. An NMOS transistor(MN2) has a gate connected to receive an output signal of the inverter and is connected between VDD and the A node so as to make a voltage swing width of the C node have a level between "VDD-Vtn" and "Vtp". A PMOS transistor(MP3) has a gate connected to receive an output signal of the inverter and is connected between the B node and GND so as to make a voltage swing width of the C node have a level between "VDD-Vtn" and "Vtp". In order to rapidly drive the bus line with a next inverted input signal, an NMOS transistor(MN3) charges the A node and a PMOS transistor(MP2) discharges the B node.

Description

Bus line driver circuit of high speed and low power {BUS LINE DRIVER FOR HIGH-SPEED AND LOW POWER}

The present invention relates to a Very Large Scaled Integrated (VLSI) design technology, and more particularly to a busline driver for driving a busline with high speed and low power consumption.

In VLSI design, interconnection lines or buslines are usually routed long, and buslines are sufficient to drive them because they have large resistance and capacitance for load. I need a driver.

1 is a circuit diagram of a conventional bus driver for driving a bus line or a long interconnect line, and has a simple structure in which a plurality of CMOS inverters 10 and 12 composed of a PMOS transistor and an NMOS transistor are connected.

The conventional bus driver illustrated in FIG. 1 has a problem that the size of the inverter needs to be increased according to the load due to the line length, and also the full-swing of the general VDD (power supply voltage level) / GND (ground voltage level) Full-swing reduces drive speed, resulting in higher power consumption, which adversely affects the performance and cost of the VLSI chip itself.

The present invention has been made to solve the above problems, and an object thereof is to provide a bus line driving circuit which reduces power consumption by driving a bus line to have a smaller voltage swing width.

In addition, the present invention is to provide a bus line driving circuit having a high driving speed by configuring to charge or discharge the node necessary for the transfer of the next opposite value when the line is driven.

1 is a circuit diagram of a conventional bus driver for driving a bus line or a long interconnect line.

2 is a circuit diagram of a bus line driver according to an embodiment of the present invention.

* Description of the main parts of the drawing

MN1, MN2 and MN3: NMOS Transistors

MP1, MP2 and MP3: PMOS Transistors

I1 and I2: Inverter

In order to achieve the above object, the present invention provides a bus line driving circuit in which an input signal of an input terminal is applied to a gate terminal and its source terminal and drain terminal are connected to a first node and a second node, respectively, to pull up an output terminal. A first PMOS transistor for pull-up; A first NMOS transistor for pull-down driving the output terminal by receiving the input signal through a gate terminal thereof, and having a drain terminal and a source terminal thereof connected to the second node and a third node, respectively; The second node is delayed and fed back to its gate terminal, and is connected to a power supply voltage terminal VDD and the first node, the third node, and a ground power supply terminal GND, respectively. A second NMOS transistor and a second PMOS transistor for maintaining a voltage swing width of the node between a first voltage level smaller than a power supply voltage level and a second voltage level greater than a ground voltage level; The inverted delayed and fed back signal of the second node is applied to its gate terminal, respectively, and is connected between a power supply voltage terminal VDD and the first node, the third node, and a ground power supply terminal GND. And a third NMOS transistor and a third PMOS transistor that occupy the first node and discharge the third node for fast driving of the next input signal opposite to the level of the input signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 2 is a circuit diagram of a bus line driver according to an embodiment of the present invention, in which an input signal of an input terminal is applied to a gate terminal, and a PMOS transistor MP1 having its source terminal and drain terminal connected to node A and node C, NMOS transistor (MN1) having an input signal of an input terminal applied to a gate terminal and having its drain and source terminals connected to nodes C and B, and inverting the signal of the node C to drive an inverted signal to a bus line as an output terminal. The inverter I2, the inverter I1 which inverts the inverted signal output from the inverter I2, and the output signal of the inverter I1 is applied to its gate terminal, respectively, and receives VDD, node A, and node B. NMOS transistor (MN2) and PMOS transistor (MP3) connected between GND and GND, respectively, to maintain the voltage swing width of node C at a level between " VDD-Vtn " and " Vtp, " Output of NMOS transistor (MN3), which receives a call and is connected between VDD and node A, and node B and GND respectively, occupies node A and discharges node B for fast driving of the next inverted input signal to be driven by a bus line. And a PMOS transistor MP2.

Operation of the bus line driver of the present invention configured as described above will be described in detail below.

First, when an input signal of "HIGH" is applied to the input terminal, the PMOS transistor MP1 is turned off, the NMOS transistor MN1 is turned on, and the two In response to the signals output through the inverters I1 and I2, the PMOS transistor MP3 and the NMOS transistor MN3 are turned on, respectively, and the NMOS transistor MN2 and the PMOS transistor MP3 are turned off, respectively. At this time, the node C is maintained at the "low" level by the turned-on NMOS transistor MN1 and the PMOS transistor MP3, and is turned on in preparation for the next "low" level input signal. The node A is occupied by " VDD-Vtn " by the NMOS transistor MN3. Here, the "low" level value of the node C is not a complete GND level but a "low" value of the "Vtp" level due to the voltage transfer characteristic of the PMOS transistor MP3. Here, Vtp represents the threshold voltage of the PMOS transistor MP3.

Next, when an input signal of "low" is applied to the input terminal, the PMOS transistor MP1 is turned on, the NMOS transistor MN1 is turned off, and to the signals output through the two inverters I1 and I2. In response, the PMOS transistor MP3 and the NMOS transistor MN3 are turned off, respectively, and the NMOS transistor MN2 and the PMOS transistor MP3 are turned on, respectively. At this time, the node C maintains the "high" level by the turned-on PMOS transistor MP1 and the NMOS transistor MN2, and the PMOS transistor (turned on in preparation for the next "high" level input signal) Node B is discharged to "Vtp" by MP2). Here, the "high" level value of the node C is not a complete VDD level but a "high" value of the "VDD-Vtn" level due to the voltage transfer characteristic of the NMOS transistor MN2. Here, Vtn represents the threshold voltage of the NMOS transistor MN2.

In conclusion, the output signal driven from the bus line driver of the present invention to the bus line as an output terminal has a voltage swing width between "VDD-Vtn-Vtp" due to the voltage transfer characteristics of the NMOS transistor MN2 and the PMOS transistor MP3. It consumes less power than a conventional busline driver driving full-swing, and also has an NMOS transistor (MN3) and a PMOS transistor for the next input current signal and the inverted level input signal. The bus line driving speed is improved by performing charge and discharge operations in advance through MP2.

For reference, the voltage level driven by "VDD-Vtn-Vtp" through the busline driver of the present invention is changed to full-swing voltage through an inverter or the like at the front of the CMOS level circuit when used in a CMOS level circuit. It is then used.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above has the effect of reducing the power consumption by reducing the swing width of the output voltage, and improve the bus driving speed by performing the charge or discharge operation in advance in preparation for the next input signal to be driven. It has an excellent effect.

Claims (3)

In the bus line driving circuit, A pull-up first PMOS transistor configured to receive an input signal from an input terminal as a gate terminal, and have its source terminal and drain terminal connected to a first node and a second node, respectively, to pull up the output terminal; A first NMOS transistor for pull-down driving the output terminal by receiving the input signal through a gate terminal thereof, and having a drain terminal and a source terminal thereof connected to the second node and a third node, respectively; The second node is delayed and fed back to its gate terminal, and is connected to a power supply voltage terminal VDD and the first node, the third node, and a ground power supply terminal GND, respectively. A second NMOS transistor and a second PMOS transistor for maintaining a voltage swing width of the node between a first voltage level smaller than a power supply voltage level and a second voltage level greater than a ground voltage level; The inverted delayed and fed back signal of the second node is applied to its gate terminal, respectively, and is connected between a power supply voltage terminal VDD and the first node, the third node, and a ground power supply terminal GND. A third NMOS transistor and a third PMOS transistor that occupy the first node and discharge the third node for the next fast driving of the input signal opposite to the level of the input signal; High speed and low power bus line driving circuit comprising a. The method of claim 1, wherein the first voltage level, A high-speed and low-power busline driving circuit, wherein the voltage level is reduced by a threshold voltage of the second NMOS transistor at a power supply voltage level. The method of claim 1, wherein the second voltage level, A high speed and low power bus line driving circuit, wherein the voltage level is increased by a threshold voltage of the second PMOS transistor at a ground voltage level.