KR20010060880A - Stacked chip package using lead frame - Google Patents
Stacked chip package using lead frame Download PDFInfo
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- KR20010060880A KR20010060880A KR1019990063338A KR19990063338A KR20010060880A KR 20010060880 A KR20010060880 A KR 20010060880A KR 1019990063338 A KR1019990063338 A KR 1019990063338A KR 19990063338 A KR19990063338 A KR 19990063338A KR 20010060880 A KR20010060880 A KR 20010060880A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 적층 칩 패키지(Stacked chip package)에 관한 것이며, 더욱 구체적으로는 슬롯(Slot)이 구비된 다이패드(Die pad)를 포함하는 리드 프레임(Lead frame)을 이용하여 반도체 칩(Semiconductor chip)들을 적층시킨 것을 특징으로 하는 적층 칩 패키지에 관한 것이다.The present invention relates to a stacked chip package, and more particularly, to a semiconductor chip using a lead frame including a die pad provided with a slot. It relates to a laminated chip package characterized in that these are laminated.
최근의 반도체 기술은 소형화(小形化), 고용량화(高容量化), 고집적화(高集積化) 추세에 있으며, 이에 따라 다양한 형태의 반도체 패키지(Semiconductor package) 구조가 개발되어 있다. 본 발명은 이 중에서 특히 단일 패키지 내에 적어도 두 개 이상의 반도체 칩들이 적층된 구조의 적층 칩 패키지의 구조에 관하여 기술한다.In recent years, semiconductor technology has been miniaturized, high capacity, and highly integrated. Accordingly, various types of semiconductor package structures have been developed. The present invention particularly relates to a structure of a stacked chip package in which at least two semiconductor chips are stacked in a single package.
도 1은 종래의 리드 프레임(40)을 이용한 적층 칩 패키지(100)를 도시한 단면도이며, 도 1을 참고로 하여 종래의 적층 칩 패키지(100)의 구조 및 제조방법을 간략히 설명하면 다음과 같다.FIG. 1 is a cross-sectional view illustrating a laminated chip package 100 using a conventional lead frame 40. A structure and a manufacturing method of a conventional stacked chip package 100 will be briefly described with reference to FIG. 1 as follows. .
종래의 적층 칩 패키지(100)는 슬롯(48 ; Slot)이 구비된 다이패드(46)와 내부리드(42) 및 외부리드(44)를 포함하는 리드 프레임(40)과, 다이패드 위로 실장되는 비교적 큰 크기의 1차 반도체 칩(10)과, 1차 반도체 칩(10) 위로 접착되는 2차 반도체 칩(20)을 포함한다.The conventional stacked chip package 100 includes a die pad 46 having a slot 48, a lead frame 40 including an inner lead 42 and an outer lead 44, and a die pad 46 mounted on the die pad. A primary semiconductor chip 10 having a relatively large size and a secondary semiconductor chip 20 bonded to the primary semiconductor chip 10 are included.
좀 더 상세히 설명하면, 다이패드(46) 위로 1차 반도체 칩(10)이 실장되고 1차 본딩패드(12)들과 내부리드(42)들이 본딩 와이어(50)를 통해 각각 전기적으로연결되며, 1차 반도체 칩(10) 위로 2차 반도체 칩(20)의 하면이 접착된 후 2차 본딩패드(22)들과 내부리드(42)들이 본딩 와이어(50)를 통해 각각 연결된다.In more detail, the primary semiconductor chip 10 is mounted on the die pad 46, and the primary bonding pads 12 and the inner leads 42 are electrically connected to each other through the bonding wire 50. After the lower surface of the secondary semiconductor chip 20 is bonded onto the primary semiconductor chip 10, the secondary bonding pads 22 and the inner leads 42 are connected to each other through the bonding wire 50.
본딩 와이어(50)는 각 내부리드(42)의 상면에서 이중으로 형성되며, 다이패드(46)와 1차 반도체 칩(10) 사이에 또한 1차 반도체 칩(10)과 2차 반도체 칩(20) 사이에 접착제(30 ; Adhesive)가 개재된다. 마지막으로 1차/2차 반도체 칩(10/20)과 본딩 와이어(50)들 및 내부리드(42)들을 포함하는 영역이 성형수지(60)로 밀봉되어 패키지 몸체를 구성한다.The bonding wires 50 are formed in double on the upper surface of each inner lead 42 and between the die pad 46 and the primary semiconductor chip 10 and also between the primary semiconductor chip 10 and the secondary semiconductor chip 20. An adhesive 30 is interposed between the layers. Finally, the region including the primary and secondary semiconductor chips 10/20, the bonding wires 50, and the inner leads 42 are sealed with the molding resin 60 to form a package body.
이러한 구조의 적층 칩 패키지(100)는 반도체 칩이 두개 적층되어 패키지 전체의 높이가 높아지며, 또한 본딩 와이어(50)가 이중으로 형성되어 있기 때문에 성형수지(60)로 패키지 몸체를 성형하는 과정에서 본딩 와이어(60)가 겹쳐지는 등 불량을 일으킬 수 있다.In the stacked chip package 100 having such a structure, two semiconductor chips are stacked and the height of the entire package is increased, and since the bonding wire 50 is formed in duplicate, bonding in the process of forming the package body with the molding resin 60 is performed. The wire 60 may overlap, causing defects.
도 2는 종래의 리드 온 칩(Lead On Chip)형 리드 프레임(140)을 이용한 적층 칩 패키지(200)를 도시한 단면도이며, 도 2를 참고로 하여 종래의 적층 칩 패키지의 구조 및 제조방법을 설명하면 다음과 같다.FIG. 2 is a cross-sectional view illustrating a stacked chip package 200 using a conventional lead on chip type lead frame 140. Referring to FIG. 2, a structure and a manufacturing method of a conventional stacked chip package are described. The explanation is as follows.
1차 반도체 칩(110) 위로 리드 온 칩용 테이프(132 ; LOC tape)가 개재되어 내부리드(142)가 부착된 후 내부리드들과 본딩패드(112)가 본딩 와이어(150)로 연결되며, 또한, 2차 반도체 칩(210) 위로 리드 온 칩용 테이프(132)가 개재되어 내부리드(142')가 부착된 후 내부리드들과 본딩패드(212)가 본딩 와이어(150)로 연결된다.After the lead on chip tape 132 (LOC tape) is interposed on the primary semiconductor chip 110 and the inner lead 142 is attached, the inner leads and the bonding pads 112 are connected by the bonding wire 150. After the lead-on chip tape 132 is interposed on the secondary semiconductor chip 210, the inner lead 142 ′ is attached to the inner leads and the bonding pads 212 through the bonding wire 150.
이와 같이 반도체 칩(110, 210) 위로 부착되는 내부리드(142, 142')와 내부리드에 일체로 형성된 외부리드(144, 144')를 포함하는 리드 온 칩(Lead On Chip)용 리드 프레임(140, 140')이 사용된 경우에는 각 리드 프레임에 반도체 칩이 실장된 후, 접착제(130)가 개재되어 1차/2차 반도체 칩(110/210)의 하면들이 서로 부착되고 리드 프레임(140, 140')들이 각각 부착된다.As described above, a lead frame for a lead on chip includes an inner lead 142 and 142 'attached to the semiconductor chips 110 and 210 and an outer lead 144 and 144' integrally formed on the inner lead. 140 and 140 'are used, after the semiconductor chip is mounted on each lead frame, the adhesive 130 is interposed so that the lower surfaces of the primary and secondary semiconductor chips 110 and 210 are attached to each other and the lead frame 140 is attached. , 140 ') are attached respectively.
이와 같은 구조의 적층 칩 패키지는 와이어 본딩이 실시된 후 두개의 리드 프레임이 접착되어야 하기 때문에 작업 공정의 어려움이 있으며, 적층되는 반도체 칩들이 서로 동일한 종류의 것으로 한정되어야 하는 제한이 있고, 특히 리드 프레임 간에 접착 불량이 발생하는 등의 기술적 어려움이 있다.The stacked chip package having such a structure has a difficulty in working process because two lead frames must be bonded after wire bonding is performed, and there is a limitation that the stacked semiconductor chips should be limited to the same kind of each other. There are technical difficulties such as poor adhesion between the liver.
본 발명의 목적은 두개의 반도체 칩을 적층하면서 단일 리드 프레임을 이용한 것을 특징으로 하는 적층 칩 패키지를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a stacked chip package characterized in that a single lead frame is used while stacking two semiconductor chips.
본 발명의 다른 목적은 패키지의 높이를 최소화할 수 있는 리드 프레임을 이용한 적층 칩 패키지를 제공하는 것이다.Another object of the present invention is to provide a laminated chip package using a lead frame that can minimize the height of the package.
도 1은 종래의 적층 칩 패키지를 도시한 단면도,1 is a cross-sectional view showing a conventional stacked chip package;
도 2는 종래의 리드 온 칩형 리드 프레임을 이용한 적층 칩 패키지를 도시한 단면도,2 is a cross-sectional view showing a laminated chip package using a conventional lead-on chip type lead frame,
도 3은 본 발명의 일 실시예에 따른 리드 프레임을 이용한 적층 칩 패키지를 도시한 단면도이다.3 is a cross-sectional view illustrating a stacked chip package using a lead frame according to an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10, 110, 210 : 1차 반도체 칩 12, 112, 212 : 1차 본딩패드10, 110, 210: Primary semiconductor chip 12, 112, 212: Primary bonding pad
20, 120, 220 : 2차 반도체 칩 22, 122, 222 : 2차 본딩패드20, 120, 220: Secondary semiconductor chip 22, 122, 222: Secondary bonding pad
30, 130, 230 : 접착제(Adhesive) 40, 140, 240 : 리드 프레임30, 130, 230: adhesive 40, 140, 240: lead frame
42, 142, 242 : 내부리드 44, 144, 244 : 외부리드42, 142, 242: inner lead 44, 144, 244: outer lead
46, 246 : 다이패드 48, 148 : 슬롯(Slot)46, 246: Die Pad 48, 148: Slot
50, 150, 250 : 본딩 와이어50, 150, 250: bonding wire
60, 160, 260 : 성형수지60, 160, 260: molding resin
100, 200, 300 : 적층 칩 패키지(Stacked chip package)100, 200, 300: Stacked chip package
이러한 목적들을 달성하기 위하여 본 발명은 슬롯이 구비된 다이패드와 다이패드를 중심으로 배열된 내부리드들 및 각 내부리드에 일체로 형성된 외부리드들을 포함하는 리드 프레임과; 다이패드 위로 실장되는 1차 반도체 칩과; 1차 반도체 칩에 실장되는 2차 반도체 칩과; 1차/2차 반도체 칩들의 본딩패드와 내부리드들을 각각 전기적으로 연결하는 본딩 와이어들; 및 1차/2차 반도체 칩들과, 본딩 와이어들, 다이패드 및 내부리드들을 포함하는 영역을 밀봉하는 성형수지;를 포함하는 적층 칩 패키지에 있어서, 2차 반도체 칩의 하부면은 다이패드의 슬롯을 통하여 1차 반도체 칩의 하부면에 접착되고, 1차/2차 본딩패드들은 각각 내부리드의 상하면에 연결되는 것을 특징으로 하는 리드 프레임을 이용한 적층 칩 패키지를 제공한다.In order to achieve the above object, the present invention provides a lead frame including a die pad provided with a slot, inner leads arranged around the die pad, and outer leads formed integrally with each inner lead; A primary semiconductor chip mounted on the die pad; A secondary semiconductor chip mounted on the primary semiconductor chip; Bonding wires electrically connecting the bonding pads and the inner leads of the primary and secondary semiconductor chips, respectively; And a molding resin for sealing the region including the primary and secondary semiconductor chips and bonding wires, the die pad, and the inner leads, wherein the bottom surface of the secondary semiconductor chip is a slot of the die pad. It is adhered to the lower surface of the primary semiconductor chip through, and the primary / secondary bonding pads provide a laminated chip package using a lead frame, characterized in that each connected to the upper and lower surfaces of the inner lead.
본 발명의 특징에 따른 적층 칩 패키지에 있어서, 1차/2차 반도체 칩들은 실리콘 접착제(Silicone adhesive)가 개재되어 접착되는 것을 특징으로 하며, 또한 내부리드들의 상하면은 각각 도금된 것을 특징으로 한다.In the stacked chip package according to the feature of the present invention, the first and second semiconductor chips are characterized by being bonded with a silicone adhesive (Silicone adhesive), and also characterized in that the upper and lower surfaces of the inner leads are each plated.
이하, 첨부도면을 참고로 하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명의 일 실시예에 따른 슬롯(248)이 구비된 다이패드(246)를 포함하는 리드 프레임(240)을 이용한 적층 칩 패키지(300)를 도시한 단면도이며, 도 3을 참고로 하여 본 발명에 따른 적층 칩 패키지(300)의 구조를 설명하면 다음과 같다.3 is a cross-sectional view illustrating a stacked chip package 300 using a lead frame 240 including a die pad 246 having a slot 248 according to an embodiment of the present invention. Referring to FIG. The structure of the stacked chip package 300 according to the present invention will be described below.
본 발명에 따른 적층 칩 패키지는 슬롯(248)이 구비된 다이패드(246)와 다이패드를 중심으로 배열된 내부리드(242)들 및 각 내부리드(242)에 일체로 형성된 외부리드(244)들을 포함하는 리드 프레임(240)을 이용한 것을 특징으로 한다.The stacked chip package according to the present invention includes a die pad 246 having a slot 248, inner leads 242 arranged around the die pads, and an outer lead 244 integrally formed with each inner lead 242. It characterized in that the lead frame 240 including the.
다이패드(246) 위에 실리콘 접착제(Silicone adhesive)와 같은 접착제(230)가 개재되어 1차 반도체 칩(210)이 실장되며 1차 본딩패드(212)들이 내부리드(242)의 상면에 각각 본딩 와이어(250)로 연결된다.An adhesive 230 such as a silicone adhesive is interposed on the die pad 246 so that the first semiconductor chip 210 is mounted, and the first bonding pads 212 are bonded to the upper surface of the inner lead 242, respectively. Connected to 250.
종래와는 달리 다이패드(246)의 슬롯(248)을 통하여 2차 반도체 칩(220)이 1차 반도체 칩(210)에 접착되며, 이때 2차 반도체 칩의 하면과 1차 반도체 칩의 하면이 부착됨으로써 각 본딩패드들(212, 222)이 노출될 수 있도록 한다. 2차 반도체 칩이 접착되고, 2차 본딩패드(222)들이 내부리드(242)들의 하면에 본딩 와이어로 연결된 후, 다이패드(246)와 내부리드(242)들과 1차/2차 반도체 칩(210/220)들 및 본딩 와이어(250)들을 포함하는 영역이 성형수지(260)로 몰딩되어 패키지 몸체가 형성된다.Unlike the related art, the secondary semiconductor chip 220 is bonded to the primary semiconductor chip 210 through the slot 248 of the die pad 246, wherein the lower surface of the secondary semiconductor chip and the lower surface of the primary semiconductor chip are Attachment allows each of the bonding pads 212 and 222 to be exposed. After the secondary semiconductor chip is bonded and the secondary bonding pads 222 are connected to the bottom surface of the inner leads 242 by bonding wires, the die pad 246 and the inner leads 242 and the primary / secondary semiconductor chip are attached. The area including the 210 and 220 and the bonding wires 250 is molded with the molding resin 260 to form a package body.
이때, 내부리드들은 상하면에서 각각 본딩 와이어가 본딩되어야 하기 때문에 상하면 모두 도금되는 것이 바람직하다.At this time, the inner leads are preferably plated on both the upper and lower surfaces since the bonding wires must be bonded on the upper and lower surfaces, respectively.
이와 같은 구조의 적층 칩 패키지는 다이패드의 슬롯을 통하여 반도체 칩들이 적층되기 때문에 패키지 전체의 높이를 줄일 수 있는 이점이 있으며, 적층되는 반도체 칩들이 동일한 종류의 것이 아니더라도 자유롭게 적층될 수 있다. 또한, 적층되는 반도체 칩들이 각각 하면으로 접착되기 때문에 접착으로 인하여 반도체 칩의 표면에 손상이 가지 않는다.The stacked chip package having such a structure has an advantage of reducing the overall height of the package because the semiconductor chips are stacked through the slots of the die pad, and the stacked semiconductor chips may be freely stacked even if they are not the same type. In addition, since the stacked semiconductor chips are bonded to each lower surface, the surface of the semiconductor chip is not damaged due to the adhesion.
본 발명에 따른 적층 칩 패키지는 슬롯이 구비된 다이패드를 포함하는 리드 프레임을 이용하고, 슬롯을 통하여 적층되는 반도체 칩들의 하면이 접착되는 것을 특징으로 하며, 이러한 구조적 특징을 통하여 패키지 전체의 높이가 최소화되면서 적층 칩 패키지를 제공할 수 있다. 또한, 기존의 다이패드를 포함하는 리드 프레임 구조를 사용할 수 있기 때문에 새로운 구조의 리드 프레임을 제작하는 등의 별도의 리드 프레임 제조비용을 필요로 하지 않으며, 기존의 공정 장치를 활용할 수 있는 등 공정상의 작업효율이 향상될 수 있다.In the stacked chip package according to the present invention, a lead frame including a die pad having a slot is used, and the bottom surface of the semiconductor chips stacked through the slot is bonded to each other. Minimized stack chip packages can be provided. In addition, since the lead frame structure including the existing die pad can be used, there is no need for a separate lead frame manufacturing cost such as manufacturing a lead frame with a new structure, and the existing process equipment can be utilized. Work efficiency can be improved.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063338A KR20010060880A (en) | 1999-12-28 | 1999-12-28 | Stacked chip package using lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063338A KR20010060880A (en) | 1999-12-28 | 1999-12-28 | Stacked chip package using lead frame |
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| Publication Number | Publication Date |
|---|---|
| KR20010060880A true KR20010060880A (en) | 2001-07-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990063338A KR20010060880A (en) | 1999-12-28 | 1999-12-28 | Stacked chip package using lead frame |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000063142A (en) * | 2000-02-17 | 2000-11-06 | 이응찬 | Starting materials for manufacturing polyorganosilsesquioxanes, polyorganosilsesquioxanes and method for manufacturing polyorganosilsesquioxanes |
| KR100532947B1 (en) * | 2002-07-11 | 2005-12-02 | 주식회사 하이닉스반도체 | Method for stacking and packaging first and second semiconductor chip with center pads on their circuit formation surfaces |
-
1999
- 1999-12-28 KR KR1019990063338A patent/KR20010060880A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000063142A (en) * | 2000-02-17 | 2000-11-06 | 이응찬 | Starting materials for manufacturing polyorganosilsesquioxanes, polyorganosilsesquioxanes and method for manufacturing polyorganosilsesquioxanes |
| KR100532947B1 (en) * | 2002-07-11 | 2005-12-02 | 주식회사 하이닉스반도체 | Method for stacking and packaging first and second semiconductor chip with center pads on their circuit formation surfaces |
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