KR20010059875A - apparatus for Direct Memory Access transfer using single address mode - Google Patents

Abstract

PURPOSE: A DMA transmitter using a single address mode is provided to rapidly transmit data by preventing waste of a memory in a DMA transmission between a memory device having different buses and peripheral devices. CONSTITUTION: A memory(10) reads or writes data in order. A peripheral device(20) corresponds to a reading/writing of the data in the memory(10). A multiplex buffer unit(32) is located between the memory(10) and the peripheral device(20). In addition, the multiplex buffer unit(32) interfaces the reading/writing between the memory(10) separated into a plurality of areas and the peripheral device(20). A buffer control unit(31) generates a signal for controlling the multiplex buffer unit(32). A control unit(40) controls a transmission between the memory(10) and the peripheral device(20).

Description

DMA transmission device using single address mode {apparatus for Direct Memory Access transfer using single address mode}

FIELD OF THE INVENTION The present invention relates to direct memory access (DMA) transfers, and more particularly to single-address mode DMA transfers between memory having 32-bit data bus lines and peripherals having different size data bus lines. .

With the recent development of IC integrated technology, the use of embedded controllers in which a CPU core, a DMA controller, a DRAM memory controller, and the like are integrated in a single chip is increasing.

In addition, most of these products require high speed data transfer between memory and peripheral devices in order to cope with the recent multi-media environment, and for this purpose, the DMA controller embedded in the embedded controller is used.

There are two types of DMA transfer methods. First, the dual-address mode is used to transfer data between memory and memory, or to transfer data between memory and peripheral devices having different data bus lines. DMA transfers,

Second, there is a memory with the same data bus line and a single address mode direct memory access (DMA) transfer that can transfer data at higher speeds in the peripheral period.

First, the dual address mode DMA transfer is a read cycle for reading data from a source of data to be transmitted to a DMA buffer and a write cycle for writing the buffered data to a destination. Two access cycles (write cycles) occur during one data transfer.

This dual-address mode DMA transfer allows two devices to be of different size because a DMA buffer can be placed between the source and destination devices, allowing the DMA buffer to be packed / unpacked to fit the data bus line. DMA transfer is possible even with a data bus line.

In the second single address mode DMA transfer, data transfer is performed in one read cycle or write cycle in the case of memory and peripheral period transfer without buffering the data.

Therefore, single address mode DMA transfers have the advantage of faster data transfer than double address mode DMA transfers, but because there is no means to pack / unpack data like dual address mode DMA transfers, The disadvantage is that the devices cannot be used if they have different data bus lines.

In recent years, many embedded controllers have more than 32-bit CPU cores, and most users are using the transfer of 32-bit data bus lines for DRAM memory access for product performance.

However, the peripherals used in these products often use 16-bit or 8-bit data bus lines.

Therefore, data transfer between a memory having a 32-bit data bus line and a peripheral device having a 16-bit or 8-bit data bus line uses dual address mode direct memory access (DMA) transfers and the memory in a manner to speed up the transfer. A single address mode DMA transfer is used, which uses a method that leaves some of the area blank.

Next, the data transfer between the memory and the peripheral device having data bus lines of different sizes will be described with reference to the drawings.

First, the dual address mode DMA transfer shown in FIG. 1 is as follows.

For simplicity, the data bus line size of the peripheral device is assumed to be 16 bits.

First, data transfer from a memory 1 having a 32-bit data bus line (hereinafter abbreviated as memory) to a peripheral device 2 having a 16-bit size data bus line (hereinafter abbreviated as a peripheral device) is performed by the peripheral device ( In 2), a DMA is requested to a DMA controller (hereinafter referred to as DMAC) buffer 3, and the DMAC buffer 3 transmits the address of the memory in which the requested data is stored to the memory 1.

The memory 1 then transfers data corresponding to the received address from the memory 1 to the DMAC buffer 3 during a read cycle.

The DMAC buffer 3 transmits an acknowledgment signal to the peripheral device 2, and simultaneously separates 32-bit data stored in the DMAC buffer 3 into two 16-bit data and writes to the peripheral device 2 twice. Each of these data is transmitted during the cycle.

The data transfer from the peripheral device 2 to the memory 1 requests the control right of the bus to the direct memory access (DMA) from the peripheral device 2 to the DMAC buffer 3, and the DMAC buffer 3 controls the control right of the bus. An acknowledgment signal is transmitted to the peripheral device 2 according to the request.

Then, the peripheral device 2 transmits the 16-bit data to be transmitted to the DMAC buffer 3 by dividing the 32-bit data in two read cycles.

The DMAC buffer 3 then transmits the two stored 16-bit data together with the address to be stored in the memory 1 by executing one write cycle.

As such, the DMA transfer from the memory 1 to the peripheral device 2 or from the peripheral device 2 to the memory 1 takes one data transfer for three access cycles.

Next, the single address mode DMA transfer shown in FIGS. 2 and 3 is as follows.

First, when the peripheral device 2 requests a bus control right to the DMA from the DMA controller (hereinafter abbreviated as DMAC) 4, the DMAC 4 transmits the address of the requested data to the memory 1, and then the peripheral device. The acknowledgment signal according to the request is transmitted to (2).

In this case, the memory 1 is divided into first and second memories 1a and 1b so as to have a memory area of 16 bits, and the first memory 1a (or the second memory 1b) is left blank. Data is stored in another second memory 1b (or first memory 1a).

Therefore, when transferring data from the memory 1 to the peripheral device 2, the second memory 1b (or the first memory 1a) in which the data is stored is transferred during the read cycle by the direct memory access (DMA) control. To send).

During the next read cycle, the next data is transferred from the fourth memory 1d (or the third memory 1c), which is another memory area, to the peripheral device 2.

Subsequently, when the DMA transfer from the peripheral device 2 to the memory 1 is requested, when the peripheral device 2 requests a bus control right from the peripheral device 2 to the DMAC 4, the DMAC 4 transmits the address of the data to the memory 1. After the transmission, the acknowledgment signal according to the bus control right request is transmitted to the peripheral device 2.

The peripheral device 2 then transmits 16 bits of data into the memory 1 during the second write cycle of the second memory 1b (or the first memory 1a) and the fourth memory 1d (or the third memory ( 1c)) respectively.

At this time, the first memory 1a (or the second memory 1b) or the third memory 1c (the fourth memory 1d) is left blank.

Therefore, 32-bit data is transferred in two read or write cycles.

However, the conventional direct memory access (DMA) transfer described above has the following problems.

First, in the case of the dual address mode DMA transfer, the transfer time is delayed because the transfer occurs in one read cycle and two write cycles.

Second, in case of single address mode DMA transfer, there is a disadvantage that a waste of memory and a delay due to code execution for data packing / unpacking occur in the memory.

Third, since most embedded controllers have a DRAM memory controller embedded in the chip, information on the transfer size (32 bits, 16 bits, or 8 bits) and valid data bytes can be located at the time of DRAM write access. There is a problem that is not provided.

Accordingly, the present invention has been made to solve the above problems, and provides a DMA transfer apparatus using a single address mode in which fast transfer is performed while reducing memory waste in DMA transfers between memory devices and peripheral devices having different data buses. The purpose is to provide.

1 is a block diagram illustrating a dual address mode DMA transfer according to the prior art.

2 is a block diagram illustrating a single address mode DMA transfer according to the prior art.

3 is a block diagram showing a transfer between a memory and a peripheral device using different bus lines in a single address mode DMA transfer according to the prior art;

4 is a block diagram showing a DMA transfer using a single address mode according to the present invention.

5 is a circuit diagram of a buffer controller according to the present invention.

6 is a block diagram showing a DMA transfer between a memory having a 32-bit data bus line and a peripheral having a 16-bit data bus line in accordance with the present invention.

7 is a timing diagram of signals used in DMA data transmission according to the present invention.

8 is a block diagram showing a DMA transfer between a memory having a 32-bit data bus line and a peripheral having an 8-bit data bus line in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

10, 10a: memory 20: peripheral device

31: buffer control section 32, 32a: multiplex buffer section

40: buried control unit

A feature of the DMA transfer apparatus using the single address mode according to the present invention for achieving the above object is to sequentially read or read data in a memory divided into a plurality of areas and peripheral periods connected by different bus lines with the memory. In a write DMA transfer, a multiplex buffer unit for interfacing reads or writes between a memory and a peripheral device located between the memory and the peripheral device and divided into the plurality of areas, and a buffer control unit controlling the multiplex buffer unit. It is configured to include.

Another feature of the present invention is to inform a part of the address information of the memory accessed by the buffer controller to the outside of the chip through the existing address pins A1 and A0.

According to an aspect of the present invention, a multiplex buffer unit is formed between a memory and a peripheral device, so that a single mode DMA transfer can be performed between a memory having a different data bus line and a peripheral period, thereby reducing the speed of the transfer and the waste of the memory.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of a DMA transfer apparatus using a single address mode according to the present invention will be described with reference to the accompanying drawings.

Control signals used for DMA control are used under various names for each chip maker.

Therefore, the following description will explain the operation using Motorola's DMA control signal and bus signal, DMA transfer between a DRAM memory having a 32-bit data bus and a peripheral device having a 16-bit data bus line as an example. Let's do it.

The configuration of the DMA transfer apparatus using the single address mode according to the present invention is shown in the block diagram of FIG.

Referring to FIG. 4, the memory 10 is divided into a plurality of areas and sequentially reads or writes data in each area, and a peripheral device corresponding to the read and write of data in the memory 10. 20 and a multiplex buffer unit 32 positioned between the memory 10 and the peripheral device 20 to interface reads or writes between the memory 10 and the peripheral device 20 divided into the plurality of areas. A buffer control unit 31 for generating a signal for controlling the multiplex buffer unit 32, and a buried control unit 40 for controlling the transfer between the memory 10 and the peripheral device 20.

The multiplex buffer section 32 is composed of FCT 16245, which is a 245 buffer of two 16-bit lines.

Referring to the operation of the DMA transmission apparatus using the single address mode configured as described above, when the value of '1' is input to OE1 and OE2 through the output enable pin of each buffer 32, the 16-bit input terminal signal It is delivered to the output of 16 bits.

At this time, the direction of input / output is determined by the value of the signal applied to the direction pin (DIR).

When the DIR value is '1', data is transferred from the memory 10 to the peripheral device 20. When the DIR value is '0', data is transferred from the peripheral device 20 to the memory 10.

The buffer controller 31 generates a signal for controlling the multiplex buffer unit 32 using signal information related to a cycle output from the embedded controller 40.

The signal from the embedded control unit 40 used here knows the chip select signal for the peripheral device 20, or the signal R / nW indicating whether it is a write cycle, and the position on the data bus of the currently accessed 16-bit data. Address line signal A1, which is information that can be used.

The circuit of the buffer controller is configured as shown in FIG. 5, and is represented by the following equation.

[Logic 1]

OE1 = (! FC3 &! NCS) # (FC3 &! A1);

OE2 = FC3 &A1;

DIR = (! FC3 &! R / nW) # (FC3 & R / nW);

The control signals OE1, OE2, and DIR of the buffer controller 31 are connected to the respective 16245 buffers of the multiplex buffer unit 32 as shown in FIG. 6.

When each signal is connected in this way, nCS becomes '0' during normal access to the peripheral device 20 from the CPU, and the data line is only 16245 buffers connected to D [31:16], which is the upper area of the memory. This is enabled, and the data transfer direction is determined at the time of data read and at the time of data write by the R / nW signal.

At this time, the 16245 buffer connected to the lower portion of the data line D [15: 0] is always write disabled.

The operation during DMA (Direct Memory Access) transfer is as follows.

First, at the time of DMA transfer, a control register of the DMA control unit is configured.

In this case, the DMA transfer size is 16 bits and the DMA transfer mode is a single address mode.

In the case of the transfer from the memory 10 to the peripheral device 20, or in the case of the transfer from the peripheral device 20 to the memory 10, the address of the memory is input to the destination address register and the transfer counter register is inputted. After setting, start DAM transmission.

At this time, the embedded controller 40 waits for the DREQ, which is a DMA transfer request signal from the outside, to be activated.

The peripheral device 20 is set to the DMA transfer mode, and the peripheral device 20 then activates the DREQ signal.

The embedded control unit 40 receiving the DREQ signal transmits a DACK, which is a DMA acknowledgment signal, to the peripheral device 20 after obtaining the control right of the bus, and the address and transfer size of the DRAM are stored in the memory control unit in the embedded control unit 40. Apply a signal of 16 bits.

At the same time, the DMA space function code FC3, the read / write signal R / nW, and the address line signal A1 are released off the chip.

At this time, since the data bus line of the DRAM memory 10 is set to 32 bits, the memory controller ignores the values of the address lines A1 / A0 during the DMA read cycle (transfer from the memory to the peripheral device) for the memory 10. 32-bit access to memory 10 is achieved by activating CASs, which are column address strobe signals.

At the same time, the buffer control section 31, from the input FC3 (== '1'), A1, R / nW (== '1') signals, according to the value of A1, OE1 = '1. ', OE2 =' 0 'is outputted, and when A1 ==' 1 ', OE1 =' 0 'and OE2 =' 1 'are outputted.

By outputting DIR as '0', the multiplex buffer unit 32 is controlled to transmit 16-bit data through a valid data bus D [31:16] or D [15: 0].

Subsequently, the embedded control unit 40 performs the next DMA cycle, and at this time, increases the memory address to be accessed by 2 and is made in the above order.

This DAM operation is repeated until the counter value of the DMA counter register becomes '0'.

That is, the description will be briefly made through the embodiment. The transfer from the memory 10 to the peripheral device 20 separates the memory 10 into a first memory and a second memory having 16 bits of data bus lines.

In this case, since the conventional method of storing either data in the first memory or the second memory and leaving the other blank is a waste of memory, in order to solve the problem, in the present invention, the data is stored in the first memory and the second memory, respectively. Save it.

That is, assuming that data to be transmitted in units of 16 bits is' 1 ',' 2 ',' 3 ', ...' 8 ',' 9 ',' 10 ', the' 1 ',' 3 in the first memory. ',' 5 ',' 7 ',' 9 'are stored in the second memory, and' 2 ',' 4 ',' 6 ',' 8 ',' 10 'are respectively stored in the second memory. The multiplex buffer unit 32 transmits data '1', '3', '5', '7', and '9' of the first memory to the peripheral device 20 by the generated OE1 == 1 signal.

The multiplex buffer unit 32 transmits data '2', '4', '6', '8', and '10' of the second memory to the peripheral device 20 by the signal OE2 == 1.

At this time, the 32-bit transmission to the peripheral device 20 is a data transmission during two read cycles.

The transfer from the peripheral device 20 to the memory 10 is stored in the memory 10 through the reverse process of the transfer from the memory 10 to the peripheral device 20, and is also performed during two write cycles of 32-bit data.

Therefore, the memory 10 has no blank area, and data reads or writes with the peripheral device 20 are performed in a short time.

7 is a timing diagram of signals generated during DMA data transfer according to the present invention. For convenience, two DMA transfer cycles from the memory 10 to the peripheral device 20 and two DMA transfers of the memory 10 from the peripheral device 20 are shown. The cycle is assumed to be a burst.

Thus, assuming four bytes (== 32 bits) of contiguous data transfer, a dual address mode DMA transfer would require three DMA cycles, one memory access and two peripheral accesses. In the single address mode DMA transmission using the circuit devised in the present invention, since the transmission is completed in two DMA cycles, it is possible to obtain a faster transmission effect than the double address mode DMA transmission.

FIG. 8 is a connection diagram of signals for DMA transfer between a memory 10a having a 32-bit data bus line and a peripheral device 20 having an 8-bit data bus line. In this case, the logical expressions of OE1 to OE4 and DIR signals are shown in FIG. As follows.

[Logical 2]

OE1 = (! FC3 &! NCS) # (FC3 &! A1 &! A0);

OE2 = FC3 &! A1 &A0;

OE3 = FC3 & A1 &! A0;

OE4 = FC3 &! A1 &! A0;

DIR = (! FC3 &! R / nW) # (FC3 & R / nW);

Since the operation description is the same as the description of the DMA transfer between the memory 10 having the 32-bit data bus line and the peripheral device 20 having the 16-bit data bus line, the description thereof is omitted.

As described above, the DMA transfer apparatus using the single address mode according to the present invention has the following effects.

First, single address mode DMA transfers can be implemented between memory with 32-bit data bus lines and peripherals with 16-bit data bus lines, and data can be transferred faster than conventional double address mode DMA transfers. There is an effect of improving the DMA transfer rate.

Second, when applied to a DTV ready chip having a 16-bit host interface, the performance of the system can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (1)

A memory that divides into a plurality of areas and sequentially reads or writes data in each of the areas; A peripheral device corresponding to reading and writing of data in the memory; And a multiplex buffer unit positioned between the memory and the peripheral device and interfacing read or write between the memory and the peripheral device separated into the plurality of areas.