KR20010059734A - Formation method of dieletric layer of semiconductor device - Google Patents
Formation method of dieletric layer of semiconductor device Download PDFInfo
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- KR20010059734A KR20010059734A KR1019990067261A KR19990067261A KR20010059734A KR 20010059734 A KR20010059734 A KR 20010059734A KR 1019990067261 A KR1019990067261 A KR 1019990067261A KR 19990067261 A KR19990067261 A KR 19990067261A KR 20010059734 A KR20010059734 A KR 20010059734A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
Abstract
Description
본 발명은 반도체 소자의 제조에 있어서, 절연막의 형성방법에 관한 것으로 절연막은 반도체 소자의 속도를 증가시키기 위하여 필요한 것으로서, 초기에는 로직 소자에서부터 그 필요성이 대두되기 시작하였다. 그러나 현재는 메모리 소자에서도 집적도의 증가에 따라 금속배선사이의 간격이 좁아지게 되었으며, 또한 이에 따라 금속배선사이의 기생커패시턴스가 증가하게 되어 그 사용이 검토되고 있는 추세이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating film in the manufacture of a semiconductor device. The insulating film is necessary to increase the speed of the semiconductor device. However, in the current memory device, the gap between the metal wirings is narrowed as the degree of integration increases, and accordingly, the parasitic capacitance between the metal wirings increases, and its use is being examined.
저유전율막의 경우는 폴리머막을 비롯하여 플라즈마 기상증착법에 의한 실리콘산화막(유전율 2.7)이 현재는 널리 평가되고 있다. 폴리머막의 경우는 소자 집적시 다마신 공정과 기존의 메탈서브스트렉티브 에치공정 모두 하드마스크막을 증착하는데 일반적으로 플라즈마 기상화학증착법에 의한 산화막(유전율 4 정도)을 사용한다. 플라즈마 증착가스로는 사일렌(SiH4)과 N2O 혹은 TEOS 와 O2등을 사용한다. 그러나 플라즈마 산화막의 증착시에는 플라즈마 분위기를 생성하기 위하여 플라즈마를 켜기 전 가스안정단계에서 O2또는 N2O 등에 의해 폴리머막과 하드마스크막의 계면이 산화되는 문제점이 있다. 좀 더 자세히 설명하면폴리머막 내의 탄소와 플라즈마 산화막 증착시의 원물질등에 의해 계면에 산화된 중간상이 존재하게 되는데 이를 하기 도 1 에 나타내었다. 우선 산화되기 이전의 폴리머 구조 즉 하드마스크막 증착전의 폴리머 구조는 하기 화학식 1 또는 화학식 2 로 나타낼 수 있다.In the case of the low dielectric constant film, the silicon oxide film (dielectric constant 2.7) by the plasma vapor deposition method, including a polymer film, is currently widely evaluated. In the case of a polymer film, both a damascene process and a conventional metal selective etch process for depositing a device deposit a hard mask film. In general, an oxide film (a dielectric constant of about 4) using a plasma vapor deposition method is used. As the plasma deposition gas, xylene (SiH 4 ) and N 2 O or TEOS and O 2 are used. However, when the plasma oxide film is deposited, there is a problem in that the interface between the polymer film and the hard mask film is oxidized by O 2 or N 2 O in a gas stabilization step before turning on the plasma to generate a plasma atmosphere. In more detail, an intermediate phase oxidized at an interface due to carbon in a polymer film and a raw material during plasma oxide film deposition is shown in FIG. 1. First, the polymer structure before oxidation, that is, the polymer structure before hard mask film deposition may be represented by the following Chemical Formula 1 or Chemical Formula 2.
상기와 같은 폴리머 구조 [화학식 1 - (C46H36O3)n, 화학식 2 - (C86H56O)n]가 하드마스크막(104)를 증착하게 되면, 플라즈마의 원물질인 N2O, O2에 의해 산화되어 구조변화 [(CxHyO)n] 를 일으키게 되며, 하기 도 1 과 같이 하드마스크막(104)과 폴리머막(102)의 사이에 중간상(103)이 생기게 되는 것이다.Polymer structure as described above [Formula 1-(C46H36O3)n, Formula 2-(C86H56O)n] Deposits the hard mask film 104, N, which is a raw material of plasma.2O, O2Oxidized by the structural change [(CxHyO)n], An intermediate phase 103 is formed between the hard mask film 104 and the polymer film 102 as shown in FIG.
따라서 폴리머막과 하드마스크막 계면의 산화등에 의해 접착이 좋지 못할 경우 에칭 공정 후 클리닝 공정에서 클리닝 케미칼에 의해 리프팅이 발생하게 된다. 하기 도 2A 및 도 2B 에서 에칭 후 클리닝 케미칼에 플라즈마 하드마스크막이 리프팅이 일어난 것을 보여주고 있다. 이는 폴리머막을 소자에 적용하기에 매우 어려운 이유가 되고 있다. 반면에 하드마스크막으로 사용되는 산화막의 유전율은 4 정도로 다른 유전율 하드마스크막에 비해 층간 커패시턴스가 높은 편이어서 저유전율의 특성이 상대적으로 좋지 못한 문제점을 갖고 있다.Therefore, when adhesion is not good due to oxidation of the interface between the polymer film and the hard mask film, lifting occurs by the cleaning chemical in the cleaning process after the etching process. 2A and 2B show that the plasma hard mask film is lifted to the cleaning chemical after etching. This is a reason why it is very difficult to apply a polymer film to an element. On the other hand, the dielectric constant of the oxide film used as the hard mask film has a problem that the dielectric constant of the low dielectric constant is relatively poor since the interlayer capacitance is higher than that of other dielectric constant hard mask films.
상기와 같은 문제점을 해결하기 위하여 본 발명은 저유전율 특성을 향상시켜 소자의 구동속도를 증가시키고 전력소모를 감소시킬 수 있는 신규한 절연막의 제조방법을 제공하고자 한다.In order to solve the above problems, the present invention is to provide a novel method of manufacturing an insulating film that can improve the low dielectric constant characteristics to increase the driving speed of the device and reduce the power consumption.
하기 도 1 은 폴리머막 내의 탄소와 플라즈마산화막 증착시의 원물질등에 의해 계면에 산화된 중간상이 형성된 것을 보여주며, 하기 도 2A 및 도 2B는 에치 후 클리닝 공정에서 클리닝 케미칼에 의한 플라즈마의 하드마스크막의 리프팅이 일어난 것을 보여주는 사진이다.1 shows that an oxidized intermediate phase is formed at an interface by carbon in a polymer film and a raw material during plasma oxide film deposition, and FIGS. 2A and 2B show a hard mask film of a plasma by a cleaning chemical in a post-etch cleaning process. This picture shows the lifting.
또한 도 3A 및 도 3B는 폴리머막과 하드마스크막으로 SOG막을 적용한 경우의 메탈 서브스트렉티브 에치 구조를 보여주며, 도 4는 폴리머막과 하드마스크막으로 SOG막을 적용한 경우의 듀얼다마신 구조를 나타낸다.3A and 3B show a metal subtractive etch structure when the SOG film is applied to the polymer film and the hard mask film, and FIG. 4 shows the dual damascene structure when the SOG film is applied to the polymer film and the hard mask film. .
* 도면의 주요부분의 상세한 설명 *Detailed description of the main parts of the drawings
101, 301, 401: 하부구조가 형성된 반도체 기판의 표면 (Underlayer)101, 301, and 401: surface of a semiconductor substrate on which an understructure is formed
102, 202: 폴리머막 103: 산화에 의한 중간상이 형성된 것102, 202: polymer film 103: intermediate phase formed by oxidation
104, 201: 하드마스크막 302: 제 1 금속배선104, 201: hard mask film 302: first metal wiring
303, 402: 저유전 폴리머막303, 402: low dielectric polymer film
304: 플라즈마법에 의한 하드마스크막304: hard mask film by plasma method
305, 403: SOG 하드마스크막 404: 감광막 (photo resist)305 and 403: SOG hard mask film 404: photo resist film
상기와 같은 기술적 과제를 달성하기 위하여 본 발명은 하부구조가 형성된 반도체 기판의 상부에 스핀코팅에 의해 저유전율 폴리머막을 증착한 후, 저유전 폴리머막의 상부에 SOG(Spin on Glass)막을 하드마스크막으로 증착한 후, 후속공정을 행하는 것을 포함하여 이루어지는 것을 특징으로 하는 절연막의 형성방법을 제공한다. .In order to achieve the above technical problem, the present invention deposits a low dielectric constant polymer film by spin coating on top of a semiconductor substrate on which a lower structure is formed, and then spins a glass on glass (SOG) layer on top of the low dielectric polymer film as a hard mask film. After the deposition, there is provided a method of forming an insulating film, which comprises performing a subsequent step. .
본 발명에 따른 절연막의 형성에 있어서, 상기 절연막의 형성은 하부구조가 형성된 반도체 기판의 상부에 스핀 코팅에 의해 저유전 폴리머막을 순차적으로 코팅, 베이크, 큐어링한 후 하드마스크막으로서의 SOG 막을 순차적으로 코팅, 베이크 큐어링한 후 후속공정을 진행하는 것이 바람직하다.In the formation of the insulating film according to the present invention, the insulating film is formed by sequentially coating, baking, and curing a low-dielectric polymer film by spin coating on a semiconductor substrate on which a lower structure is formed, and then sequentially forming an SOG film as a hard mask film. It is preferable to proceed with the subsequent process after coating and baking cure.
상기와 같은 저유전율 절연막의 형성방법에 있어서, 저유전율 폴리머막의 큐어링 단계를 제외하고 진행할 수도 있다. 즉, 저유전 폴리머막의 코팅, 베이크단계 이후 큐어링 없이 SOG 막을 코팅, 베이크, 큐어링하는 방법에 의하여 두번의 큐어링과정을 한번으로 동시에 행할 수 있다.In the method of forming the low dielectric constant insulating film as described above, the process may be performed except for the curing step of the low dielectric constant polymer film. That is, two curing processes may be simultaneously performed by one method by coating, baking, and curing the SOG film without curing after coating and baking of the low dielectric polymer film.
상기한 바와 같은 절연막의 형성방법에 있어서, SOG 막의 코팅, 베이크, 큐어링 단계이후 스핀코팅에 의한 저유전율막의 코팅, 베이크, 큐어링 단계와 SOG 막의 코팅, 베이크, 큐어링 단계를 재실행하여 듀얼 다마신 공법으로 이용할 수도 있다.In the method of forming the insulating film as described above, the coating, baking and curing step of the SOG film and the coating, baking and curing step of the low dielectric constant film by spin coating followed by the coating, baking and curing step are performed. It can also be used as a drinking technique.
본 발명에 따른 절연막의 형성에 있어서, SOG 막은 HSQ-SOG(Hidrogen Silsesquioxane-SOG), MSQ-SOG(Methyl Silsesquioxane-SOG) 및 Siloxane-SOG 로 이루어진 그룹에서 선택된 것을 사용하는 것이 바람직하며, SOG 막의 두께는 500 에서 5000 Å으로 하는 것이 바람직하다.In forming the insulating film according to the present invention, the SOG film is preferably selected from the group consisting of HSQ-SOG (Hidrogen Silsesquioxane-SOG), MSQ-SOG (Methyl Silsesquioxane-SOG) and Siloxane-SOG, and the thickness of the SOG film Is preferably 500 to 5000 kPa.
본 발명에 따른 절연막의 형성에 있어서, 큐어링단계에서의 산소의 열화를 방지하기 위하여 챔버내의 산소농도는 100ppm이하로 하는 것이 바람직하며, 온도는 300 내지 500℃의 온도로 하는 것이 바람직하다.In forming the insulating film according to the present invention, in order to prevent deterioration of oxygen in the curing step, the oxygen concentration in the chamber is preferably 100 ppm or less, and the temperature is preferably 300 to 500 ° C.
상기 하드마스크막으로 SOG막을 얇게 증착하고 플라즈마 산화막을 증착하는 것을 특징으로 하는 반도체 소자 제조공정에 있어서의 절연막의 형성방법.A method of forming an insulating film in a semiconductor device manufacturing process, comprising depositing a thin SOG film with the hard mask film and depositing a plasma oxide film.
본 발명에 따른 절연막의 형성에 있어서, 하드마스크막으로 SOG막을 얇게 증착하고 플라즈마 산화막을 증착하는 방법을 사용할 수도 있다.In forming the insulating film according to the present invention, a method of thinly depositing an SOG film with a hard mask film and depositing a plasma oxide film may be used.
본 발명을 좀 더 구체적으로 설명하기로 한다.The present invention will be described in more detail.
우선 상기한 바와 같은 기상화학증착방법의 산화막에 의한 저유전 폴리머막의 산화를 막기위하여 본 발명에서는 SOG 막으로 하드마스크막을 형성하는 것을 특징으로 한다. 이 때 사용되는 SOG 막은 상기한 바와 같이 HSQ-SOG, MSQ-SOG, Siloxane-SOG 막 등을 주로 사용하는데 이런 종류의 막들은 유전율이 2.7 내지 3.2 정도로 저유전율 특성이 우수하여 기존의 플라즈마 산화막(유잔율 4정도)보다 좋은 저유전율특성을 확보할 수 있다. 또한 플라즈마 등을 사용하지 않기 때문에 플리머막의 산화에 의한 접착특성의 열화를 방지할 수 있는 장점이 있다.First, in order to prevent oxidation of the low dielectric polymer film by the oxide film of the vapor phase chemical vapor deposition method as described above, the present invention is characterized in that a hard mask film is formed of an SOG film. The SOG film used at this time is mainly used as HSQ-SOG, MSQ-SOG, Siloxane-SOG film as described above, these kinds of films have excellent dielectric constant of about 2.7 to 3.2, so the existing plasma oxide film ( Low dielectric constant better than the residual rate 4) can be secured. In addition, since plasma is not used, there is an advantage in that deterioration of adhesion characteristics due to oxidation of the polymer film can be prevented.
또 절연막의 평탄도는 다마신 공정보다는 기존의 메탈 서브스트렉티브 에치 구조에서 후속포토 공정을 위하여 반드시 필요한데, 다공성막의 형성 후 스핀코팅에 의해서 저유전율 SOG 막을 증착하여 상기의 플라즈마 기상화학증착방법에 의한 막보다 평탄도를 향상시킬 수 있는 장점이 있다.In addition, the flatness of the insulating film is necessary for the subsequent photo process in the existing metal sub-etch structure rather than the damascene process. There is an advantage that can improve the flatness than the film.
그러므로 본 발명에서와 같이 저유전율 폴리머막에 저유전율 특성이 우수한 스핀 코팅에 의한 SOG막을 하드마스크막으로 증착하면 플라즈마증착공정에서 O2나 N2O에 의해서 생기는 폴리머막의 산화를 방지할 수 있으며 저유전율 특성 및 평탄화 특성을 향상시킬 수 있게 되는 것이다.Therefore, as in the present invention, if the SOG film by spin coating having excellent low dielectric constant on the low dielectric constant polymer film is deposited as a hard mask film, oxidation of the polymer film caused by O 2 or N 2 O in the plasma deposition process can be prevented and The dielectric constant and planarization characteristics can be improved.
본 발명에서의 절연막을 형성하는 일공정도는 다음과 같다. 이하에서 나타내는 공정도 및 도면은 본 발명을 한정하는 것은 아니다.One process chart for forming the insulating film in the present invention is as follows. The process chart and drawing shown below do not limit this invention.
1. 메탈 서브스트렉티브 에치 스킴(scheme)에서의 공정과정1. Process in Metal Substretch Etch Scheme
1) 금속을 증착한 후 패터닝(포토 및 에치)한다.1) The metal is deposited and then patterned (photo and etched).
2) 스핀코팅에 의해 저유전 폴리머 막을 코팅한다.2) A low dielectric polymer film is coated by spin coating.
3) 저유전율막을 베이크/큐어링한다.3) Bake / cure the low dielectric constant film.
4) 하드마스크막으로 SOG 막을 코팅/베이크/큐어링한다.4) The SOG film is coated / baked / cured with a hard mask film.
5) 후속공정을 행한다. (비아 포토, 에칭 등)5) Follow up the process. (Via photo, etching, etc.)
상기 과정에 의해 이루어진 형태를 기존의 플라즈마 산화막의 경우와 비교하기 위하여 하기 도 3A 에 기존의 플라즈마 산화막의 경우를, 도 3B 에 SOG 막에 의한 상기 과정에 의해 이루어진 경우를 비교하여 나타내었다.In order to compare the shape formed by the above process with that of the conventional plasma oxide film, FIG. 3A shows the case of the conventional plasma oxide film by comparing the case made by the above-described process by the SOG film in FIG. 3B.
하기 도 3A 는 하부구조가 형성된 반도체 기판(301)의 상부에 제1 금속배선(302)을 형성하고 제 1 금속배선(302)의 상부에 저유전폴리머막(303)을 증착한 후 기존의 방법에 의한 플라즈마법에 의한 하드마스크막(304)을 적용한 경우를 나타낸 것이다. 또한 도 3B 는 동일 구조에서 기존의 플라즈마법에 의한 하드마스크막(304) 대신 본 발명에 따른 SOG 하드마스크막(305)을 적용한 경우를 나타낸 것이다. 양 도면에서 알 수 있듯이 하드마스크막의 평탄도에서 본 발명에 따른 저유전율 절연막의 형성방법에 의한 경우가 월등한 것을 알 수있다.3A illustrates a method of forming a first metal interconnection 302 on an upper portion of a semiconductor substrate 301 on which a lower structure is formed, and depositing a low dielectric polymer film 303 on the first metal interconnection 302. The case where the hard mask film 304 by the plasma method is applied is shown. 3B shows a case where the SOG hard mask film 305 according to the present invention is applied instead of the hard mask film 304 by the conventional plasma method in the same structure. As can be seen from the drawings, it can be seen that the method of forming the low dielectric constant insulating film according to the present invention is superior in the flatness of the hard mask film.
2. 다마신 스킴(scheme)에서의 공정과정2. Process in the damascene scheme
1) 스핀코팅에 의해 저유전 폴리머막을 코팅, 베이크, 큐어링한다.1) A low dielectric polymer film is coated, baked and cured by spin coating.
2) 하드마스크막으로 SOG 막을 코팅/베이크/큐어링한다.2) The SOG film is coated / baked / cured with a hard mask film.
3) 1)-2)의 과정을 재실행한다.3) Repeat the process of 1) -2).
4) 후속공정을 행한다. (포토, 에칭, 금속증착 등)4) Follow up the process. (Photo, etching, metal deposition, etc.)
상기 과정에 있어서 3)의 과정을 제외한 것이 싱글 다마신 공법, 3)의 과정을 포함한 것이 듀얼다마신 공법이다. 듀얼다마신 공법에 의한 결과를 하기 도 4에 나타내었다.In the above process, except for the process of 3), the single damascene method, and the process including 3) are the dual damascene method. The results by the dual damascene method are shown in FIG. 4.
상기와 같은 방법에 의한 본 발명에 의한 절연막의 형성에 의하여 저유전율 특성이 우수한 SOG 막을 하드마스크막으로 증착하여 폴리머 산화방지 효과를 나타내며, 저유전율특성 및 평탄화 특성을 향상시킬 수 있다.By forming the insulating film according to the present invention by the above-described method, a SOG film having excellent low dielectric constant characteristics is deposited as a hard mask film to exhibit a polymer antioxidant effect, and low dielectric constant and planarization characteristics can be improved.
또한 본 발명에 따른 절연막의 적용에 의하여 유기물인 폴리머막의 소자집적을 안정적으로 구현할 수 있으며 기존의 방법보다 소자의 RC 지연시간을 최소화 할 수 있으며, 전력소모 및 금속배선사이의 신호간섭(cross talk)를 줄일 수 있어 구동속도를 증가시킬 수 있으며, 소자특성이 향상된다.In addition, by applying the insulating film according to the present invention, the device accumulation of the polymer film, which is an organic material, can be stably realized, and the RC delay time of the device can be minimized, compared to the conventional method, and the signal talk between power consumption and metal wiring (cross talk) It can reduce the driving speed can be increased, and the device characteristics are improved.
Claims (9)
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| KR100727439B1 (en) * | 2005-03-22 | 2007-06-13 | 주식회사 하이닉스반도체 | Method for forming interconnection line |
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|---|---|---|---|---|
| JPH02249226A (en) * | 1989-03-23 | 1990-10-05 | Matsushita Electric Ind Co Ltd | Resist forming method |
| US5312512A (en) * | 1992-10-23 | 1994-05-17 | Ncr Corporation | Global planarization using SOG and CMP |
| US5438022A (en) * | 1993-12-14 | 1995-08-01 | At&T Global Information Solutions Company | Method for using low dielectric constant material in integrated circuit fabrication |
| US5759906A (en) * | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
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1999
- 1999-12-30 KR KR1019990067261A patent/KR20010059734A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02249226A (en) * | 1989-03-23 | 1990-10-05 | Matsushita Electric Ind Co Ltd | Resist forming method |
| US5312512A (en) * | 1992-10-23 | 1994-05-17 | Ncr Corporation | Global planarization using SOG and CMP |
| US5438022A (en) * | 1993-12-14 | 1995-08-01 | At&T Global Information Solutions Company | Method for using low dielectric constant material in integrated circuit fabrication |
| US5759906A (en) * | 1997-04-11 | 1998-06-02 | Industrial Technology Research Institute | Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100727439B1 (en) * | 2005-03-22 | 2007-06-13 | 주식회사 하이닉스반도체 | Method for forming interconnection line |
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