KR20010058831A - Fabricating method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a gate oxide layer from being contaminated and damaged, by separately forming the gate oxide layer in a logic region and a dynamic random access memory(DRAM) region, and by consecutively stacking a polysilicon layer on the respective gate oxide layers. CONSTITUTION: An isolation region(12) is formed on a semiconductor substrate(11) where A logic region and a dynamic random access memory(DRAM) region are defined. A thin gate oxide layer(13) and the undoped first polysilicon layer are formed. N-type impurity ions are implanted into a portion of the first polysilicon layer in the logic region. The first polysilicon layer and the thin gate oxide layer in the DRAM region are removed. A thick gate oxide layer(15), the second polysilicon layer doped with the n-type impurity ions, a WSix layer(17) and a cap insulation layer(18) are formed. A gate is patterned through a photolithography process. The first polysilicon layer and the thin gate oxide layer in the logic region are etched to pattern a logic region gate. A patterned insulation layer sidewall of a gate is formed in the logic region and the DRAM region. A source/drain(20) is formed in the semiconductor substrate by a selective n-type and p-type impurity ion implantation process while p-type impurity ions are implanted into the undoped first polysilicon layer in the logic region. A silicide layer(21) is selectively formed only on the first polysilicon layer and the source/drain in the logic region where silicon is exposed.

Description

Manufacturing method of semiconductor device {FABRICATING METHOD OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device suitable for simultaneously forming gate electrodes suitable for operating characteristics of each of a logic part and a DRAM part of a memory module. It relates to a manufacturing method of.

In general, a logic process of 0.25 μm or less is formed using a dual polysilicon gate structure on the thin gate oxide layer to improve performance, and a self aligned silicide (SALICIDE) method on the gate electrode and the source / drain. The Ti or Co silicide layer is formed, whereas the highly integrated DRAM process is self-aligned using a gate cap material for high integration of a memory cell on a relatively thick gate oxide layer to increase the operating voltage of the word line and improve the reliability of the DRAM cell. A polysilicon plug is formed through a self aligned contact (SAC) method, and a WSix polycide is formed on the gate electrode.

Therefore, in order to form a memory embedded logic semiconductor device, the logic process and the highly integrated DRAM process need to be easily merged.

Referring to the procedure cross-sectional view of Figs. 1A to 1E attached to the conventional method for manufacturing a semiconductor device as described above in detail as follows.

First, as shown in FIG. 1A, a shallow trench isolation (STI) isolation region 2 is formed on a semiconductor substrate 1 having a logic region and a DRAM region divided therein to define an active region, and a thick gate oxide film is formed on the upper surface. After forming (3), the thick gate oxide film 3 formed on the logic region is etched through the photoresist film PR1 pattern.

As shown in FIG. 1B, the photoresist film PR1 pattern is removed, a thin gate oxide film 4 required in the logic region is formed on the upper surface of the logic region and the DRAM region, and then the undoped polysilicon layer ( 5) Deposition and planarization, through the second mask and ion implantation, the N-type and impurity ions are selectively injected into the region where the NMOS and PMOS transistors of the logic region are to be formed, and the N-type impurity ions are injected into the DRAM region. Inject. In this case, the DRAM region satisfies the required thickness of the gate oxide film by stacking the thick gate oxide film 3 and the thin gate oxide film 4.

1C, a WSix film 6 and a cap insulating film 7 are sequentially formed on the polysilicon layer 5 into which the impurity ions are selectively implanted. At this time, the WSix film 6 is formed to minimize the resistance value of the gate electrode applied to the word line of the DRAM, the cap insulating film 7 is SiO ₂ or to apply a self-aligned contact method for high integration of the DRAM It is formed by applying SiN.

As shown in FIG. 1D, a gate patterning mask (not shown) is formed on the cap insulating film 7 by a photo process to form a cap insulating film 7, a WSix film 6, a polysilicon layer 5, and the like. By sequentially etching the gate oxide films 4 and 3, the gates required on the active regions of the logic region and the DRAM region are patterned.

As shown in FIG. 1E, the sidewalls 8 of the gate are formed on the upper surface of the resultant through an insulating film deposition and selective etching, and then a semiconductor substrate is formed through selective N-type and impurity ion implantation using a mask (not shown). The source / drain 9 is formed in (1), Ti or Co is deposited on the upper surface of the logic area, and then rapid thermal processing (RTP) is performed to expose the silicon area / drain (9). The silicide layer 10 is selectively formed only on the?).

However, the above-described method for manufacturing a semiconductor device has the following problems.

First, in the case of the gate oxide film, the thick gate oxide film of the DRAM region may be contaminated by the photoresist film for etching the logic region, and the damage may be caused by plasma when the photoresist film is removed, and the thin gate oxide film and the thick gate oxide film may be As the stack is formed, a trap may occur at an interface, and a change in thickness may occur due to oxidation and cleaning, thereby making it difficult to control.

In the case of the WSix film, as the height of the gate electrode needs to be lowered to facilitate the process of the DRAM region, the thickness of the lower polysilicon layer is lowered. In this case, the energy of boron injected into the polysilicon layer with the impurity ions in the form When the concentration and the concentration control become difficult, the energy and the concentration become high, boron ions penetrate the gate oxide film and penetrate to the substrate, and boron penetration occurs. When the energy and the concentration become low, the polysilicon layer becomes There is a problem that depletion causes the deterioration of the characteristics of the PMOS transistor, and the WSix film itself affects the gate oxide film, thereby increasing the thickness of the electrical gate oxide film, thereby making it difficult to control the thin gate oxide film. .

In addition, in the case of gate patterning, etching of the thin gate oxide film and the thick gate oxide film is simultaneously performed, thus making it difficult to control the etching. That is, since the etching rate of the DRAM area having a high gate pattern density is relatively low due to the micro loading effect, the transient etching considering the DRAM area causes the active area of the logic area to form a thin gate oxide film of the logic area. May be damaged and polysilicon residues remain in the DRAM area if the over etching is not performed.

The DRAM region gate electrode to which the WSix film is applied has a sheet resistance of 7 to 14. / sq. Surface resistance of logic region gate electrode to which silicide layer is applied / sq. Due to the high degree of accuracy, the performance of the DRAM area is lowered compared to the logic area, which makes it difficult to implement a high-performance memory embedded logic semiconductor device.

On the other hand, if the silicide layer is applied to the DRAM region gate electrode, problems of the doping problem of the polysilicon layer and the increase of the sheet resistance may be solved. In this case, however, the refresh characteristic of the DRAM may be reduced.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to independently form a gate oxide film of a logic region and a DRAM region, and to apply a silicide layer as a gate electrode of a logic region. The present invention provides a method of manufacturing a semiconductor device capable of simultaneously forming a gate electrode suitable for each operation characteristic by applying a WSix film as a gate electrode of a DRAM region.

1A to 1E are cross-sectional views showing a conventional method for manufacturing a semiconductor device.

2A to 2H are cross-sectional views showing an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

11: semiconductor substrate 12: isolation area

13: thin gate oxide film 14, 16: polysilicon layer

15: thick gate oxide film 17: WSix film

18: Cap insulation film 19: Side wall

20: source / drain 21: silicide layer

PR21-PR23: photosensitive film

A method of manufacturing a semiconductor device for achieving the object of the present invention as described above is to form an isolation region on a semiconductor substrate divided logic region and DRAM region and then a thin gate oxide film and an undoped first polysilicon on the upper surface Forming a layer and implanting N-type impurity ions into a portion of the logic region first polysilicon layer; Removing the first polysilicon layer and the thin gate oxide layer in the DRAM region; Forming a thick gate oxide film, a second polysilicon layer doped with N-type impurity ions, a WSix film, and a cap insulating film on an upper surface of the resultant, and then patterning the gate through DRAM region gate photolithography; Patterning the logic region gate by etching the first polysilicon and the thin gate oxide layer of the logic region; Forming an insulating film sidewall of the gate patterned in the logic region and the DRAM region, and then forming a source / drain in the semiconductor substrate through selective N-type and implanted impurity ion implantation and in the undoped first polysilicon layer of the logic region And implanting the impurity ions, and selectively forming a silicide layer only on the logic region-first polysilicon layer and the source / drain in which silicon is exposed.

Referring to the cross-sectional view of Figure 2a to 2h accompanying the method for manufacturing a bipolar transistor according to the present invention as described above in detail as an embodiment as follows.

First, as shown in FIG. 2A, an STI isolation region 12 is formed on a semiconductor substrate 11 having a logic region and a DRAM region defined therein to define an active region, and then doped with a thin gate oxide film 13 on the upper surface. The polysilicon layer 14 is sequentially formed, and a photoresist film PR11 pattern is formed to expose the polysilicon layer 14 forming the gate of the logic region NMOS transistor, and then the N-type impurity ions are implanted. At this time, the polysilicon layer 14 is formed to a thickness of about 2500 Å in the same manner as a single logic process.

As shown in FIG. 2B, the photoresist film PR11 pattern is removed, the photoresist film PR12 pattern is formed to mask the polysilicon layer 14 of the logic region, and then the polysilicon layer 14 of the exposed DRAM region is formed. ) And the thin gate oxide film 13 are etched.

2C, a thick gate oxide film 15, a polysilicon layer 16 into which N-type impurity ions are implanted, a WSix film 17, and a cap insulating film 18 are sequentially formed on the upper surface of the resultant product. do. At this time, the thick gate oxide film 15, the polysilicon layer 16 into which the N-type impurity ions are implanted, the WSix film 17, and the cap insulating film 18 are formed to have the same thickness as a single DRAM process.

As shown in FIG. 2D, a DRAM region gate patterning mask (not shown) is formed on the cap insulation layer 18 to selectively etch the cap insulation layer 18, and then the DRAM region gate patterning mask is removed.

As shown in FIG. 2E, the cap insulation layer 18 is applied as a hard mask to etch the WSix layer 17, the polysilicon layer 16, and the thick gate oxide layer 15 to form a DRAM region. The gate required on the top of the active region is patterned.

As shown in FIG. 2F, a photoresist film PR13 pattern is formed to completely mask the DRAM region and to pattern the gate of the logic region on the polysilicon layer 14 of the logic region.

As shown in FIG. 2G, the polysilicon layer 14 and the thin gate oxide layer 13 are etched by applying the photoresist layer PR13 pattern to pattern the gate required on the active region of the logic region, and then the photoresist layer. (PR13) Remove the pattern.

As shown in FIG. 2H, the sidewalls 19 of the gate patterned in the logic region and the DRAM region are formed through the insulating film deposition and selective etching on the upper surface of the resultant, and then the selective N-type using a mask (not shown); Source / drain 20 is formed in the semiconductor substrate 11 by implanting impurity impurities, and implanted impurity ions into the undoped polysilicon layer 14 of the logic region are formed on the upper surface of the logic region. After the deposition of Ti or Co, a rapid heat treatment is performed to selectively form the silicide layer 21 only on the silicon region-exposed logic region polysilicon layer 14 and the source / drain 20.

The method of manufacturing a semiconductor device according to the present invention as described above has the following effects.

First, the gate oxide films of the logic region and the DRAM region are formed as individual single films, and polysilicon is continuously deposited on the gate oxide films of each region to prevent contamination and damage of the gate oxide film, and to generate an interface trap due to the stacking. It is effective in preventing the formation thickness and improving the reliability of the semiconductor device.

Since the gate polysilicon layer thickness and doping of the logic region can be performed in the same manner as a single logic process, boron permeation and polysilicon layer depletion occurring during gate doping of the logic region PMOS transistor are prevented, There is an effect that can prevent the performance degradation of the PMOS transistor.

As the gate patterning of the logic region and the DRAM region is performed separately, etching conditions suitable for the characteristics of each region can be set, thereby facilitating process progress and improving reliability of the manufactured device.

In addition, the gate electrodes of the logic region and the DRAM region are formed by applying a polyside using a silicide layer and a WSix film according to the characteristics of each region, thereby implementing a memory-embedded logic semiconductor device capable of exhibiting optimal performance in each region. It works.

In addition, by applying a polysilicon gate in a logic region and a polyside gate using a WSix film in a DRAM region, a stacked gate of a planar capacitor and a flash memory, which is required in an analog circuit, is easily provided. Since it can be manufactured, it is possible to manufacture a memory-embedded logic semiconductor device having not only DRAM but also flash memory.

Claims (1)

An isolation region is formed on the semiconductor substrate where the logic region and the DRAM region are separated, and then a thin gate oxide layer and an undoped first polysilicon layer are formed on the upper surface, and the N-type impurity ion is formed on a portion of the logic region first polysilicon layer. Injecting; Removing the first polysilicon layer and the thin gate oxide layer in the DRAM region; Forming a thick gate oxide film, a second polysilicon layer doped with N-type impurity ions, a WSix film, and a cap insulating film on an upper surface of the resultant, and then patterning the gate through DRAM region gate photolithography; Patterning the logic region gate by etching the first polysilicon and the thin gate oxide layer of the logic region; Forming an insulating film sidewall of the gate patterned in the logic region and the DRAM region, and then forming a source / drain in the semiconductor substrate through selective N-type and implanted impurity ion implantation and in the undoped first polysilicon layer of the logic region And forming a silicide layer only on the logic region first polysilicon layer and the source / drain where silicon is exposed.