KR20010057935A - Method of forming bottom electrode of capacitor in high integrated memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a lower electrode of a capacitor in a high integrated semiconductor memory device is provided to prevent a bridge between lower electrodes by removing selectively a doped polysilicon layer. CONSTITUTION: An interlayer dielectric(30) is formed on a semiconductor substrate(10). A contact plug(54) is formed through a contact hole. The first polysilicon layer(58) is deposited on a whole face of a sacrificial insulating layer. A selective meta-stable polysilicon growth process and a doping process are performed. The second polysilicon layer(60) is deposited on the first polysilicon(58). The second and the first polysilicon layers(60,58) are polished. The sacrificial insulating layer is removed selectively. The first polysilicon layer(58) is removed selectively. A lower electrode is formed by performing the doping process for the first polysilicon layer(58).

Description

Method of manufacturing a capacitor bottom electrode of a high density semiconductor memory device {Method of forming bottom electrode of capacitor in high integrated memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor lower electrode of a highly integrated semiconductor memory device capable of preventing a bridge between a cylindrical lower electrode having an uneven structure.

At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. As the integration of semiconductor devices increases, the area of the capacitor is greatly reduced, but the capacitor used as a memory device in a semiconductor memory device, for example, a DRAM, must further increase the charge required for operation, that is, the capacitance secured in a unit area.

Meanwhile, the basic structure of a capacitor used in a memory cell is composed of a lower electrode for a storage node, a dielectric layer, and an upper electrode for a plate node. Capacitors having such a structure have the first thin dielectric film thickness in order to obtain a higher fixed capacitance in a small area, the effective area is increased through the structure of the three-dimensional capacitor, or the third dielectric material using a high dielectric constant material. Several conditions must be met, such as

Capacitors in semiconductor devices generally obtain better dielectric films with less leakage current at a given dielectric film thickness, and larger dielectric breakdown voltages. This method is limited because the leakage current increases due to tunneling, which lowers the reliability. In addition, research is underway to develop and apply a thin film material having high dielectric properties such as Ta ₂ O ₅ in a design rule of 0.16 µm or less so that a fixed capacitance can be sufficiently secured even in a small area of a highly integrated memory device. .

Finally, in order to increase the effective area of the capacitor, a study of increasing the cross-sectional area of the lower electrode in a three-dimensional structure is being conducted.

Among these methods, selective metastable polysilicon (Selective Meta-stable) is a technique for increasing the surface area of a capacitor by increasing the surface area of the lower electrode in order to secure a certain amount of charge preservation capacity required for cell operation. Polysilicon: hereinafter referred to as MPS) growth technology is widely used. This selective MPS technique deposits a low doped or undoped amorphous silicon film at 510-530 ° C., and then uses Si ₂ H ₆ gas to seed the silicon on the surface of the amorphous silicon film, followed by high vacuum. When the annealing process is performed at, the lower electrode having the concave-convex surface of the silicon thin film due to the movement property of the silicon atoms may be formed. After the MPS process, a P ion doping treatment step is further performed to compensate for the lack of conductivity in the silicon film.

However, the manufacturing process of increasing the cross-sectional area of the lower electrode by the selective MPS process to secure the high capacity of the capacitor causes the following problems in the cylindrical capacitor structure of the highly integrated semiconductor memory device. That is, when the space between the cells is gradually reduced due to the shrinking of the semiconductor device, and when the gap between the lower electrodes is narrow, when the uneven silicon grains of the lower electrode are broken, a bridge is generated at the lower electrodes between the cells.

In order to prevent this, if the MPS process is performed only on the inner side of the cylindrical lower electrode, the capacitor capacity is small, so that the cylinder size is increased by this insufficient capacity, thereby increasing the load during the wiring process.

An object of the present invention is to select and remove only the MPS doped polysilicon film by etching selectivity after depositing a polysilicon film having a large undoped or doped concentration difference on the MPS doped polysilicon film during the lower electrode manufacturing process of a capacitor having a cylinder structure. The present invention provides a method for manufacturing a capacitor lower electrode of a highly integrated semiconductor memory device, which can prevent a bridge between lower electrodes due to a process and secure a desired capacity without increasing the size of the lower electrode.

1 to 8 are process flowcharts illustrating a method for manufacturing a capacitor lower electrode of a highly integrated semiconductor memory device according to the present invention.

* Description of symbols on the main parts of the drawings *

10 silicon substrate 20 cell transistor

30, 50: interlayer insulating film 32, 54: contact plug

40: bit line 52: contact hole

56: sacrificial insulating film 58: first polysilicon film

60: second polysilicon film

In order to achieve the above object, the present invention provides a method for manufacturing a lower electrode of a cylindrical capacitor of a highly integrated semiconductor memory device, the lower electrode being bonded to a lower surface of a semiconductor substrate on which a semiconductor element is formed and a dielectric thin film and an upper electrode thereon, Forming an interlayer insulating film for interlayer insulation of the device on the semiconductor substrate including the semiconductor device, and forming a contact plug vertically connected to the junction surface of the lower substrate through the contact hole of the interlayer insulating film; After forming the insulating film, forming a contact hole in the film to open the contact plug surface, depositing the first polysilicon on the entire surface of the sacrificial insulating film, and performing a selective metastable silicon growth process and doping treatment, There is a doping concentration difference with the first polysilicon film on the first polysilicon film having the uneven surface Depositing a second polysilicon film, polishing the stacked second and first polysilicon films until the sacrificial insulating film is exposed, selectively removing only the sacrificial insulating film, and selectively removing the first polysilicon film And forming a lower electrode by doping the second polysilicon film.

According to the present invention, during the manufacturing process of the lower electrode of the cylindrical capacitor, the second polysilicon film having a large undoped or doping concentration difference is deposited on the first polysilicon film to which the MPS process is applied, and only the first polysilicon film is selectively removed, thereby the uneven structure By forming the lower electrode of the integrated semiconductor device, it is possible to prevent the silicon bridge due to the MPS process between the lower electrodes of the highly integrated semiconductor device, and the size of the lower electrode because the upper polysilicon film obtains the uneven shape by the removed polysilicon film (MPS process applied). The desired capacity can be obtained without increasing the

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 8 are flowcharts illustrating a method of manufacturing a capacitor lower electrode of a highly integrated semiconductor memory device according to the present invention.

A capacitor manufacturing process of a DRAM having a cylindrical lower electrode according to an embodiment of the present invention is as follows.

First, as shown in FIG. 1, a field oxide film (not shown) is formed on a silicon substrate 10 as a semiconductor substrate to define an active region and an inactive region of a device, and a series of device processes are formed on the upper surface of the substrate. A cell transistor 20 having a gate oxide film 22, a gate electrode 24, a hard mask insulating film 26, a spacer 28, and a source / drain region (not shown) is formed.

Then, the interlayer insulating film 30 is formed by depositing a material selected from USG (Undoped Silicate Glass), BPSG (Boro Phospho Silicate Glass) and SiON on the entire surface of the substrate 10 and performing a chemical mechanical polishing process. do. Next, a contact hole is formed in the interlayer insulating film 30, and the doped polysilicon is embedded and polished to form a contact plug 32 in contact with any one of the source / drain regions, and a wiring process is performed thereon. As a result, a bit line 40 connected to the contact plug 32 is formed. Subsequently, an interlayer insulating film 50 is further formed on the resultant, and a contact hole 52 is formed in this film.

Next, as shown in FIG. 2, the upper contact plug 54 is buried / polished in the interlayer insulating film 50 to contact the contact plug 32 corresponding to another region of the source / drain region. To form. A sacrificial insulating film 56 is formed on the resultant to form a lower electrode of a cylinder structure. Herein, the sacrificial insulating layer 56 may be formed of any one of USG, PSG, BPSG, PE-TEOS, and LP-TEOS.

Subsequently, as shown in FIG. 3, a contact hole is formed in the sacrificial insulating film 56 to open the surface of the contact plug 54. The lower electrode manufacturing process according to the present invention is performed on the sacrificial insulating film 56.

Thus, the first polysilicon film 58 is deposited to a thickness of 100 to 500 kHz on the entire substrate on which the sacrificial insulating film 56 is formed. Here, the first polysilicon film 58 uses P (Phosphorus) to make the doping concentration 0 to 1E20 atoms / cc.

Next, as shown in FIG. 4, the first polysilicon film 58 is subjected to a selective meta-stable silicon growth process, so that the grains 58 ′ of the uneven structure are formed on the surface of the silicon film. Is grown and PH ₃ doped in-situ to supply the insufficient P in the film 58 '. In the doping process, the doping concentration of the uneven first polysilicon film 58 'is preferably 2E20 to 9E20 atoms / cc.

Next, as shown in FIG. 5, the second polysilicon film 60 having a doping concentration difference between the first polysilicon film 58 'and the top of the first polysilicon film 58' having the uneven surface is 100. The deposition is carried out at about 500 kPa. Here, the doping concentration of the second polysilicon film 60 is 0 to 1E20 atoms / cc.

As shown in FIG. 6, when the surface of the sacrificial insulating layer 56 is exposed to the second and first polysilicon layers 60 and 58 ′ that are stacked by performing an entire surface etching process and a chemical mechanical polishing (CMP) process. Polish until

As shown in FIG. 7, only the sacrificial insulating layer 56 is removed from the resultant. The etching process may be performed using a dip-out process using HF or BOE, but the sacrificial insulating layer 56 may be left at a predetermined thickness so that the contact plug 54 may not be exposed.

Subsequently, the etch selectivity of the second polysilicon film 60 and the first polysilicon film 58 'is adjusted to selectively remove the first polysilicon film 58'. For example, when the wet etching process is used, the first polysilicon film 58 ′ is selectively etched by adjusting the composition ratio of the mixed chemical of NH ₄ OH and H ₂ O. Here, reference numeral 58 '' denotes a polysilicon film remaining between the second polysilicon film 60 and the contact plug 54 due to the etching process.

In addition, a doping process is performed to supply the insufficient P to the second polysilicon film 60 to complete the cylindrical lower electrode manufacturing process according to the present invention. Here, the concentration of the second polysilicon film 60 is 2E20 to 9E20 atoms / cc by the doping process.

Therefore, the present invention can prevent the silicon grains from breaking between the cylindrical lower electrodes of the uneven structure, thereby preventing the bridge phenomenon between the capacitor lower electrodes of the highly integrated semiconductor device.

Subsequently, as shown in FIG. 8, after completing the manufacturing process on the lower electrode of the cylindrical shape of the present invention, the conventional dielectric thin film 62 and the upper electrode 64 are formed.

Meanwhile, a film to be used for etch stop may be further formed on the sacrificial insulating film 56 in the capacitor manufacturing process of the semiconductor device as described above when the first polysilicon film 58 ′ is subsequently removed. Here, the etch stop film is, for example, a nitride film or an Al ₂ O ₃ film.

When the capacitor lower electrode manufacturing method according to the present invention is used in the manufacturing process of the highly integrated semiconductor memory device, it is possible to prevent the silicon bridge phenomenon between the lower electrode caused by the MPS process to increase the cross-sectional area of the lower electrode.

In addition, since the polysilicon film on the upper side of the polysilicon film to which the MPS process is applied also has a concave-convex shape, even if the polysilicon film to which the MPS process is subsequently removed is selectively removed, the desired capacitance can be secured without increasing the size of the lower electrode. have.

Claims (5)

A method of manufacturing a lower electrode of a cylindrical capacitor of a highly integrated semiconductor memory device, comprising a lower electrode bonded to a lower surface of a semiconductor substrate on which a semiconductor element is formed, and a dielectric thin film and an upper electrode thereon, Forming an interlayer insulating film for interlayer insulation of the device on the semiconductor substrate having a semiconductor device, and forming a contact plug vertically connected to a bonding surface of the lower substrate through a contact hole of the interlayer insulating film; Forming a sacrificial insulating film over the entire surface of the substrate and forming a contact hole in the film to open the contact plug surface; Depositing a first polysilicon over the sacrificial insulating film, and performing a selective metastable silicon growth process and a doping process; Depositing a second polysilicon film having a doping concentration difference with the first polysilicon film on the first polysilicon film having an uneven surface by the process; Polishing the stacked second and first polysilicon films until the sacrificial insulating film is exposed; Selectively removing only the sacrificial insulating film; Selectively removing the first polysilicon film; And And forming a lower electrode by doping the second polysilicon layer. The method of claim 1, wherein an etching stop layer is further formed on the sacrificial insulating layer to remove the first polysilicon layer. The method of claim 1, wherein the thickness of the first polysilicon film is 100 to 500 kPa, and the dopant concentration of the first polysilicon film is 2E20 to 9E20 atoms / cc. The method of claim 1, wherein the thickness of the second polysilicon film is 100 to 500 kPa, and the dopant concentration of the second polysilicon film is 0 to 1E20 atoms / cc. 2. The method of claim 1, wherein the doping concentration is 2E20 to 9E20 atoms / cc during the doping treatment of the second polysilicon film after the first polysilicon film is selectively removed.