KR20010057477A - Planarization method of semiconductor device - Google Patents

Planarization method of semiconductor device Download PDF

Info

Publication number
KR20010057477A
KR20010057477A KR1019990060919A KR19990060919A KR20010057477A KR 20010057477 A KR20010057477 A KR 20010057477A KR 1019990060919 A KR1019990060919 A KR 1019990060919A KR 19990060919 A KR19990060919 A KR 19990060919A KR 20010057477 A KR20010057477 A KR 20010057477A
Authority
KR
South Korea
Prior art keywords
layer
polishing
slurry
semiconductor device
chemical mechanical
Prior art date
Application number
KR1019990060919A
Other languages
Korean (ko)
Other versions
KR100532982B1 (en
Inventor
이성하
이지혜
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR10-1999-0060919A priority Critical patent/KR100532982B1/en
Publication of KR20010057477A publication Critical patent/KR20010057477A/en
Application granted granted Critical
Publication of KR100532982B1 publication Critical patent/KR100532982B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/0056—Control means for lapping machines or devices taking regard of the pH-value of lapping agents
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/005—Control means for lapping machines or devices
    • B24B37/013—Devices or means for detecting lapping completion

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

PURPOSE: A planarization method of a semiconductor device is provided to permit an easy end-point detection of chemical mechanical polishing. CONSTITUTION: In the method, after the first layer(2) is formed on a semiconductor wafer(1) and patterned, the second layer(3) of silicon is formed on the entire surface. Thus a surface of the second layer(3) becomes rough due to the patterned first layer(2). The second layer(3) is then planarized through the chemical mechanical polishing, producing slurry comprised of water, potassium hydroxide(KOH), and colloidal SiO2. Slurry is titrated with HNO3 and further the acidity of slurry is measured. When the acidity of slurry is suddenly reduced, the polishing is stopped.

Description

반도체소자의 평탄화방법{PLANARIZATION METHOD OF SEMICONDUCTOR DEVICE}Planarization Method of Semiconductor Device {PLANARIZATION METHOD OF SEMICONDUCTOR DEVICE}

본 발명은 반도체소자의 평탄화방법에 관한 것으로, 특히 화학기계적 연마(chemical mechanical polishing : CMP)의 종료점(end point) 검출을 용이하게 할 수 있도록 한 반도체소자의 평탄화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly, to a planarization method of a semiconductor device for facilitating detection of an end point of chemical mechanical polishing (CMP).

최근들어 반도체소자의 평탄화방법으로 다양한 장점을 갖는 화학기계적 연마가 많이 사용되고 있다.Recently, as a planarization method of a semiconductor device, chemical mechanical polishing having various advantages has been widely used.

이와같은 화학기계적 연마는 임의의 층을 연마할 때, 하부의 다른 층이 노출되는 시점에서 종료점을 검출할 수 있어야만 하부의 다른 층이 손실되는 것을 방지할 수 있게 되어 후속공정의 안정성을 확보할 수 있게 되므로, 연마 종료점 검출이 매우 중요하지만, 현재는 연마 종료점 검출에 많은 기술적인 어려움을 갖고 있다.Such chemical mechanical polishing can ensure that the end point is detected at the time when the lower layer is exposed when polishing an arbitrary layer, so that the lower layer can be prevented from being lost, thereby securing the stability of the subsequent process. Since the polishing endpoint detection is very important, there are many technical difficulties in the polishing endpoint detection at present.

상기 화학기계적 연마의 일반적인 종료점 검출방법으로는 광(optic) 방식과 전류(current) 방식이 있는데, 먼저 광 방식은 평탄화가 진행되는 웨이퍼 표면에 광을 조사하여 일부의 층을 통과하고, 하부의 다른 층을 통해 반사되는 광의 세기를 측정하여 두께를 측정하는 방식이고, 전류 방식은 연마대상층의 연마가 진행되어 하부의 다른 층이 노출될 경우에 연마속도가 변화하므로, 이때 패드에 연결된 모터에 걸리는 부하의 변화를 전류 차이로 측정하는 방식이다.Common end point detection methods for the chemical mechanical polishing include an optical method and a current method. First, the optical method irradiates light onto a wafer surface where planarization is performed, passes through a layer, and the other part of the lower part. The thickness is measured by measuring the intensity of the light reflected through the layer, and the current method changes the polishing speed when the polishing target layer is polished and other layers are exposed. Therefore, the load applied to the motor connected to the pad is applied. This is a method of measuring the change in current difference.

그러나, 상기한 바와같은 종래의 평탄화 방법으로 광 방식의 화학기계적 연마방법은 웨이퍼의 표면상태에 따라 입사된 광의 산란이 일어날 경우에 두께 측정의 오차가 발생하고, 전류 방식의 화학기계적 연마 방법은 연마대상층과 다른 층의 선택비가 높지 않을 경우에 연마속도 변화가 미세하여 전류 차이 측정이 불가능한 문제로 인해 공정의 신뢰성이 저하되는 문제점이 있었다.However, in the conventional planarization method as described above, in the optical type chemical mechanical polishing method, an error in thickness measurement occurs when scattering of incident light occurs depending on the surface state of the wafer, and the chemical mechanical polishing method in the current method is polishing. When the selection ratio between the target layer and the other layer is not high, there is a problem that the reliability of the process is deteriorated due to the problem that the current difference cannot be measured due to the change of the polishing rate being minute.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 화학기계적 연마의 종료점 검출을 용이하게 할 수 있는 반도체소자의 평탄화방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a planarization method of a semiconductor device that can facilitate the detection of the end point of chemical mechanical polishing.

도1a 내지 도1c는 본 발명의 일 실시예를 보인 수순단면도.1A to 1C are cross-sectional views showing an embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

1:반도체 웨이퍼 2:제1막1: Semiconductor Wafer 2: First Film

3:실리콘막3: silicon film

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 평탄화방법은 패턴의 형태를 갖는 막과 단차를 갖는 실리콘막이 적층된 반도체 웨이퍼를 화학기계적 연마를 통해 평탄화하는 반도체소자의 평탄화방법에 있어서, 실리콘막의 연마에서 발생되는 슬러리(slurry)의 일부를 질산으로 실시간 적정(titration)하여 슬러리의 산도가 급격히 감소할 때, 연마를 종료하는 것을 특징으로 한다.In the planarization method of a semiconductor device for achieving the object of the present invention as described above, in the planarization method of a semiconductor device for planarizing a semiconductor wafer on which a film having a pattern form and a silicon film having a step is laminated through chemical mechanical polishing, Polishing is terminated when a portion of the slurry generated during polishing of the silicon film is titrated with nitric acid in real time to rapidly decrease the acidity of the slurry.

상기한 바와같은 본 발명에 의한 반도체소자의 평탄화방법을 첨부한 도1a 및 도1c의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 1a and Figure 1c attached to the planarization method of the semiconductor device according to the present invention as described above in detail as an embodiment as follows.

먼저, 도1a에 도시한 바와같이 반도체 웨이퍼(1) 상에 제1막(2)을 형성하고, 패터닝한 다음 상부전면에 실리콘막(3)을 형성한다. 이때, 실리콘막(3)은 제1막(2)의 패터닝으로 인해 단차를 갖게 된다.First, as shown in FIG. 1A, the first film 2 is formed on the semiconductor wafer 1, patterned, and then the silicon film 3 is formed on the upper front surface. At this time, the silicon film 3 has a step due to the patterning of the first film 2.

그리고, 도1b에 도시한 바와같이 상기 실리콘막(3)을 화학기계적 연마를 통해 평탄화한다. 이때, 실리콘막(3)의 화학기계적 연마로 인해 증류수, KOH 및 콜로이드상태의 SiO2혼합물로 구성되는 슬러리가 발생하며, 질산(HNO3)을 통해 아래의 화학식1과 같이 반응시켜 실시간 적정함으로써, 슬러리의 산도(pH)를 측정하면 산도의 변화가 없음을 알 수 있다.As shown in Fig. 1B, the silicon film 3 is planarized by chemical mechanical polishing. At this time, due to the chemical mechanical polishing of the silicon film 3, a slurry composed of a mixture of distilled water, KOH, and colloidal SiO 2 is generated, and reacted in real time with nitric acid (HNO 3 ) as shown in Formula 1 below, By measuring the acidity (pH) of the slurry, it can be seen that there is no change in acidity.

SiO2+ 2HNO2 SiO 2 + 2HNO 2

그리고, 도1c에 도시한 바와같이 상기 패터닝된 제1막(2)이 노출되면, 실리콘막(3)의 연마를 종료한다. 이때, 제1막(2)이 노출되어 연마되면, 상기 화학식1의 반응에서 실리콘의 양이 급격히 감소하게 되고, 이에 따라 소모되는 질산의 양도 줄어들어 슬러리의 산도가 급격히 감소되므로, 이를 이용해 연마 종료점을 검출할 수 있게 된다.As shown in Fig. 1C, when the patterned first film 2 is exposed, polishing of the silicon film 3 is terminated. At this time, when the first film 2 is exposed and polished, the amount of silicon is drastically reduced in the reaction of Chemical Formula 1, and thus the amount of nitric acid consumed is also reduced, so that the acidity of the slurry is drastically reduced. It can be detected.

상기한 바와같은 본 발명에 의한 반도체소자의 평탄화방법은 화학기계적 연마에서 발생하는 슬러리의 산도변화를 실시간으로 측정하여 정확하게 연마 종료점을 검출할 수 있으므로, 연마대상막의 두께 편차를 획기적으로 줄일 수 있으며, 공정의 안정성을 확보할 수 있는 효과가 있다.The planarization method of the semiconductor device according to the present invention as described above can accurately detect the polishing end point by measuring the acidity change of the slurry generated in the chemical mechanical polishing in real time, thereby significantly reducing the thickness variation of the polishing target film, There is an effect to ensure the stability of the process.

Claims (1)

패턴의 형태를 갖는 막과 단차를 갖는 실리콘막이 적층된 반도체 웨이퍼를 화학기계적 연마를 통해 평탄화하는 반도체소자의 평탄화방법에 있어서, 실리콘막의 연마에서 발생되는 슬러리(slurry)의 일부를 질산으로 실시간 적정(titration)하여 슬러리의 산도가 급격히 감소할 때, 연마를 종료하는 것을 특징으로 하는 반도체소자의 평탄화방법.In a planarization method of a semiconductor device in which a semiconductor wafer having a patterned film and a silicon film having a step difference is planarized by chemical mechanical polishing, a part of the slurry generated during polishing of the silicon film is titrated with nitric acid in real time ( polishing is terminated when the acidity of the slurry decreases rapidly by titration).
KR10-1999-0060919A 1999-12-23 1999-12-23 Planarization method of semiconductor device KR100532982B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-1999-0060919A KR100532982B1 (en) 1999-12-23 1999-12-23 Planarization method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-1999-0060919A KR100532982B1 (en) 1999-12-23 1999-12-23 Planarization method of semiconductor device

Publications (2)

Publication Number Publication Date
KR20010057477A true KR20010057477A (en) 2001-07-04
KR100532982B1 KR100532982B1 (en) 2005-12-02

Family

ID=19628599

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1999-0060919A KR100532982B1 (en) 1999-12-23 1999-12-23 Planarization method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100532982B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7048612B2 (en) 2003-09-08 2006-05-23 Samsung Electronics Co., Ltd. Method of chemical mechanical polishing

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0161887B1 (en) * 1995-12-26 1999-02-18 문정환 Etch end point detecting method with vessel for wet etching apparatus
KR19980016862A (en) * 1996-08-29 1998-06-05 김광호 Interlayer insulating film planarization method to prevent voids
KR100202192B1 (en) * 1996-10-01 1999-06-15 문정환 Planation of semiconductor device
KR19990008774A (en) * 1997-07-03 1999-02-05 윤종용 How to automatically detect the end point of chemical mechanical polishing using pH sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7048612B2 (en) 2003-09-08 2006-05-23 Samsung Electronics Co., Ltd. Method of chemical mechanical polishing

Also Published As

Publication number Publication date
KR100532982B1 (en) 2005-12-02

Similar Documents

Publication Publication Date Title
JP4074434B2 (en) Processing fluid and method for modifying a structured wafer suitable for semiconductor manufacturing
US6287879B1 (en) Endpoint stabilization for polishing process
US6602117B1 (en) Slurry for use with fixed-abrasive polishing pads in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods
US5321304A (en) Detecting the endpoint of chem-mech polishing, and resulting semiconductor device
CA1245517A (en) Chem-mech polishing method for producing coplanar metal/insulator films on a substrate
US5972793A (en) Photolithography alignment mark manufacturing process in tungsten CMP metallization
US5439551A (en) Chemical-mechanical polishing techniques and methods of end point detection in chemical-mechanical polishing processes
US6895360B2 (en) Method to measure oxide thickness by FTIR to improve an in-line CMP endpoint determination
JP3011113B2 (en) Substrate polishing method and polishing apparatus
CN109262445A (en) A kind of online end-point detection method of chemical-mechanical planarization based on spectrum
KR100532982B1 (en) Planarization method of semiconductor device
JP4792200B2 (en) Planarization etching method with in-situ monitoring by interferometry before recess etching
US20040018733A1 (en) Method of planarizing a surface of a semiconductor wafer
JPH06216096A (en) Semiconductor device, manufacture thereof, polishing method, polishing apparatus and recovering method of polished surface of the same apparatus
KR0165353B1 (en) Forming alignment key pattern in semiconductor apparatus
KR20010095894A (en) Method for measuring End Point of Chemical Mechanical Polishing
CN100411110C (en) Slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect and method for planarizing surface of semiconductor device using same
JPH08339982A (en) Semiconductor manufacturing equipment, and manufacture of semiconductor device
JP2000091415A (en) Sti-forming method
KR19990085105A (en) Slurry for metal film CMP and CMP method using the same
US6429130B1 (en) Method and apparatus for end point detection in a chemical mechanical polishing process using two laser beams
JP2002075939A (en) End-point detection method and aqueous dispersion for chemical mechanical polishing used for the same
JP2005175110A (en) Method for manufacturing semiconductor device
CN110690103B (en) Nanoscale thinning method, direct band gap strain SOI and preparation method thereof
TW492905B (en) Method of chemical-mechanical planarization

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20101025

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee