KR20010056790A - Current mirror type high-gain sense amplifier - Google Patents

Abstract

PURPOSE: A sense amplifier is provided to amplify an input signal having a small voltage difference to a large output signal by configuring a comparison unit receiving input signals by using NMOS transistors parallel with each other. CONSTITUTION: The sense amplifier of high sensitive current mirror type includes a current mirror(110), a comparison unit(120) and the fifth NMOS transistor(N31). The current mirror consists of the first and second PMOS transistors whose sources receive a supply voltage. The drain of the second PMOS transistor outputs an output signal. The comparison unit consists of the first through fourth NMOS transistors. The first and second PMOS transistors connects parallel with each other, connect with the drain of the first PMOS transistor, and receive an non-inverted signal and an output signal of the second PMOS transistor. The third and fourth PMOS transistors connects parallel with each other, connect with the drain of the second PMOS transistor, and receive a non-inverted signal and an output signal of the first PMOS transistor. The fifth NMOS transistor connects sources of the first through fourth NMOS transistor with a ground voltage and receives an enable signal to its gate.

Description

High sensitivity current mirror type sense amplifier {CURRENT MIRROR TYPE HIGH-GAIN SENSE AMPLIFIER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, by comparing input signals using N-channel metal oxide semiconductor transistors (NMOS transistors) connected in parallel. To a sense amplifier.

In the semiconductor memory device, when a data signal stored in a memory cell is input or outputted, a sense amplifier (SA) for sensing and amplifying the data signal is an important part.

Such sense amplifiers require high sensitivity to sense and amplify low potential data signals, high speed operation for fast transfer of data signals, low power consumption, and low area that can be configured in small portions on a semiconductor substrate. . In particular, the high sensitivity and high speed operation of the sense amplifier can be said to be an important factor to determine the overall performance of the semiconductor memory device.

The potential difference input to the sense amplifier through the bit line and the bit bar line connected to the memory cell may be represented by Equation 1 below.

In the above description, C _B is bit line capacitance and C _C is cell capacitance. In order to increase the input potential difference, the value of C _B / C _C should be as small as possible and the value of power supply voltage (Vcc) should be as large as possible. do.

However, as the memory capacity increases, the length of the bit line becomes longer, and accordingly, the bit line capacitance C _B increases. As the size of the transistor decreases, the power supply voltage Vcc also gradually decreases, so that the input potential difference ( ) Became smaller.

Therefore, there is a further need for a high-sensitivity amplification circuit capable of sensing and amplifying and outputting the small input potential difference as described above.

A current mirror type sense amplifier mainly used as such an amplifier circuit is shown in FIG. 1. Referring to FIG. 1, the conventional current mirror type sense amplifier 10 includes a current mirror type PMOS transistor (P-channel Metal Oxide Semiconductor Transistors (P1, P2) and a drain connected to a power source (Vcc)). Drain includes NMOS transistors N1 and N2 connected to drains of the PMOS transistors P1 and P2, respectively.

The same amount of current flows through the drains of the PMOS transistors P1 and P2, respectively. The two currents are combined to a source connection portion from the PMOS transistors P1 and P2 through the NMOS transistors N1 and N2. To form a constant current source (I).

At this time, the constant current I flows in proportion to the difference between the gate-source voltage Vgs and the threshold voltage Vtn of the NMOS transistors N1 and N2. That is, it has a value of constant current I = gm x (Vgs-Vtn), where gm is a transconductance representing the change ratio of the output current to the change of the applied voltage.

When the enable signal pse1i is applied in a high state, the NMOS transistor N3 is turned on and the potential difference between the input voltages saib and sai applied to the gates of the NMOS transistors N1 and N2 ( Vd) is amplified to generate an output voltage sa1ob_o. That is, it is proportional to the difference Vd between the input voltages saib and sai, the transconductance gm, and the output resistance rp2 of the output PMOS transistor P2 and the output resistance rn2 of the output NMOS transistor N2. The output voltage saiob_o is shown.

In recent years, as the potential difference of the input signal becomes smaller, a sense amplifier having the above structure cannot generate an output signal of sufficient magnitude.

In addition, an amplifier capable of generating a larger output signal even with a potential difference of the same input signal may correspond to a future direction of development of a memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a sense amplifier capable of amplifying an input signal having a small potential difference into an output signal having a large width by configuring an NMOS transistor connected in parallel with a comparison means receiving an input signal. Its purpose is to.

1 is a conventional sense amplifier circuit diagram,

2 is a sense amplifier circuit diagram according to an embodiment of the present invention;

3 and 4 show simulation results of an output signal with respect to an input signal in a conventional sense amplifier and a sense amplifier of the present invention.

(Name of the code for the main part of the drawing)

10: conventional sense amplifier 100: sense amplifier of the present invention

110: current mirror means 120: comparison means

130: control unit

P1, ..., P12: PMOS transistor N1, ..., N31: NMOS transistor

saib, sai: input signal sa1ob_n: output signal

pse1i: enable signal

In order to achieve the above object, the sense amplifier of the present invention comprises a current mirror means in which the first and second PMOS transistors whose source is connected to the power supply voltage are configured in a current mirror type to generate an output signal, and the NMOS transistors connected in parallel. A control unit connected to the drain terminal of the PMOS transistor, the comparison unit receiving an inverted input signal and a non-inverting input signal, respectively, and a control unit connected between the comparison unit and a ground power source to control an operation of a sense amplifier by an enable signal. It is characterized by including.

The comparing means is connected in parallel between the drain of the first PMOS transistor and the control unit, the first and second NMOS transistors for inputting an inverting input signal and an output signal of the second PMOS transistor, a drain of the second PMOS transistor, The third and fourth NMOS transistors are connected in parallel between the control unit and input the non-inverting input signal and the output signal of the first PMOS transistor.

The control unit is characterized in that the NMOS transistor connected between the comparison means and the ground power source.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, a means for receiving two input signals is configured as NMOS transistors connected in parallel, respectively, and one NMOS transistor is configured to control on / off operation by an output signal of the other NMOS transistor.

2 illustrates a high gain current mirror type sense amplifier according to an embodiment of the present invention. Referring to FIG. 2, the sense amplifier 100 of the present invention is connected to a power supply voltage Vcc and includes current mirror means 110 including first and second PMOS transistors P11 and P12 configured in a current mirror type. And a comparison unit 120 for receiving and comparing inverted and non-inverted input signals saib and sai between the first and second PMOS transistors P11 and P12 and the controller 130, and an enable signal. The control unit 130 controls the operation of the sense amplifier by pse1i.

The current mirror means 110 is similar to the configuration of the PMOS transistors P1 and P2 constituting the conventional sense amplifier 10, the source terminal is connected to the power supply voltage (Vcc), the gates are connected to each other, The connected gate terminal is connected to the drain terminal node1 of the first PMOS transistor P11.

The comparison means 120 has a source terminal and a drain terminal connected to each other to connect the first PMOS transistor P11 and the control unit 120, respectively, and output signals of the inverting input signal saib and the second PMOS transistor P12, respectively. Is connected to the first and second NMOS transistors N21 and N22 and a source terminal and a drain terminal provided with a gate input to connect the second PMOS transistor P12 and the control unit 120, respectively. and third and fourth NMOS transistors N23 and N24 that receive sai and an output signal node1 of the first PMOS transistor P11 as a gate input.

The controller 130 has a drain terminal connected to a source terminal of the first to fourth NMOS transistors N21, N22, N23, and N24, a source terminal connected to a ground power source Vss, and an enable signal pse1i. The fifth NMOS transistor N31 is provided as a gate input signal.

In the sense amplifier 100 having the above structure, the first NMOS transistor N21 and the third NMOS transistor N23 are driven by the inverting input signal saib and the non-inverting input signal sai, respectively. The fourth NMOS transistor N24 is controlled by the output signal node1 of the first NMOS transistor N21, and the second NMOS transistor N22 is controlled by the output signal sa1ob_n of the third NMOS transistor N23. Is controlled, the first node node1 and the output signal sa1ob_n have a higher potential at a higher potential and a lower potential at a lower side so that an input signal (saib, sai) having a small potential difference is output at a large potential difference. Will be generated.

If this is explained in more detail, it is as follows.

First, when the enable signal pse1i is applied in a high state and the fifth NMOS transistor N31 is turned on, the first to fourth NMOS transistors N21, N22, N23, and N24 forming the comparison unit 120 are provided. The source terminal is supplied with ground power by the fifth NMOS transistor N31.

When the non-inverting input signal sai is applied at a higher potential than the inverting input signal saib, the potential difference between the two input signals sai and saib is amplified and appears at the output terminal. The potential of the first node node1 is output. It becomes relatively higher than the voltage sa1ob_n. Therefore, the fourth NMOS transistor N24 having a gate terminal connected to the first node node1 having a high potential is turned on relatively sooner than the second NMOS transistor N22 connected to the output node sa1ob_n. Through the 4 NMOS transistor N24, the ground power source influences the output voltage sa1ob_n to lower the potential.

As the output voltage sa1ob_n falls, the second NMOS transistor N22 connected thereto is weakly turned on to increase the potential of the first node node1, and the potential difference between the two input signals sai and saib is increased. The output gain is further increased.

As described above, the output signal sa1ob_o of the conventional sense amplifier 10 and the sense amplifier 100 of the present invention when the non-inverting input signal sai is applied at a potential higher than the inverting input signal saib. An output signal of sa1ob_n is shown in FIG. 3.

Referring to FIG. 3, when the non-inverting input signal 31 is applied at a potential of 2.0 volts and the inverting input signal 32 is applied at a potential of 1.9 volts, the potential difference of the input signal is 0.1 volt. The output signal 33 of the conventional sense amplifier 10 is output at a potential of about 0.83 volts, and the output signal 34 of the sense amplifier 100 of the present invention is output at a potential of 0.72 volts, whereby the output gain is increased. You can see that.

On the contrary, when the inverting input signal saib is applied at a potential higher than the non-inverting input signal sai, the sense amplifier 100 causes the output voltage sa1ob_n to be generated at a potential higher than the potential of the first node node1. Perform an amplification operation. Accordingly, the second NMOS transistor N22, which is applied with the output voltage sa1ob_n having a relatively high potential, is turned on faster than the fourth NMOS transistor N24, so that the first node node1 is connected to the second NMOS transistor (N2). Through N22), the potential is lowered due to the influence of the ground power supply. As a result, the fourth NMOS transistor N24 connected to the first node node1 is relatively weakly turned on so that the output voltage sa1ob_n is increased to increase the output gain.

4 illustrates output signals sa1ob_o and sa1ob_n of the conventional sense amplifier 10 and the sense amplifier 100 of the present invention when the inverting input signal saib is applied at a potential higher than the non-inverting input signal sai. Respectively.

Referring to FIG. 4, when the inverting input signal 41 is applied at 2.0 volts and the non-inverting input signal 42 is applied at 1.9 volts so as to have the same potential difference (0.1 volt) as in the case of FIG. The output signal 44 of the sense amplifier 10 of the output voltage of 1.5 volts, the output signal 43 of the sense amplifier 100 of the present invention generates an output voltage of 1.8 volts to further increase the output gain by 0.3 volts You can see that it rises.

As a result, when two sense amplifiers are connected in parallel to amplify the inverted input signal (saib) and the non-inverted input signal (sai) having a 0.1 volt potential difference, when using the conventional sense amplifier 10, a high potential The output signal of is output at 1.5 volts and the low potential output signal at 0.83 volts to have an output potential difference of about 0.7 volts.

However, when performing the amplification operation using the sense amplifier 100 of the present invention, the output signal of the high potential becomes 1.8 volts and the output signal of the low potential becomes 0.72 volts, resulting in a 1.1 potential output potential difference. It can be seen that the gain increases by about 50% compared to the sense amplifier 10.

In the case of the current semiconductor device in which the input potential difference between the bit line and the bit bar line is gradually reduced, the high gain amplification effect by the sense amplifier of the present invention may have a greater effect.

As described above in detail, according to the current mirror type sense amplifier of the present invention, an NMOS transistor connected in parallel to an input terminal can amplify an input signal having a low potential difference into an output signal having a large potential difference.

Therefore, there is an advantage that it is possible to prevent the malfunction due to the low potential difference of the input signal due to the increase in the degree of integration, and to ensure the stability in the operation of the semiconductor device.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (1)

Current mirror means wherein the first and second PMOS transistors whose source is connected to a power supply voltage are configured in a current mirror type and generate an output signal at the drain terminal of the second PMOS transistor; First and second NMOS transistors connected in parallel to a drain terminal of the first PMOS transistor, respectively, and an output signal of an inverted input signal and a second PMOS transistor, respectively, and a drain terminal of the second PMOS transistor; A comparison means comprising third and fourth NMOS transistors connected in parallel, each having an inverted input signal and an output signal of the first PMOS transistor as inputs; And a control unit comprising a fifth NMOS transistor connected between a source terminal of the first to fourth NMOS transistors and a ground power supply, and having an enable signal as a gate input.