KR20010056151A - The fabrication of field emission cathode of field emission display device - Google Patents

Abstract

PURPOSE: A making method for an electric field emission cathode in an electric field emission display element is provided to improve an electric character and to low an electric consumption by etching a wet and a dry etching in order. CONSTITUTION: A cathode electrode layer(22), an insulated layer(26) and a gate electrode layer(28) are gradually formed on the upper surface of the lower substrate(20) in an electric field emission display element. The area of an emitter(25) is formed along to the pattern of an electric field emission cathode array by etching the gate electrode layer(28) and the insulating layer(26). The emitter(25) is formed at the area to form the electric field emission display element. The electric field emission display element is positioned at between the cathode electrode layer(22) and anode electrode layer to maintain electrical insulation. When the insulated layer(26) is etched at the lower substrate(20), the area is gradually performed the wet method and the dry method.

Description

Field emission cathode manufacturing method of field emission display device {The fabrication of field emission cathode of field emission display device}

BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a field emission display device, which is a type of flat panel display. The purpose of the present invention is to optimize the shape of the gate insulating film by appropriately combining dry etching and wet etching in forming the gate insulating film, which serves to maintain insulation between the cathode electrode layer and the gate electrode layer in order to improve characteristics.

1 is a schematic diagram of a general field emission display device. The basic operation principle of a general field emission display device will be described with reference to FIG. 1.

The display device shown in FIG. 1 is a full color display device. For example, R (12R), G (12G), and B (12B) phosphors formed in a stripe shape are formed on an upper substrate. It is formed on the inner surface of (10), and the ITO anode electrode layer 11, which is a kind of transparent electrode, is formed between the upper substrate 10 and the R, G, and B phosphors to apply an anode voltage.

In the lower substrate 20 where the electron emission portions are formed, an FEC array 24 including a plurality of field emission cathodes FEC is formed. Electrons are emitted from the FEC array 24 and the emitted electrons are captured by the anode electrode 11, so that the phosphors deposited on the captured anode electrode 11 emit light.

Here, when the field emission is briefly described, if the applied voltage of the metal or semiconductor surface is about 10 ⁹ [V / m], the electrons will pass through the potential barrier by the tunneling effect and the electrons will be radiated in vacuum even at room temperature. This is called field emission, and the cathode that emits electrons in this way is called a field emission cathode or a field emission device.

In recent years, it has become possible to manufacture surface-radiated field emission cathodes consisting of micron-sized field emission cathodes using semiconductor micromachining technology, and FEC arrays in which a plurality of field emission cathodes are formed on a substrate have their respective emitters. By irradiating electrons emitted from the fluorescent surface, it can be used as an electron supply means constituting a flat display device or various electronic devices.

As an example of such a field emission cathode, a field emission cathode (hereinafter referred to as FEC) called a Spindt type is known.

As shown in FIG. 2, each FEC array 24 is formed on the lower substrate 20 so as to correspond to R, G, and B phosphors for full color display, respectively, and is formed orthogonal to each other. And the gate electrode layer 28 are driven in a matrix. In this case, an insulator layer 26 is formed in the middle to insulate the cathode electrode layer 22 and the gate electrode layer 28. In more detail, a stripe cathode electrode layer 22 is formed on the lower substrate 20, and an emitter tip from which electrons are emitted is formed by patterning to form an FEC array 24 to emit electrons. Done. An insulator layer 26 patterned over the entire surface of the lower substrate 20 is formed on the cathode electrode layer 22, and a gate electrode layer 28 is formed thereon by patterning. That is, the cathode electrode layer 22 and the gate electrode layer 28 are formed in a cross-shaped matrix form. Electrons emitted from the FEC array 24 fly toward the spaced-oriented top substrate 10 at a predetermined interval by a spacer 29 formed in a suitable manner.

In order to enable such an operation, a space formed between the upper substrate 10 and the lower substrate 20 is in a vacuum atmosphere. In order to maintain the vacuum atmosphere, the peripheral edge between the upper substrate 10 and the lower substrate 20 is sealed by a sealant 21. In general, a voltage of about several tens of V-several Kv is applied between the anode electrode layer 11 and the cathode electrode layer 22 to accelerate the electrons.

2, the structure and operation principle of the FEC array 24 will be described in detail. 2 shows a schematic cross-sectional view of a typical conventional field emission display device cut in a vertical direction at a predetermined position. As shown in FIG. 2, a cathode electrode layer 22 is formed on the lower substrate 20, and a plurality of emitters 25 are formed on the lower substrate 20 to form a cone and emit electrons by generation of an electric field. In addition, an integral insulator layer 26 is formed between the emitters 25 so as to enclose each of these emitters in an enclosed form, and a portion of the insulator layer 26 facing the cathode electrode layer 22 is common. The in-gate electrode layer 28 is formed.

In addition, the upper substrate 10 and the lower substrate 20 are spaced by the spacer 29 so that the phosphor layer 12 and the emitter 25 face the space 30, for example, 100 μm to 3 Mm is attached spaced apart. The spacer 29 is formed in plural so that the upper substrate 10 and the lower substrate 20 face each other to form a space 30. In addition, the spacer 29 is made of a material having a high hardness and good insulation such as a ceramic including glass, an oxide or a nitride, or an insulating material such as a polymer including polyamide. Here, the spacers 29 not only attach the edges of the upper substrate 10 and the lower substrate 20 to each other, but in the case where the field emission display elements are large, that is, large screens, hundreds to thousands are formed in the center part, and high vacuum The upper substrate 10 and the lower substrate 20 are prevented from contacting each other due to the pressure difference between the space 30 in the state and the outside of the atmospheric pressure state.

An anode electrode layer 11 for accelerating electrons is formed on the inner surface of the upper substrate 10, and R, G, and B phosphors 12 are formed in one pixel. A black matrix 23 is formed between each phosphor to increase color purity and contrast.

As illustrated in FIG. 1, the cathode electrode layer 22 and the gate electrode layer 28 are formed in a matrix form orthogonally crosswise with the insulator layer 26 interposed therebetween, so that each intersection point is an R phosphor 12R or a G phosphor ( 12G) or B-shaped fruit 12B. The area where the cathode electrode layer 22 and the gate electrode layer 28 intersect is approximately In this area, about hundreds to thousands of field emission cathodes are formed in an array.

3 shows a photograph taken by a scanning electron microscope of a general spin type field emission cathode array 24 actually manufactured. A sharp tip in the round hole is the emitter 25, the inside of the hole is an insulator layer 26 surrounding the emitter 25 and the top surface is the gate electrode layer 28. The cathode electrode layer 22 is not shown in this figure.

In order for one subpixel to emit light, a voltage of about 10V to 100V is applied between the gate electrode layer 28 and the cathode electrode layer 22. At the intersection of the cathode electrode layer 22 and the gate electrode layer 28 where this voltage difference occurs, A strong electric field is generated at the tip of the emitter 25 to cause electron emission due to the tunneling effect described above to form the electron beam 27. The electron beam 27 emitted from the emitter 25 is accelerated by a potential of several tens of V to several kV applied to the anode electrode layer 11 and impinges on the phosphor corresponding to the corresponding field emission cathode array 24. The result is a light of the desired color. This energy generated by the collision of energy electrons to the phosphor is called cathode luminescence (cathode luminescence) and the mechanism is the same as the CRT (Cathode Ray Tube) mainly used in monitors and televisions.

The interior of the space 30 formed between the upper substrate 10 and the lower substrate 20 in order for the field emission to occur easily and the electrons emitted from the emitter 25 to reach the phosphor without interference of other molecules or ions. Minimum vacuum Should be less than or equal torr

The intensity of the light emitted from the phosphor is generally adjusted by the voltage difference applied between the cathode electrode layer 22 and the gate electrode layer 28, or the gray scale display can be performed by modulating the width of the applied voltage pulse. Width Modulation). Due to the difference in the structure of each emitter or the shape of the electrode, a change in the current emitted for each pixel may occur, which degrades the characteristics of the display device. In order to solve this problem, a method of forming a resistance layer between the cathode electrode layer 22 and the emitter 25 is also used.

The larger the amount of current emitted from the emitter 25 under the same applied voltage, the higher the brightness of the display element is. In addition, ideally, all electrons emitted from the emitter 25 transfer energy to the phosphor, but in actual cases, some electrons converge on the gate electrode layer 28 to act as a leakage current, thereby increasing power consumption of the display device. Becomes

4 (a) to 4 (f) illustrate a method of making a general field emission cathode. First, the cathode electrode layer 22, the insulator layer 26, and the gate electrode layer 28 are deposited on the lower substrate 20 by a predetermined method. In this case, the cathode electrode layer 22 and the gate electrode layer 28 are mainly deposited by a thickness of about 200 to 300 nm by sputtering, and the insulator layer 26 is about 1 μm thick by chemical vapor deposition (CVD). To be deposited. Thereafter, the gate electrode layer 28 is patterned as shown in FIG. 4B, and the insulator layer 26 is etched as shown in FIG. 4C. The insulator layer 26 mainly has excellent insulation characteristics. Membrane is used to etch it. There are two methods of wet etching and dry etching. Etching the insulator layer 26 creates a cylinder shaped cavity in which the emitter 25 is to be formed.

Subsequently, the sacrificial layer 31 having a thickness of about 200 nm with an aluminum or the like is inclinedly rotated at an angle of about 15 ° with respect to the horizontal direction of the substrate, and the emitter material is vertically deposited. Emitter is formed inside the hole as in the process of depositing the material, and the material used as the emitter is accumulated on the sacrificial layer 31. Thereafter, when the sacrificial layer 31 is removed by a lift-off method, the emitter 25 tip is formed as shown in FIG. 4 (f) to finally form the field emission cathode.

5 and 6 illustrate differences between the dry etching method and the wet etching method described above when forming holes in the insulator layer by etching.

Dry etching is also referred to as reactive ion etching, for example, a process of performing etching using a gas such as argon or CH ₃ . The characteristic of dry etching is that the etching aspect ratio is very large because the etching speed in the vertical direction is much faster than the etching speed in the horizontal direction. Therefore, as shown in FIG. 5, the etching surface is formed almost vertically.

On the other hand, the wet etching is performed using a liquid such as hydrofluoric acid solution, in which case the etching surface is curved as shown in Figure 6 because the etching speed in the vertical direction and the horizontal direction is almost the same. (A) and (b) of FIG. 8 show scanning electron micrographs of the field emission cathode prepared by the wet etching method and the field emission cathode prepared by the dry etching method, respectively.

The field emission display device formed by the dry etching method and the field emission display device formed by the wet etching method have advantages and disadvantages, respectively. In other words, when formed by the dry etching method, the electric field formed at the tip end is relatively high, so that the amount of current caused by the field emission is high and the operating start voltage is low, while the leakage current in which electrons emitted from the emitter converge is increased. In contrast to the case formed by the wet etching method, the leakage current is small but the emission current is small and the operation start voltage is high.

An object of the present invention is to obtain a field emission cathode having a lower operating voltage and a smaller amount of leakage current in manufacturing a spin type field emission display device, having excellent electrical characteristics and low power consumption.

In order to achieve the present invention, the insulator layer is first etched by wet etching, and then etched by dry etching so as to take advantage of both wet etching and dry etching.

1 is a perspective view of a conventional field emission display device.

2 is a cross-sectional view of a conventional field emission display device.

3 is a scanning electron micrograph of a typical field emission cathode array.

4 is a schematic view of a method of manufacturing a general field emission cathode.

Figure 5 is a cross-sectional view showing the shape of the field emission cathode by the insulator layer dry etching method.

Figure 6 is a cross-sectional view showing the shape of the field emission cathode by the insulator layer wet etching method.

7 is a cross-sectional view showing the shape of the field emission cathode according to the present invention.

8 is a scanning electron micrograph of a field emission cathode prepared by etching of various methods.

9 is a view showing a change in dielectric breakdown characteristics of the insulating film according to the etching method.

10 is a change in leakage current characteristics according to the etching method.

11 is a change in voltage-current characteristics according to the etching method.

12 is a comparative characteristic F-N Plot according to the etching method.

<Description of the code | symbol about the principal part of drawing>

10 upper substrate 11 anode electrode layer 12 fluorescent layer (R, G, B)

20: lower substrate 21: sealant 22: cathode electrode layer

23: Black matrix 24: Field emission cathode array (FEA)

25 emitter 26 insulator layer 27 electron beam

28: gate electrode layer 29: spacer 30: space (Gap)

Figure 7 shows the shape of the field emission cathode according to the present invention. In the present invention, when the gate electrode layer 28 is patterned and the insulator layer 26 is etched, the insulator layer is initially etched using a wet etching method, and after some time, the etch is performed using a dry etching method. The wall surface is characterized by forming a complex shape in which the shape by wet etching and the shape by dry etching are combined.

Here, the wet etching is performed to the upper 1/3 depth of the etching depth of the insulation layer 26, and the remaining 2/3 depth of the lower portion performs dry etching.

Figure 8 (c) shows a scanning electron micrograph of the field emission cathode prepared by the method according to the present invention.

9 shows dielectric breakdown characteristics of an insulating film in two conventional etching methods and the field emission cathode array manufactured by the etching method according to the present invention. As the etching of the gate electrode layer and the insulator layer proceeds, the dielectric breakdown electric field is lowered and the degradation of the insulating property in the case of dry etching is most significant. In the case of the present invention, the dielectric breakdown strength was about 3.3 MV / cm.

10 shows a difference in current density according to an etching method. It can be seen that the wet current has the lowest current density and the dry etching is higher than the method according to the present invention, but non-uniform electron emission occurs.

11 shows a difference in voltage-current characteristics according to an etching method. In the case of the dry etching and the present invention, the operation start voltage is similar to about 47V, and the wet etching is about 56V to about 10V, which is high.

That is, when the same 100V is applied to the gate voltage, it can be seen that according to the present invention, the amount of anode current is almost similar to that of dry etching and about twice as high as that of wet etching. However, in the case of dry etching, the current leaking through the gate electrode is about three times higher than the method according to the present invention, and thus, power consumption increases when the display device is operated as a display device.

12 illustrates a Fowler Nordheim (FN) Plot according to an etching method. In addition, the field emission characteristics of the method and the dry etching method according to the present invention can be seen that the properties are relatively inferior in the case of wet etching.

As described above, when the field emission cathode array is manufactured according to the present invention, the field emission cathode array has excellent characteristics in terms of operating voltage, emission current, leakage current, insulation breakdown, and the like, and when applied to the field emission display device, image quality is improved. An excellent display element with low power consumption can be obtained.

Claims (2)

A cathode electrode layer, an insulator layer, and a gate electrode layer are sequentially formed on the upper surface of the lower substrate for the field emission display device, and the gate electrode layer and the insulator layer are etched according to the pattern of the field emission cathode array to form a space where an emitter is formed. In the method of forming an emitter in the etched region to form a field emission cathode array of the field emission display device, When forming the field emission cathode array, wet etching is performed between the cathode electrode layer and the anode electrode layer to etch the insulator layer to maintain electrical insulation and to form a space in which an emitter from which electrons are emitted is formed. A method of manufacturing a field emission cathode of a field emission display device, comprising the steps of a method followed by a dry etching method. The method of claim 1, Wet etching is performed to an upper 1/3 depth of the etching depth of the insulation layer, The remaining two-thirds of the depth of the lower portion is a method for manufacturing a field emission cathode of the field emission display device characterized in that the dry etching.