KR20010055491A - The fabrication method of smart power IC technology concluding trench gate MOS power device - Google Patents

Abstract

PURPOSE: A method for fabricating a smart power IC having a trench gate MOS power device is provided to permit a high power driving and to improve device performance and reliability. CONSTITUTION: In the method, an analog bipolar device, a digital CMOS device, a lateral double diffused MOS device(LD-MOS), a lateral insulated gate bipolar transistor(LIGBT), the trench gate double diffused MOS device(TDMOS), and a zener diode are formed altogether in a single chip. First an n+ buried layer(2) is formed in a p-type silicon substrate(1), and then a p+ buried layer(3) and a lower p+ isolation are formed. Next, after growth of an n- epitaxial layer(4), an n+ sink junction(5), an upper p+ isolation(6), an n-well(7), a p-well and a p- collector(8) and a p- drift region(9) are formed. Next, the sink junction(5), the isolations, and the wells(7,8) are diffused, and then a base(10,11) is formed. Next, a p- body region(12) for channel, a trench, a gate oxide layer(13), and a polysilicon gate(14) are formed in sequence for the TDMOS. Next, an active area is defined and a field oxide is selectively grown. Next, the second polysilicon gate(16), an emitter(18,19), and an n+ cathode(19) are formed, and then a source and drain(20,21), an extrinsic base(20,21), and a metal electrode(23) are formed.

Description

The fabrication method of smart power IC technology concluding trench gate MOS power device

The present invention relates to a manufacturing method of a smart power integrated circuit (Smart Power IC), and in particular, power IC and high frequency high voltage resistance of secondary battery protection and control IC, Automotive Power IC, DC / DC Converter, etc. A method of manufacturing a bipolar-CMOS-DMOS (BCD) device for a smart power integrated circuit for implementing an information communication system.

1 is a cross-sectional view of a smart power integrated circuit according to the prior art, wherein the smart power integrated circuit is a CMOS device, an analog bipolar device, and a power device mainly applied in a digital circuit using silicon epi technology and junction isolation technology. Double diffused MOS) is a BCD device structure integrated. However, the structure shown in FIG. 1 is disadvantageous in terms of integration for large currents.

FIG. 2 is a cross-sectional view of another smart power integrated circuit according to the prior art, in which the smart power integrated circuit is an integrated structure of a CMOS device and a high current trench gate vertical double diffused MOSFET (VDMOS). Looking at this in more detail, the drain electrode is formed on the n + substrate, and the deep p-well is formed to electrically insulate the substrate from the CMOS device, but it is difficult to integrate the bipolar device, which is an analog device, There is a problem that the characteristics and the degree of integration is low.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and by incorporating a trench gate DMOS device with an upper layer structure into BCD technology and integrating a zener diode necessary for analog circuit design, a large current drive is possible. The goal is to provide a method for manufacturing smart power integrated circuits that improves performance and reliability and significantly increases flexibility in IC design.

1 is a cross-sectional view of a smart power integrated circuit (Bipoar-CMOS-DMOS, aka BCD) according to the prior art,

2 is a cross-sectional view of another smart power integrated circuit according to the prior art,

3 is a cross-sectional view of a smart power integrated circuit according to an embodiment of the present invention;

4A through 4K are cross-sectional views sequentially illustrating a manufacturing process of the smart power integrated circuit illustrated in FIG. 3.

5 is a cross-sectional view of a smart power integrated circuit according to another embodiment of the present invention.

♠ Explanation of symbols for the main parts of the drawing ♠

1: silicon wafer substrate

2: n + burried layer

3: p + burried layer

4: n light doped epitaxal layer

5: n + sink junction

6: p + isolation & sink junction

7: n well junction

8: p well & collector junction

9: p drift junction

10: n base junction

11: p base & buffer junction

12: p turbe junction

13: gate oxide I

14 polysilicon gate I

15: gate oxide II

16: polysilicon gate II

17: side-wall oxide

18: p + emitter junction

19: n + emitter & Cathode junctions

20: source-drain junction of nMOS, TDMOS, LIGBT and NLDMOS, source-drain junction of nMOS, TDMOS, LIGBT & nLDMOS, extrinsic base junction of pnp bipolar Tr.

21: PMOS source-drain junction, npn bipolar Tr., Inactive base junction of npn bipolar Tr.

22: TEOS / BPSG inter dielectric layer

23: Al-Cu metal electrode

According to the present invention for achieving the object as described above, by forming the drain region of the high-current trench gate DMOS device, the collector region of the first bipolar transistor and the second bipolar transistor by performing an ion implantation and diffusion process, A first step of forming an investment layer 2 for the purpose of reducing the leakage current of the first high voltage LDMOS; Forming a lower layer isolation for electrical isolation between the buried layer for reducing the collector series resistance of the first bipolar transistor and the second bipolar transistor, the buried layer of the LIGBT and Zener diodes, and the lower element; After the epitaxial layer 4 is grown, a sink junction 5 serving as a collector of the second bipolar transistor and a drain gate of the trench gate DMOS, an upper isolation 6 for electrical isolation of an upper element, and the first A third step of forming a first well (7) of LDMOS, a second well (8) of CMOS and the first LDMOS drift layer (9); A fourth step of forming a base of the first and second bipolar transistors after performing the diffusion process on the sink junction (5), isolation of the upper and lower layers, and the first and second wells; A fifth step of forming a body serving as a channel of the trench gate DMOS; Forming a trench in the trench gate DMOS; A seventh step of forming a gate oxide film and a polycrystalline silicon electrode of the trench gate DMOS; An eighth step of selectively growing an active region definition and a field oxide film; A ninth step of forming a polycrystalline silicon gate (16) of the CMOS, first and second LDMOS, and LIGBT, an emitter (18) of the first bipolar transistor, and a cathode region (19) of a zener diode; A tenth step of defining source-drain regions (20) of said CMOS, first and second LDMOS, trench gate DMOS and LIGBT devices; And an eleventh step of forming metal wirings of the respective devices.

In the following, with reference to the accompanying drawings, a preferred embodiment according to the present invention will be described in detail.

3 is a cross-sectional view of a smart power integrated circuit according to an embodiment of the present invention. By incorporating a trench gate DMOS device having an upper layer structure into a BCD technology, an integrated circuit application capable of driving a large current is possible, and the performance and reliability of the device are improved. Improved.

In addition, by suggesting a trench gate DMOS structure in the form of an upper layer electrode, the BCD process is simplified, the integration and device performance are improved, and in addition to the trench gate DMOS power device capable of driving high voltage / high current, a zener diode necessary for analog circuit design is integrated. The flexibility in IC design has been greatly increased to secure BCD device technology that can be applied to various applications.

In addition, one-chip analog bipolar and high voltage double double diffused PMOS (LDPMOS) devices, large current latent gate insulated gate bipolar transistor (LIGBT) devices, trench gate DMOS devices, CMOS devices, and Zener diodes Provide technology.

4A to 4K are cross-sectional views sequentially illustrating a manufacturing process of the smart power integrated circuit illustrated in FIG. 3, which will be described in detail step by step as follows.

(1) first step

FIG. 4A shows the ion implantation and diffusion process of the n + buried layer 2 used for the purpose of reducing the drain of the high current trench gate DMOS device, forming the collector region of the npn bipolar transistor, and reducing the leakage current of the high voltage LDMOS.

First, a thin thermal oxide film is grown on the p-type silicon substrate 1, and a nitride film is deposited by a low pressure chemical vapor deposition (LPCVD) method. Next, the n + buried layer 2 is defined by photolithography, and a high concentration of arsenic (Arsine) is ion implanted to diffuse the n + buried layer 2 in an oxidizing atmosphere. At this time, the remaining region except for the n + buried layer is protected by a thin oxide film and a nitride film to prevent the oxide film from growing during the diffusion of the n + buried layer.

(2) second stage

4B is a step of reducing the leakage current of the p + buried layer 3, LIGBT and LDMOS for reducing the collector series resistance of the vertical bipolar pnp transistor and forming the lower layer p + isolation required for electrical isolation between the devices. After selectively etching the silicon nitride film using a p + mask, a high concentration of boron is ion implanted to simultaneously form the p + buried layer 3 and the lower layer p + isolation.

(3) the third stage

FIG. 4C shows an n + sink (5) junction, an upper layer p + isolation, which grows a phosphorous doped n-type epi layer 4 to a level of 10 um and serves as a drain of the collector and trench gate DMOS of the npn bipolar transistor. (6), n-well (7), p-well (8) and p-drift (9) is shown forming steps.

First, the n-type epi layer 4 dopes phosphorus at a relatively low concentration. In the forming of the n + sink junction 5, an oxide film and a nitride film are first applied, a sink area is defined using an n + sink mask, and the nitride film is etched and phosphorus is ion implanted. Subsequently, the p + isolation (6), the p + sink (6) and the anode area (6) of the Zener diode are defined by photo transfer and etching, and after ion implantation of high concentration boron, the collector series resistance of the bipolar transistor And simultaneously diffuse the n + and p + sink / isolation layers by high temperature heat treatment to reduce the on-resistance of the trench gate DMOS. At this time, the oxide film is grown in the portion where the nitride film is etched, and this oxide film prevents the outside diffusion of doped n + and p + impurities. The nitride film is then removed by nitric acid.

Subsequently, n-wells 7 and p-wells 8, which serve as collectors of channels of high voltage LDMOS and CMOS devices, and pnp bipolar transistors, are defined as photographic transfers, and then phosphorus boron is ion implanted, respectively. The p-drift region 9 serving as a drift region of the LD-PMOS device is photo-etched and then ion implanted. At this time, since the concentration and junction depth of the p-drift region of the LD-PMOS device directly affect the on-resistance and breakdown voltage characteristics of the LD-PMOS device, ion implantation and subsequent heat treatment conditions are very important.

In the process step according to an embodiment of the present invention, the p-drift process may be implanted after the well ion implantation and before the heat treatment as described above, or may be formed by photolithography and ion implantation after the well heat treatment. It may be.

(4) the fourth step

4D is a step of forming a base of an n + sink, p + isolation, n-well and p-well diffusion process, bipolar npn and pnp devices.

First, the wells having the junction depth of about 4 μm are formed by heat-treating the n-well and p-well ion-implanted in the third step at a high temperature for 7 to 9 hours, and then, the oxide film is peeled off, and the buffer oxide film growth and Perform nitride film application. As shown in FIG. 4D, during the heat treatment of the n-well and p-well at high temperature, the n + sink and p + isolation also diffuse simultaneously, and the n + sink junction is connected to the lower n + buried layer 2 to collect collectors of the npn bipolar transistor. And effectively reduces the series resistance of the trench gate DMOS.

In addition, the p + isolation 6 is connected to the lower p + isolation 3 and the collector 8 of the pnp transistor is connected to the p buried layer 3. The n-drift 10 of the LDNMOS and the active base region 10 of the pnp bipolar device are then defined by photo transfer and etching, and phosphorus is ion implanted to diffuse to a junction depth of 2 um. Then, the base region 11 of the pnp bipolar element, the p-ground region 11 of the trench gate DMOS, and the p-drift II (11) region of the LIGBT element are defined, and boron is ion-implanted into each region at the same time for the junction depth. Heat to 1μm level.

(5) fifth step

4E is a step of forming a p-body serving as a channel of a trench gate DMOS.

First, after the fourth step process, the nitride film is removed, the p-body region 12 is defined by a photo transfer method, boron is ion implanted, and a p-body junction is formed by heat treatment.

(6) the sixth step

4F is a step of forming a trench of the high current trench gate DMOS of the upper electrode structure.

In order to form a trench gate, first, a Tetra Ethyl Ortho Silicate (TEOS) oxide film is applied, photographic transfer and etching are performed, and then dry etching is performed using the TEOS oxide film as a mask layer.

(7) the seventh step

4G is a step of forming a gate oxide film and a polycrystalline silicon electrode of the trench gate DMOS after the trench gate etching process of the sixth step.

After the trench gate etching process, the gate oxide film 13 of the DMOS is grown by thermal oxidation. Next, polycrystalline silicon is deposited by the LPCVD method, doped the polycrystalline silicon by thermal doping, the gate electrode 14 of the trench gate DMOS is defined by photolithography, and a nitride film having a thickness of about 1600 Å is deposited on the entire surface by the LPCVD method. do. This is a later step, the active area definition and the process for selective growth of the field oxide film.

(8) 8th step

4H is a step of selectively growing an active region definition and a field oxide film.

First, the nitride film is selectively dry-etched using an active region mask, a field oxide film having a thickness of about 6000 Å is grown, the nitride film is removed, the CMOS and LDMOS channel regions are defined, and the boron is ion implanted to form a threshold voltage (Threshold). Voltage) Subsequently, high-quality gate oxide films II (15-1, 15-2) are formed in the CMOS device.

At this time, the gate oxide film first grows 200 microseconds, and only the CMOS region is defined as photo transfer, followed by wet etching to grow 200 microseconds again.

(9) 9th step

4I is a step of forming polycrystalline silicon gate 16 of CMOS, LDMOS and LIGBT, emitter 18 of bipolar transistor, and cathode region 19 of zener diode.

In order to form the polycrystalline silicon gate electrode 16 of CMOS, LDMOS, and LIGBT, polycrystalline silicon is deposited by the LPCVD method, followed by a phosphorous doping process, and a gate electrode is formed by photo transfer and dry etching. Subsequently, a TEOS oxide film is deposited on the entire surface, and a side wall oxide film 17 is formed by dry etching, and then the light doped drain (LDD) region of the CMOS and the power device is defined as a photoresist film, and boron and phosphorus are ions. After injection, heat treatment is performed at 900 ° C. to form an LDD junction.

Subsequently, the region of the emitter 18 of the pnp bipolar transistor and the cathode 19 region of the zener diode are used to facilitate current gain control of the bipolar transistor and to prevent incomplete electrode formation due to impurity redistribution in the LIGBT and Zener diode. At the same time, photo transfer and dry etching are performed, and high concentrations of boron are ion implanted. Subsequently, in order to form the emitter 19 and collector of the npn bipolar transistor, the collector 19 of the LIGBT and the cathode 19 of the zener diode, photographic transfer and dry etching are performed, and after ion implantation of a high concentration of phosphorus, Heat treatment is carried out.

(10) 10th step

4J illustrates defining source-drain regions 20 of CMOS, LDMOS, trench gate DMOS, and LIGBT devices by an n + source-drain photolithography process.

Arsenic (As) is implanted at high concentration into the defined portion, and at the same time, the inactive base region 20 of the pnp bipolar transistor is also formed by ion implanting at high concentration.

The source-drain regions 21 of the CMOS, LDMOS, trench gate DMOS, and LIGBT devices are then defined by a p + source-drain photolithography process. After the high concentration of boron is implanted into the defined portion, at the same time, the inactive base region 21 of the npn bipolar transistor is also implanted with high concentration of boron to perform a heat treatment at 950 ° C.

(11) eleventh step

4K is a step of forming a metal wiring.

After the heat treatment process, the interlayer insulator TEOS / BPSG (Boron Phosphorous Silica Glass) 22 is deposited to a thickness of about 7000 kPa, and contact point photo transfer and dry etching are performed to form a contact window. Subsequently, the Al-Cu metal is deposited by the metal wiring, and the unnecessary portion is removed to form the metal wiring 23.

5 is a cross-sectional view of a smart power integrated circuit according to another embodiment of the present invention, which is a cross-sectional view of a smart power integrated circuit manufactured using a silicon on insulator (SOI) technique and a dielectric isolation technique.

Magnetic thin film inductors are fabricated on thick silicon substrates or SOI substrates with dense trench isolation technology to reduce losses in high frequency operation.

As described in detail above, the present invention provides a method for manufacturing a smart power integrated circuit including a trench gate DMOS power device, and has the following effects.

First, by integrating high-current trench gate power devices, high-voltage power devices, CMOS, and bipolar devices on an epi substrate, chip size of large-current ICs such as battery control, protection ICs, and high-current DC-DC converter ICs can be reduced. Can be.

Second, System On Chips technology can be achieved by one-chip analog bipolar devices, digital CMOS devices, high breakdown voltage LDMOS devices, high current LIGBT devices, trench gate VDMOS devices, and Zener diodes. It can be developed into a technology integrated with the sensor technology.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only and not by way of limitation to the present invention. In addition, it is obvious that any person skilled in the art may make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (12)

An ion implantation and diffusion process is performed to form a drain region of a high current trench gate double diffused MOS device on a silicon substrate, a collector region of a first bipolar transistor and a second bipolar transistor, and a first high voltage lateral double diffused MOS. A first step of forming a buried layer (2) for the purpose of reducing the leakage current of; A second layer forming a lower layer isolation layer for electrical isolation between the buried layer for reducing the collector series resistance of the first bipolar transistor and the second bipolar transistor, the buried layer of LIGBT and Zener diode, and the lower layer device. step; After the epitaxial layer 4 is grown, a sink junction 5 serving as a collector of the second bipolar transistor and a drain gate of the trench gate DMOS, an upper isolation 6 for electrical isolation of an upper element, and the first A third step of forming a first well (7) of LDMOS, a second well (8) of CMOS and the first LDMOS drift layer (9); A fourth step of forming a base of the first and second bipolar transistors after performing the diffusion process on the sink junction (5), isolation of the upper and lower layers, and the first and second wells; A fifth step of forming a body serving as a channel of the trench gate DMOS; Forming a trench in the trench gate DMOS; A seventh step of forming a gate oxide film and a polycrystalline silicon electrode of the trench gate DMOS; An eighth step of selectively growing an active region definition and a field oxide film; A ninth step of forming a polycrystalline silicon gate (16) of the CMOS, first and second LDMOS, and LIGBT, an emitter (18) of the first bipolar transistor, and a cathode region (19) of a zener diode; A tenth step of defining source-drain regions (20) of said CMOS, first and second LDMOS, trench gate DMOS and LIGBT devices; And And an eleventh step of forming metal wirings of the respective devices. The method of claim 1, The first step is, A first sub-step of growing a thin thermal oxide film on the silicon substrate; A second sub step of depositing a nitride film on the thermal oxide film formed in the first sub step by a low pressure chemical vapor deposition (LPCVD) method; And And defining a n + buried layer 2 by photolithography, and then implanting a high concentration of arsenic (Arsine) to diffuse the n + buried layer 2 in an oxidizing atmosphere. Method of manufacturing integrated circuits. The method of claim 1, The second step, And selectively etching the nitride film using a first mask, and then implanting a high concentration of impurities to simultaneously form the buried layer (3) and the lower layer isolation. The method of claim 1, The third step, A first sub-step of sequentially applying a second oxide film and a second nitride film on the resultant, defining a sink region by using a sink mask, etching the second nitride film, and ion implantation of impurities; Isolation (6), the anode areas of the sink and zener diodes are defined by photo transfer and etching, and after implanting high concentration impurities, the collector series resistances of the first and second bipolar transistors and the trench gate DMOS are turned on. A second sub-step of simultaneously diffusing the sink and the isolation layer by a high temperature heat treatment method to reduce the resistance; The first and second wells 7 and 8, which serve as collectors of the first and second LDMOS, the channel of the CMOS device, and the first bipolar transistor, are defined as photographic transfer, and then ion implantation of impurities, respectively. 3 substeps; And And performing a fourth sub-step of ion implanting impurities after photo etching the drift region 9 serving as a drift region of the first LDMOS device. . The method of claim 1, The fourth step, Performing a heat treatment of the first and second wells at a high temperature, then peeling off an oxide film, and further performing buffer oxide growth and nitride film application; A second sub-step connecting an upper isolation (6) and a lower isolation (3) and connecting the collector (8) of the first bipolar transistor with the buried layer (3) of the second LDMOS and LIGBT; A third sub-step of defining a drift layer (10) of the second LDMOS and an active base region (10) of the first bipolar transistor by photo transfer and etching, and implanting and diffusing impurities; And After defining the base region 11 of the first bipolar element, the ground region 11 of the trench gate DMOS, and the second drift 11 region of the LIGBT element, impurities are implanted into each of the regions at the same time to perform heat treatment. And a fourth sub-step comprising the manufacturing method of the smart power integrated circuit. The method of claim 1, The fifth step, Removing the nitride film, defining a body region (12) by a photo transfer method, implanting impurities and forming a body junction by heat treatment. The method of claim 1, The sixth step, In order to form a trench gate, a method of manufacturing a smart power integrated circuit, which first applies a TEOS (Tetra Ethyl Ortho Silicate) oxide film, performs photo transfer and etching, and then dry-etchs the TEOS oxide film as a mask layer. The method of claim 1, The seventh step, After a trench gate etching process, a first sub-step of growing a gate oxide layer 13 of the trench gate DMOS by thermal oxidation, depositing polycrystalline silicon by LPCVD, and doping polycrystalline silicon by thermal doping; And And defining a gate electrode (14) of the trench gate DMOS by photolithography, and then depositing a third nitride film on the entire surface by LPCVD. The method of claim 1, The eighth step, A first sub-step of selectively dry etching the nitride film using an active region mask, growing a field oxide film, and then removing the nitride film; And After defining the CMOS, the first and second LDMOS channel regions, an ion is implanted into the channel region to adjust a threshold voltage, and gate oxide film II (15−) is applied to the second LDMOS and CMOS elements. And a second sub-step of forming 1, 15-2). The method of claim 1, The ninth step, In order to form the polycrystalline silicon gate electrode 16 of the CMOS, first and second LDMOS, and LIGBT, polycrystalline silicon is deposited by an LPCVD method, and then an impurity doping process is performed, and the gate electrode is formed by photo transfer and dry etching. Forming a first sub-step; After depositing TEOS oxide on the entire surface of the resultant, forming side wall oxide (Side Wall Oxide) 17 by dry etching, defining LDD (Light Doped Drain) region of the CMOS as a photoresist, and implanting impurities A second sub-step of heat treatment to form an LDD junction; In order to facilitate current gain control of the first and second bipolar transistors and to prevent incomplete electrode formation due to impurity redistribution in the LIGBT and zener diodes, the emitter 18 and the zener diode of the first bipolar transistor A third sub-step of simultaneously performing photo transfer and dry etching of the cathode 19 region, followed by ion implantation of a high concentration of impurities; And In order to form the emitter 19 and the collector of the second bipolar transistor, the collector 19 of the LIGBT and the cathode 19 of the zener diode, phototransfer and dry etching are performed, and after ion implanting a high concentration of impurities, And a fourth sub-step of performing heat treatment. The method of claim 1, The tenth step is High concentration ion implantation of arsenic (As) into the CMOS, first and second LDMOS, trench gate DMOS and LIGBT device region, and at the same time high concentration ion implantation of arsenic into the inactive base region 20 of the first bipolar transistor 1 sub step; Defining a source-drain region (21) of the CMOS, first and second LDMOS, trench gate DMOS, and LIGBT elements by a photolithography process, and then performing a high ion implantation of impurities into the defined portion; And And performing a heat treatment process by ion implanting impurities at a high concentration into the inactive base region (21) of the second bipolar transistor. The method of claim 1, The eleventh step, A first sub-step of depositing an interlayer insulator TEOS / BPSG (Boron Phosphorous Silica Glass) 22 on a portion where metal wiring is formed, and performing contact point photo transfer and dry etching to form a contact window; And And forming a metal wiring (23) by depositing an Al—Cu metal with the metal wiring and removing an unnecessary portion, thereby manufacturing a smart power integrated circuit.