KR20010055444A - A circuit for controlling wordline of flash memory device - Google Patents

Abstract

PURPOSE: A word line control circuit of a flash memory device is provided to form a word line control circuit for preventing a malfunction due to an abnormal word line voltage. CONSTITUTION: A plurality of memory cells store data. A plurality of word lines are extended toward a row direction according to the memory cells. An address transition detection circuit(100) generates an address transition detection signal for detecting transition of addresses applied from the outside. A boosting control circuit(200) generates a boosting control signal according to the address transition detection signal. A boosting circuit(400) generates boosting voltage according to the boosting control signal. A word line selection circuit(500) transfers the boosting voltage to a selected word line according to a plurality of word line control signal. A word line control circuit(300) decodes the addresses and outputs the delayed word line control signals according to the address transition detection signal.

Description

Word line control circuit of flash memory device {A CIRCUIT FOR CONTROLLING WORDLINE OF FLASH MEMORY DEVICE}

The present invention relates to a flash memory device, and more particularly, to a word line control circuit for controlling a word line of a flash memory device.

Referring to FIG. 1, a flash memory cell has a current pass formed between a source 3 and a drain 4 on a semiconductor substrate 2, and a predetermined thickness on the semiconductor substrate 2. It is composed of a floating gate 6 and a control gate 8 formed with the insulating films 7 and 9 having (about 100 kV) interposed therebetween. The program of the flash memory cell grounds the source region 3 and the semiconductor substrate, that is, the bulk region 2, as shown in the following table, and has a positive high voltage (Vpgm, For example, by applying about 10V to 20V and applying a voltage (for example, about 5V to 6V) for programming to the drain region 4 to generate hot carriers. The hot carriers are charged to the floating region 6 by the electrons in the bulk region 2 accumulated in the floating gate 6 by an electric field of a high voltage Vpgm applied to the control gate 8. Are cumulative. When the flash memory cells are programmed, the flash memory cells have a program threshold voltage of a predetermined program voltage distribution (eg, about 6V to 7V).

Erase of the flash memory cell is performed by applying a negative high voltage Vera (for example, about −10 V to −20 V) to the control gate 8 as shown in the following table. By applying a predetermined voltage (e.g., about 5V) to 2) to cause FN tunneling (Fowler-Nordheim tunneling) phenomenon, the flash memory cells are erased in sector units sharing the bulk area (2) . The FN tunneling releases electrons accumulated in the floating gate 6 into the source region 3 so that the flash memory cells have an erase threshold voltage of a predetermined voltage distribution (for example, about 1V to 3V). To have

The flash memory cell of which the threshold voltage is increased by the program operation appears to be turned off during the read operation because current is prevented from being injected from the drain region 4 to the source region 3. In addition, the flash memory cell having the lower threshold voltage due to the erase operation appears to be turned on with current injected from the drain region 4 to the source region 3.

Table 1

Operation mode Vg Vd Vs Vb Program + 10 V + 5 V to + 6 V 0 V 0 V Cattle 10V Floating Floating + 6 V Sojeong Chung + 3 V + 5 V to + 6 V 0 V 0 V Reading + 4.5V + 1V 0 V 0 V

Since the flash memory cells are configured to share the bulk region 2 for high integration in a flash memory array, flash memory cells included in one sector are erased at the same time. At this time, if all of the flash memory cells in the sector are erased at the same time, some of the flash memory cells may be out of the erase threshold voltage distribution due to uniformity with respect to the threshold voltage of each of the flash memory cells. Flash memory cells having a threshold voltage of less than '0 V' out of the erase threshold voltage distribution are referred to as over erase memory cells, and for this purpose, the threshold voltage of the erased flash memory cell is used. A series of over erase repairs (over erase repairs) must be performed to distribute H into the erase threshold voltage distribution.

2 and 3, in order to transfer the program voltage Vpgm or the read voltage Vrea to a control gate of a flash memory cell, a word line WL corresponding to external addresses A is predetermined. It should be charged to the program voltage (Vpgm) or the read voltage (Vrea) level of. In general, a charge pump or a boosting circuit is used to generate the program voltage Vpgm or the read voltage Vrea, and a fast operating speed such as a NOR flash memory device is required. In the memory device, the boosting circuit 40 is mainly used.

When a plurality of addresses A1 are input from the outside for programming or reading the flash memory cell, the address transition detection circuit 10 provides the boosting control circuit 20 with the address transition signal ATD detected by the address transition detection circuit 10. do. The boosting control circuit 20 outputs a boosting control signal CON for controlling a boosting operation in response to the address transition signal ADT to the boosting circuit 40. At this time, the addresses A1 input from the outside are decoded through a decoder and output as a decoding address DA1.

The boosting circuit 40 outputs a boosting voltage Vboost (not shown) higher than the power supply voltage VCC in response to the boosting control signal CON from the boosting control circuit 20. When the boosting operation of the boosting circuit 40 starts, the node N1 of the boosting circuit 40 is charged to the power supply voltage level by the precharge circuit 43 controlled by the precharge signal PRE. Subsequently, when the boosting control signal CON having a logic low level is input, the boosting is maintained at the ground voltage VSS level through the current path of the PMOS transistor PM1 of the switching circuit 41 of the boosting circuit 40. One terminal of the capacitor 42 is charged to the power supply voltage VCC level.

As one terminal of the boosting capacitor 42 is charged to the power supply voltage VCC level, the voltage level of the node N1 is changed from the power supply voltage VCC level to a predetermined boosting voltage level by a coupling effect. Is raised. At this time, at least one of the switches S0, S1,..., Sn-1, Sn of the switching circuit 50 is turned on by the decoding addresses DA from the decoder 30. The boosting voltage Vboost from the boosting circuit 40 is provided to the word line WL selected by the decoder 30.

When the next addresses A2 are input from the outside, the word line WL corresponding to the addresses A1 is deactivated, and the word line WL corresponding to the addresses A2 should be deactivated. For example, assuming that the word line WL1 corresponds to the addresses A1 and the word line WLn corresponds to the addresses A2, after the addresses A1 are input, the word line WL1 ) Is activated until the next addresses A2 are entered and deactivated when the next addresses A2 are entered.

In addition, when the addresses A2 are input, the boosting voltage Vboost charged in the activated word line WL1 should be discharged to the power supply voltage VCC level. At this time, the boosting voltage Vboost charged in the activated word line WL1 is equal to the level of the power supply voltage VCC charged to one terminal of the boosting capacitor 42 of the word line selection circuit 41 in the boosting circuit 40. The charges are lowered to the power supply voltage VCC level by being discharged to the ground voltage VSS through the current path of the MOS transistor NM1. However, as shown in FIG. 3, when the word line WLn corresponding to the next addresses A2 is activated before the activated word line WL1 is inactivated, the boosting voltage Vboost lowered to the power supply voltage VCC level. Charges corresponding to the level are transferred to the word line WLn activated by the addresses A2 so that the voltage level of the node N1 becomes lower than the power supply voltage VCC level.

As such, when the voltage level of the node N1 is lower than the power supply voltage VCC level, the node N1 may have a lower boosting voltage Vboost than the previous boosting voltage Vboost during the next boosting operation of the boosting circuit 40. Is charged. Thus, when the word line WLn corresponding to the addresses A2 is activated, the boosting voltage Vboost lower than the required voltage level is transmitted to the word line WLn. As such, when a boosting voltage lower than the required voltage level is transferred to the selected word line WLn, a malfunction occurs in which a program or a read operation of the flash memory cell is not normally performed.

It is an object of the present invention to provide a word line control circuit of a flash memory device which prevents malfunction due to an abnormal word line voltage.

1 is a cross-sectional view showing the structure of a typical flash memory cell;

2 is a block diagram showing a simplified structure of a typical flash memory device;

3 is an operation timing diagram showing an operation of activating the word line of FIG.

4 is a block diagram showing the structure of a flash memory device according to the present invention;

5 is an operation timing diagram illustrating an operation of activating the word line of FIG. 4.

* Description of the symbols for the main parts of the drawings *

10, 100: address transition detection circuit 20, 200: boosting control circuit

30: decoder 300: word line control circuit

40, 400: boosting circuit 50, 500: word line selection circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, a flash memory device according to the present invention comprises a plurality of memory cells for storing data; A plurality of word lines extending along the memory cells in a row direction; An address transition detection circuit for generating an address transition detection signal that detects a transition of addresses applied from the outside; A boosting control circuit for generating the boosting control signal informing a boosting operation in response to the address transition detection signal; A boosting circuit for generating a boosting voltage having a voltage level higher than a power supply voltage in response to the boosting control signal; A word line selection circuit for transferring the boosting voltage from the boosting circuit to a word line selected by the word line control signals of the word lines in response to a plurality of word line control signals; Word line control circuitry that accepts the addresses and outputs the word line control signals that decode and delay the addresses in response to the address transition detection signal.

Here, the word line control circuit is a combination of a decoder for receiving the addresses and outputting a plurality of decoded decoding addresses, a delay circuit for delaying the address transition detection signal, and a combination of the decoding addresses and the address transition signal. And a combination circuit for outputting a signal as the word line control signal. The combination circuit is a NAND gate that NAND gates the addresses and the address transition detection signal.

(Action)

By such an apparatus, by activating another word line after the activated word line is deactivated, malfunctions caused by word line voltages lower than the voltage levels required during program and read operations are prevented.

(Example)

Hereinafter, reference will be described in detail with reference to FIGS. 4 to 5 according to a preferred embodiment of the present invention.

Referring to FIG. 4, a flash memory device according to the present invention includes an address transition detection circuit 100, a boosting control circuit 200, a word line control circuit 300, a boosting circuit 400, and a word line selection circuit 500. It includes. The address transition detection circuit 100 outputs an address transition detection signal ADT detecting a transition of the addresses A applied from the outside. The boosting control circuit 200 outputs a boosting control signal CON for controlling the boosting circuit 400 in response to the address transition detection signal. The word line control circuit 300 includes a delay circuit 310, a decoder 320, and a combination circuit 320, decodes the addresses A in response to the address transition detection signal ATD, and The delayed word line select signals COM are output. The boosting circuit 400 outputs a boosting voltage Vboost higher than the power supply voltage VCC in response to the boosting control signal CON. The word line select circuit 500 may perform the word line select signals COM among the plurality of word lines WL0, WL1,..., WLn-1, and WLn in response to the word line select signals COM. In this example, a word line WL corresponding to the first line WL is selected to transfer the boosting voltage Vboost from the boosting circuit 400 to the selected word line WL. As such, the word line control circuit 300 of the flash memory device according to the present invention decodes and delays the addresses A applied from the outside to prevent the unwanted activation of multiple word lines WL at the same time. As a result, malfunctions caused by word line voltages lower than the voltage levels required for program and read operations of the flash memory device are prevented.

Referring to FIG. 4, the flash memory device according to the present invention includes an address transition detection circuit 100, a boosting control circuit 200, a word line control circuit 300, a boosting circuit 400, and a word line selection circuit 500. It includes. The address transition detection circuit 100 receives a plurality of addresses A applied from the outside, and outputs an address transition detection signal ATD detected when the addresses A transition. The boosting control circuit 200 outputs a boosting control signal Vboost for controlling a boosting operation of the boosting circuit 400 in response to the address transition detection signal ADT.

The word line control circuit 300 includes a delay circuit 310, a decoder 320, and a combination circuit 330, accepts the addresses A, and responds to the address transition detection signal ATD. It decodes the addresses A and outputs word line select signals COM0, COM1, ..., COMn-1, COMn (hereinafter referred to as COM) which are delayed. The boosting circuit 400 outputs a boosting voltage Vboost having a voltage level higher than a power supply voltage VCC in response to the boosting control signal CON. The word line select circuit 500 may perform the word line select signal COM among a plurality of word lines WL0, WL1,..., WLn-1, and WLn in response to the word line select signals COM. Select the word line WL corresponding to.

Hereinafter, the operation of the flash memory device according to the present invention will be described in detail with reference to FIGS. 4 and 5.

4 and 5, the flash memory device may store data or read stored data in memory cells included in a memory cell array (not shown) through program, write, and read operations. In this case, voltages having a predetermined level must be applied to word lines WL and bit lines BL connected to corresponding memory cells. In particular, a boosting voltage Vboost having a voltage level higher than the power supply voltage VCC should be applied to the word line WL selected by the addresses A applied from the outside during a program or read operation, and the boosting circuit 400 serves to generate this boosting voltage Vboost.

In order to transfer the boosting voltage Vboost generated from the boosting circuit 400 to the word line WL corresponding to the addresses A, the word line control circuit 300 may be arranged in the word line selection circuit 500. The switches S0, S1,..., Sn−1 and Sn must be controlled to select the word line WL corresponding to the addresses A. FIG. At this time, if another word line WL is activated while the word line WL activated by the word line selection circuit 300 is inactivated, a problem occurs in that the boosting voltage Vboost level is lowered. In order to prevent such a problem, the word line control circuit 300 of the flash memory device according to the present invention decodes the addresses A applied from the outside and outputs the word line select signals COM which delay the delay. It features.

The address transition detection circuit 100 detects a transition of an address A (for example, it is assumed that the addresses A2 are input after an address A1 is input) applied from the outside and detects an address transition that informs of this. Output the signal ADT. The boosting control circuit 200 outputs a boosting control signal CON for controlling a boosting operation of the boosting circuit 400 in response to the address transition detection signal ADT.

In this case, the delay circuit 310 in the word line control circuit 300 outputs a delay signal DATD in which the address transition detection signal ATD is delayed to have a predetermined delay time. The decoder 320 outputs a plurality of decoding addresses DA1 obtained by decoding the addresses A1. The combination circuit 330 outputs a plurality of combination signals COM that combine the delay signal DATD and the decoding addresses DA1 as a word line selection signal. In this case, the word line selection signals COM may include a switch corresponding to the decoding addresses DA1 among the switches S0, S1,..., Sn−1 and Sn of the word line selection circuit 500. Turn on S).

The boosting circuit 400 performs a boosting operation in response to a boosting control signal CON from the boosting control circuit 200. First, a precharge operation for charging the node N2 to the power supply voltage VCC level before the boosting operation is performed. During the precharge operation, that is, when the boosting control signal CON is at a logic low level (hereinafter referred to as L), a precharge signal at a logic high level (hereinafter referred to as H). Under the control of PRE, the PMOS transistor of the precharge circuit 430 is turned on so that the node N2 is precharged to the power supply voltage VCC level. At this time, the NMOS transistor NM1 of the switch circuit 410 is turned on by the control of the boosting control signal CON so that one terminal of the boosting capacitor 420 is discharged to the ground voltage VSS level.

When the node N2 is precharged, the PMOS transistor PM1 of the switch circuit 410 is turned on by controlling the boosting control signal CON from the boosting control circuit 200 to turn on the boosting capacitor ( One terminal of 420 is charged to the power supply voltage VCC level. At this time, the node N2 is boosted to a level higher than the power supply voltage VCC due to a capacitor coupling effect as one terminal of the boosting capacitor 420 is charged to the power supply voltage VCC level. Thereafter, the boosting voltage Vboost is transferred to the corresponding word line through the turned-on switch of the word line selection circuit 500. Here, after the word line WL is selected, a process of performing a program or a read operation is obvious to those skilled in the art, and thus a detailed description thereof will be omitted.

When the program or read operation ends, the addresses A2 are applied from the outside to select the word line WL corresponding to the next addresses A2. At this time, the activated word line WL1 (assuming that WL1 is in an activated state and next addresses A2 correspond to the word line WLn) must be deactivated before the next word line WLn is activated. In order to deactivate the word line WL1, the boosting control circuit 200 outputs a boosting control signal CON having a logic low level L to the boosting circuit 400.

The switch circuit 410 in the boosting circuit 400 discharges the voltage level of one terminal of the boosting capacitor 420 to the ground voltage VSS level under the control of the boosting control signal CON. Thus, the voltage level of the node N2 is lowered from the boosting voltage Vboost to the power supply voltage VCC level by the capacitor coupling effect. However, when another word line WLn is activated by next addresses A2 before the activated word line WL1 is deactivated, the voltage level of the node N2 is lower than the power supply voltage VCC level. Descends. In order to prevent this, the word line control circuit 300 of the flash memory device according to the present invention uses a word line in which a next word line WLn is deactivated by using the address transition detection signal ATD and decoding addresses DA2. WL1) to prevent activation faster.

The delay circuit 310 of the word line control circuit 300 outputs a delay signal DATD, which delays the address transition detection signal ATD, to the combination circuit 330. The decoder 320 outputs decoding addresses DA2 decoded from the addresses A2 to the combination circuit 330. The combination circuit 300, that is, the NAND gate, outputs the combination signal COM NAND-gated the delay signal DATD and the decoding addresses DA2 as a word line control signal COM. As such, since the word line control signal COM is delayed by the time delay of the address transition detection signal ADT, the word lines WL1 and WLn corresponding to the addresses A1 and A2 that are continuously input are By preventing activation at the same time, the word line voltage is prevented from being lower than the required voltage level during program and read operations.

In the above, the word line control circuit of the flash memory device according to the present invention has been shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications are possible without departing from the technical spirit of the present invention. Of course.

As described above, by activating another word line after the activated word line is deactivated, malfunctions caused by word line voltages lower than the voltage levels required during program and read operations are prevented.

Claims (3)

A plurality of memory cells for storing data; A plurality of word lines extending along the memory cells in a row direction; An address transition detection circuit for generating an address transition detection signal that detects a transition of addresses applied from the outside; A boosting control circuit for generating the boosting control signal informing a boosting operation in response to the address transition detection signal; A boosting circuit for generating a boosting voltage having a voltage level higher than a power supply voltage in response to the boosting control signal; A word line selection circuit for transferring the boosting voltage from the boosting circuit to a word line selected by the word line control signals of the word lines in response to a plurality of word line control signals; And a word line control circuit that accepts the addresses and outputs the word line control signals that decode and delay the addresses in response to the address transition detection signal. The method of claim 1, The word line control circuit, A decoder which receives the addresses and outputs a plurality of decoded addresses decoded; A delay circuit for delaying the address transition detection signal; And a combination circuit for outputting a combined signal obtained by combining the decoding addresses and the address transition signal as the word line control signal. The method of claim 2, And the combination circuit is a NAND gate that NAND gates the addresses and the address transition detection signal.