KR20000050309A - Flash memory device having improved program and read operation speed - Google Patents

Abstract

PURPOSE: A flash memory device having improved program and reading operation speed is provided to improve a program and a reading operation speed by reducing a parasitic capacitance generated between a high voltage generator and a line decoder. CONSTITUTION: A line decoder(400) includes a plurality of odd line decoders and a plurality of even line decoders connected each selector of a memory cell array. A high voltage generator(800) has a program voltage generator(810), a switch(820) and a reading voltage generator(830). The program voltage generator(810) generates a program voltage(Vpp1) for programming memory cells of a memory cell array during a program operation. The reading voltage generator(830) generates a reading voltage(Vpp2) for reading data stored in memory cells of the memory cell array during a reading operation. The switch(820) transmits the program voltage(Vpp1) from the program voltage generator(810) to a word line driving circuit(900) during the program operation and prevents that the reading voltage(Vpp2) from the reading voltage generator(830) is short with the program voltage(Vpp1) from the program voltage generator(810) during the reading operation. The word line driving circuit (900) has a plurality of word line drivers connected to each line decoders.

Description

FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM AND READ OPERATION SPEED}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flash memory device, and more particularly, to a flash memory device which prevents malfunctions occurring during program and erase operations.

Referring to FIG. 1, a flash memory cell includes a current path formed between a source 3 and a drain 4 on a semiconductor substrate 2, and insulating layers 5 and 7 on the semiconductor substrate 2. And a floating gate 6 and a control gate 8 connected therebetween. The program operation of the memory cell grounds the source region 3 and the semiconductor substrate, that is, the bulk region 2, as shown in the following table, and positive high voltage (eg, to the control gate 8). For example, by applying 10V and applying a voltage (for example, 5 to 6V) for programming to the drain 4, it is performed by generating hot carriers. The hot carriers accumulate electrons in the bulk region 2 in the floating gate 6 by an electric field of the high voltage 10V applied to the control gate 8, thereby causing the memory cells to weaken. It has a threshold voltage distribution from '6V' to '8V'.

In the erase operation of the flash memory cell, a negative high voltage (-10V) is applied to the control gate 8 as shown in the following table, and a predetermined voltage (for example, the bulk region 2 is applied). , 6V) is applied to generate FN tunneling (Fowler-Nordheim tunneling), it is performed simultaneously in the sector (sector) unit sharing the bulk region (2). The FN tunneling is typically performed by discharging electrons accumulated in the floating gate 6 into the bulk region 2 by forming an electric field of 6 to 7 MV / cm between the insulating layers, thereby preventing the memory cells from about '1V'. It has a distribution of erase threshold voltages up to 3V. The cell in which the threshold voltage is increased by the program operation appears to be off because a current is prevented from being injected from the drain region 4 to the source region 3 during a read operation. The cell in which the threshold voltage is lowered by the erase operation appears to be turned on by a current injected from the drain region 4 to the source region 3 during a read operation.

Table

Operation mode Vg Vd Vs Vb Program + 10V + 5V to + 6V 0 V 0 V Cattle -10V Floating Floating + 6V Sojeong Chung + 3V + 5V to + 6V 0 V 0 V Reading + 4.5V + 1V 0 V 0 V

Since the memory cells are configured to share the bulk area 2 for high integration in the configuration of a flash memory array, the memory cells included in one sector are erased simultaneously. In this case, when the memory cells of the sector are simultaneously erased, each of the memory cells may leave some of the memory cells out of the erase threshold voltage range (1 to 3V) due to uniformity with respect to the threshold voltage. . Among the cells outside the erase threshold voltage range, memory cells having a threshold voltage of '0 V' or less are called over erase memory cells, and a threshold voltage is distributed within the erase threshold voltage range for them. A series of over erase repairs must be performed.

The read operation of the memory cells may ground the source region 3 and the bulk region 2, and apply a predetermined voltage (for example, 4.5V) to the control gate 8 as shown in the above table. And a predetermined voltage (for example, 1V) is applied to the drain terminal 4. The over erase recovery operation of the over erased memory cells grounds the source region 3 and the bulk region 2 and supplies a predetermined voltage (3V) to the control gate 8 as shown in the above table. And a predetermined voltage (for example, 5V to 6V) is applied to the drain terminal 4.

Referring to FIG. 2, a general flash memory device, in particular, a NOR type flash memory device, includes a row address buffer 10, a column address buffer 15, a control logic and command register 20, and a memory cell array. 30, a row decoder 40, a column decoder 50, a sense amplifier and write driver circuit 60, an input / output buffer 70, a high voltage generator circuit 80, and a word line driver circuit 90 do. The row address buffer 10 is provided with external addresses (for example, in the case of an 8 Mbit flash memory device, A0, A1, ...) by control of the control signal from the control logic and command register 20. , Corresponding to the addresses A17 and A18 are accepted. The column address buffer 15 receives corresponding ones of the addresses A0, A1, ..., A17, A18 from the outside by controlling the control signal from the control logic and command register 20. .

The control logic and command register 20 receives signals CEB, OEB, BYTEB, WEB, and RB from the outside and outputs a control signal for controlling the circuits 10, 15, 60, and 70. The signal CEB is a signal for notifying activation of the chip, the signal OBE is a signal for notifying the output of data, the signal BYTEB is a signal for determining a reading unit of data, and the signal WEB is In the program operation, the signal notifies the write operation and the signal RB is the signal informing the read operation. The memory cell array 30 is arranged so that the memory cells in a sector unit having the structure as shown in FIG. 1 and the plurality of word lines extending the memory cells in a row direction and the word lines W / L intersect each other. A plurality of bit lines BL extending along the direction are provided.

The row decoder 40 decodes the addresses A buffered by the row address buffer 10 to select word lines W / L of corresponding sectors of the memory cell array 30. The column decoder 50 decodes the addresses A buffered by the column address buffer 15 to select a bit line BL of a corresponding sector of the memory cell array 30. The sense amplifier and write driver circuit 60 are transferred from the memory cell array 30 through the column decoder 50 by the control of the control signal from the control logic and command register 20 during a read operation. During sensing and during a program operation, data programmed into the memory cell array is supplied to the memory cell array 30 through the column decoder 50.

The input / output buffer 70 receives the addresses A0, A1, ..., A17, A18 and data from the outside and is output from the sense amplifier and the write driver circuit 60 during a read operation. Output the read data to the outside. The high voltage generator circuit 80 generally includes a program voltage generator circuit, an erase voltage generator circuit, a read voltage generator circuit, and the like, and is a voltage transferred to memory cells of the memory cell array 30 during program, erase, and read operations. Occurs. The word line driver circuit 90 selectively transfers one of the program voltage, the erase voltage, and the read voltage from the high voltage generator circuit 80 to the row decoder 40.

Referring to FIG. 3, a NOR flash memory device in a sector unit according to the related art includes a high voltage generation circuit 80, a word line driving circuit 90, and a memory cell array 30. The high voltage generation circuit 80 may include a program voltage generation circuit 81 that generates a program voltage Vpp1 during a program operation, a read voltage generation circuit 83 that generates a read voltage Vpp2 during a read operation, and the And a switch 82 for selectively transferring a program voltage Vpp1 and the read voltage Vpp2 to the word line driver circuit 90. The word line driver circuit 90 is a row decoder connected to the output terminal of the high voltage generator 80 and the sectors S0, S1,..., Si-1, Si of the memory cell array 30. And a plurality of word line drivers WD0, WD1, ..., WDi-1, WDi connected between the fields RD0, RD1, ..., RDi-1, RDi.

Referring to FIG. 4, each of the row decoders RD0, RD1,..., RDi-1, RDi connected to the sectors S0, S1, Si-1, and Si of the memory cell array 30 may be described. It is divided into an odd row decoder RDe and an even row decoder RDo. Each of the word line drivers WD0, WD1,..., WDi-1, and WDi may select one of the program voltage Vpp1 and the read voltage Vpp2 from the high voltage generator 80. The odd and even row decoders RDe and RDo are simultaneously transmitted.

Referring to FIG. 5, the read voltage generator circuit 83 of the high voltage generator circuit 80 includes a level shifter 83a and a pumping circuit 83b. The level shifter 83a receives a low level voltage indicating the pumping operation of the pumping circuit 83b by controlling a logic high level signal nPMP indicating the generation of a read voltage from the outside. Will output When the level shifter 83a receives the signal nPMP, the current path of the NMOS transistor NM1 is blocked, the current path of the NMOS transistor NM2 is conducted so that the node N1 is charged to a high level. Node N2 is discharged to the low level.

The pumping circuit 83b includes MOS transistors PM3, PM4, PM5, and NM3 and a capacitor C1. The MOS transistors PM3 and NM3 are switched by control of the signal Φ Bn from the outside, and the MOS transistor PM5 is controlled by the output signal from the level shifter 83a and the PMOS transistor ( PM4) is controlled by the signal? Pre from the outside. The read voltage generation circuit 83 generates the read voltage Vpp2 for reading data of a memory cell in a corresponding sector of the memory cell array 30 during a read operation.

The read voltage Vpp2 is a signal in which a current path of the MOS transistor PM5 of the pumping circuit 83b is conducted by control of a low level output signal from the level shifter 83a and has a predetermined period. When the current path of the MOS transistor PM4 is turned on under the control of? Pre, and the output terminal of the pumping circuit 83b is charged to the power supply voltage Vcc level, the signal? Bn having a predetermined period is It is generated by controlling the switching operation of the MOS transistors PM3 and NM3 to pump the power supply voltage charged to one terminal of the capacitor C1. The capacitor C2 of the pumping circuit 83b shows parasitic capacitance existing between the output terminal and the row decoders RD0, RD1, ..., RDi-1, RDi of each sector. .

Referring to FIG. 6, each of the word line driving circuits WD0, WD1,..., WDi-1, WDi may include inverters I1, I2, I3, I4, I5, NAND gate ND1, and NOR. A combination circuit having gates NOR1, NOR2, NOR3, a level shift circuit having MOS transistors PM1, PM2, NM1, NM2 and a switching circuit having MOS transistors PM4, PM5, PM6, PM7. do. The MOS transistors PM3 and PM5 of the switching circuit are controlled by the voltage levels of both output terminals of the level shift circuit and the MOS transistors PM4 and NM3 are output signals of the inverters I4 and I5 of the combination circuit. Controlled by During the read operation, each of the word line driving circuits WD0, WD1, ..., WDi-1, WDi is in control of logic low level signals Vexen and LVppen and logic high level signal SA. The current path of the MOS transistor PM3 is conducted so that the odd and even row decoders RD0, RD1, ..., RDi- connected the read voltage Vpp2 from the read voltage generation circuit 83 to each sector. 1. RDi).

In recent years, as all the systems become faster, the program and read operations of the flash memory device are also required to be faster. However, in the flash memory device according to the related art, the program voltage Vpp1 or the read voltage Vpp2 is applied to each of the sectors S0, S1,. There is a problem that a time delay occurs due to the operation of transferring to the row decoders RD0, RD1, ..., RDi-1, RDi of ... Si-1, Si. The time delay is the output terminal of the read voltage generator circuit 83 and the row decoders RD0, RD1, ..., RDi- of the sectors S0, S1, ..., Si-1, Si. 1. The influence by parasitic capacitance C2 existing between RDi) is the largest.

Accordingly, an object of the present invention is to provide a flash memory device having a fast program and read operation speed.

1 is a cross-sectional view of a typical flash memory cell;

2 is a block diagram showing a typical flash memory device;

3 is a block diagram showing a high voltage generation circuit, a word line driving circuit and a row decoder according to the prior art;

4 is a block diagram showing the word line driving circuit of FIG. 3;

5 is a circuit diagram illustrating the high voltage generating circuit of FIG. 3;

FIG. 6 is a circuit diagram illustrating the word line driving circuit of FIG. 3; FIG.

7 is a block diagram showing a high voltage generating circuit, a word line driving circuit and a row decoder according to the present invention;

8 is a block diagram illustrating the word line driver circuit of FIG. 7;

9 is a detailed circuit diagram showing the word line driver circuit of FIG. 7;

10 is a waveform diagram illustrating an operating characteristic of a flash memory device according to the present invention.

* Explanation of symbols on the main parts of the drawings

400: row decoder 800: high voltage generation circuit

900 word line driving circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, a memory cell array including a plurality of sectors having a plurality of memory cells of the floating gate type, and a corresponding word line of each sector of the memory cell array A flash memory device having a first group of row decoders for selecting one of the two groups and a second group of row decoders for selecting one of the corresponding word lines of the respective sectors may have a predetermined voltage level during a program operation. A high voltage generation circuit for generating a program voltage having a read voltage and generating a read voltage having a predetermined voltage level lower than the program voltage during a read operation; The program voltage or the read voltage from the high voltage generation circuit in response to a sector address, an address for selecting one of the first and second groups of row decoders, and the first and second control signals; And a word line driving circuit which transfers to a corresponding one of the first and second groups of row decoders.

In this embodiment, the word line driving circuit combines the sector address, the address, the first and second control signals, and inverts the first, second, third control signals, and the first control signal. A combination circuit for outputting; A switch control circuit outputting first and second switch control signals in response to the first control signal and the inverted signal; Selectively transmitting one of a power supply voltage, the program voltage, the read voltage, and the ground voltage to a corresponding row decoder in response to the first and second switch control signals and the second and third combination signals. It includes a switch circuit.

In this embodiment, the combination circuit comprises: a first combination circuit for outputting the first combination signal combining the sector address, the address, and the first and second control signals; An inverter for outputting the inverted signal inverting the first combination signal; A second combining circuit for outputting the second combined signal combining the sector address, the first and second control signals; And a third combining circuit for outputting the third combined signal combining the inverted signal and the first and second control signals.

(Action)

By such a device, in the program or read operation, the program and read voltages can be selectively transmitted to odd row decoders or even row decoders connected to each sector to reduce parasitic capacitance, thereby improving the program and read operation speed. have.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 7 to 10 according to an embodiment of the present invention.

Referring to FIG. 7, the novel flash memory device of the present invention includes a row decoder 400, a high voltage generator circuit 800, and a word line driver circuit 900. The row decoder 400 includes a plurality of odd row decoders RD0e, RD1e, ..., RDi-1e, RDie) and a plurality of even row decoders RD0o, RD1o, which are connected to each sector of the memory cell array. .., RDi-1o, RDio). The high voltage generator circuit 800 includes a program voltage generator circuit 810, a switch 820, and a read voltage generator circuit 830. The word line driver circuit 900 includes a plurality of words connected to the corresponding row decoders RD0e, RD1e, RDi-1e, RDie, RD0o, RD1o, RDi-1o, and RDio. Line drivers WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi-1o, WDie, WDio. In the flash memory device according to the present invention, each of the word line drivers WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi-1o, WDie, WDio may be a sector from the outside during a program or read operation. The odd number of sectors SAi corresponding to the program voltage Vpp1 or the read voltage Vpp2 from the high voltage generation circuit 800 is controlled by the control of the address SAi, the address Ai, and the signals Vexen and LVppen. And a parasitic capacitance generated between the high voltage generating circuit 800 and the row decoder 400 by transferring the data to one of the even row decoders RDie and RDio, to reduce the parasitic capacitance. Can improve speed.

Referring to FIG. 7, the flash memory device according to the present invention, in particular the NOR-type flash memory device, has the same components as the flash memory device of FIG. 2 except for the high voltage generation circuit 800 and the word line driving circuit 900. The high voltage generator circuit 800 of the flash memory device according to the present invention includes a program voltage generator circuit 810, a switch 820, and a read voltage generator circuit 830. Although not shown, the program voltage generation circuit 810 generates a program voltage Vpp1 for programming the memory cells of the memory cell array during a program operation. The read voltage generation circuit 830 generates a read voltage Vpp2 for reading data stored in a memory cell of the memory cell array during a read operation. The switch 820 transfers the program voltage Vpp1 from the program voltage generation circuit 810 to the word line driving circuit 900 during the program operation by controlling the signal nPMP from the outside. During the read operation, the read voltage Vpp2 from the read voltage generator 830 is prevented from being shorted with the program voltage Vpp1 from the program voltage generator 810.

The word line driver circuit 900 may include row decoders RD0e, RD1e, ..., RDi-1e connected to corresponding sectors S0, S1, ..., Si-1, Si of the memory cell array. Multiple word line drivers (WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi-1o, WDie, WDio) connected to RDie, RD0o, RD1o, ..., RDi-1o, RDio The program voltage Vpp1 or the read voltage Vpp2 from the high voltage generation circuit 800 may include the row decoders RD0e, RD1e, RDi-1e, RDie, RD0o, RD1o, ..., RDi-1o, RDio) to the corresponding row decoder. The row decoder 400 includes row decoders RD0e, RD1e, ..., RDi-1e, RDie connected to corresponding sectors S0, S1, ..., Si-1, Si of the memory cell array. , RD0o, RD1o, ..., RDi-1o, RDio, each of the memory cells corresponding to the decoded address DRA by decoding the addresses A from the row address buffer 10 of FIG. The program voltage Vpp1 or the read voltage Vpp2 is supplied to gates.

Referring to FIG. 8, the word line driving circuit 900 of the flash memory device according to the present invention may include row decoders RD0e, RD1e, connected to respective sectors S0, S1,. Multiple word line drivers (WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi) connected to ..., RDi-1e, RDie, RD0o, RD1o, ..., RDi-1o, RDio -1o, WDie, WDio). For example, as shown in FIG. 8, each of the row decoders RDie and RDio has odd-numbered word lines W / L1 and W / L3 of the sector Si. , ..., W / Ln-3, W / Ln-1) and even word lines (W / L0, W / L2, ..., W / Ln-2, W / Ln), respectively do. The word line drivers WDie and W / Lio corresponding to the sector Si of the word line driver circuit 900 are connected to the corresponding row decoders RDie and RDio. Each of the word line drivers WDie and W / Lio selectively selects the program voltage Vpp1 or the read voltage Vpp2 from the high voltage generation circuit 800 as corresponding row decoders RDie and RDio, respectively. To pass.

9, the word line drivers WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi-1o, WDie, WDio of the word line driver circuit 900 according to the present invention are combined. The circuit unit COMB, the level shift circuit LS, and the switch circuit SW are included. The combination circuit unit COMB includes an inverter I1, first, second and third combination circuits COMB1, CONB2, and COMB3. The first combination circuit unit COMB1 includes NOR gates NOR1 and NOR2 and a NAND gate ND1, and combines a sector address SA, an address A, and signals Vexen and LVppen. The combined signal COM1 is output. The inverter I1 inverts the first combination signal COM1. The second combination circuit COMB2 includes inverters I2 and I3 and NOR gates NOR3 and NOR4, and the sector address SA and the signals Vexen are brought into a logic high level during an erase operation. A second combination signal COM2 that combines the signal being enabled, LVppen; which is enabled at a logic high level when Vpp is lower than Vcc) is output. The third combination circuit COMB3 includes a NOR gate NOR5 and an inverter I4, and a third combination combining the combination signal COM1B and the signals Vexen and LVppen from the inverter I1. Output the signal COM3.

The level shift circuit LS includes MOS transistors PM1, PM2, NM1, NM2, and receives the program voltage Vpp1 or the read voltage Vpp2, and a combined signal from the combination circuit COMB. The switch circuit SW is controlled in response to the signals COM1 and COM1B. The switch circuit SW includes MOS transistors PM3, PM4, PM5, NM3, and output signals from the level shift circuit LS and second and third combinations from the combination circuit COMB. One of the power supply voltage Vcc, the program voltage Vpp1, and the read voltage Vpp2 is transmitted to the row decoder 400 by controlling the signals COM2 and COM3.

Hereinafter, the operation of the flash memory device according to the present invention will be described with reference to FIGS. 7 to 10.

7 to 10, in the flash memory device according to the present invention, word line drivers WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi-1o, WDie, WDio corresponds to the program voltage Vpp1 or the read voltage Vpp2 from the high voltage generation circuit 800 by controlling the sector address SAi, the address Ai, and the signals Vexen and LVppen from the outside. The parasitic capacitance generated between the high voltage generator circuit 800 and the row decoder 400 may be transferred to one of the row decoders RDi among the odd and even row decoders RDie and RDio of the sector SAi. By reducing, the program and read operation speed are improved.

As shown in FIG. 7, the flash memory device according to the present invention includes a plurality of row decoders RD0e, RD1e, ..., RDi-1e, RDie, RD0o, RD1o, which are connected to respective sectors of the memory cell array. Word line driver circuit 900 having a plurality of word line drivers WD0e, WD0o, WD1e, WD1o, ..., WDi-1e, WDi-1o, WDie, WDio connected to RDi-1o, RDio) ). The word line drivers (eg, WDie, WDio) may have a corresponding row decoder (RDi) among the row decoders (RDie, RDio) connected to one sector (eg, SAi) as shown in FIG. 8. Are each connected to.

When the program operation starts, the program voltage generation circuit 810 of the high voltage generation circuit 800 generates the program voltage Vpp1 having a predetermined voltage level (eg, 10V). In this case, the switch 820 transfers the program voltage Vpp1 to the word line driving circuit 900 under the control of the signal nPMP having a logic low level. In addition, when a read operation is started, the read voltage generator 830 of the high voltage generator 800 generates the read voltage Vpp2 having a predetermined voltage level (for example, 4V). In this case, the switch 820 blocks the output path of the program voltage Vpp1 under the control of the signal nPMP having a logic high level.

When the program voltage Vpp1 or the read voltage Vpp2 is supplied to the word line driver circuit 900, each of the word line drivers WDe and WDo of FIG. 9 is connected to the voltages Vpp1 and Vpp2. One of the power supply voltages Vcc is selectively transferred to the row decoders RDe and RDo. The first combination circuit COMB1 of the combination circuit COMB combines a logic high level sector address SA and an address A with logic low level signals Vexen and LVppen during the program or read operation. The first combination signal COM1 of one logic low level is output. In this case, the sector address SA is an address for selecting a sector, and the address A is a signal for selecting one of odd and even row decoders. The inverter I1 inverts the voltage level of the first combined signal COM1. The second combination circuit COMB2 outputs the second combination signal COM2 having the logic low level combining the sector address SA of the logic high level and the signals Vexen and LVppen of the logic low level. . The third combination circuit COMB3 is configured to combine the combination signal COM1B from the inverter I1 and the signals Vexen and LVppen of a logic low level with the third combination signal COM3 having a logic high level. Outputs

During the program or the read operation, the level shift circuit LS is controlled by the first combination signal COM1 from the combination circuit 800 and the inverted first combination signal COM1B. The MOS transistors PM3 and PM5 of (SW) are controlled. When the first combination signal COM1 having a logic low level and the inverted first combination signal COM1B having a logic high level are input from the combination circuit COMB to the level shift circuit LS, the level shift circuit The current path of the MOS transistor NM1 of the LS is blocked and the current path of the MOS transistor NM2 is conducted. Accordingly, the node ND1 formed at the drain of the MOS transistor NM1 is charged with the program voltage Vpp1 or the read voltage Vpp2 and the node ND2 formed at the drain of the MOS transistor NM2 is It is discharged to the ground voltage (Vss) level.

The current path of the MOS transistor PM3 of the switch circuit SW is conducted by the low level voltage of the node ND2 of the level shift circuit LS, so that the program voltage Vpp1 or the read voltage ( Vpp2) is supplied to the corresponding row decoder RD. The current path of the MOS transistor PM5 is blocked by a high level voltage charged at the node ND1 of the level shift circuit LS, so that the program voltage Vpp1 or the read voltage Vpp2 is reduced. Prevent leakage to power supply voltage (Vcc). In addition, each of the current paths of the MOS transistors PM4 and NM3 is blocked by the control of the second and third combination signals COM2 and COM3 from the combination circuit COMB, thereby reducing the program voltage Vpp1. The read voltage Vpp2 is prevented from leaking to the power supply voltage Vcc or the ground voltage Vss.

In addition, the switch circuits SW of the word line drivers connected to the sectors in which the program or the read operation is not performed may use the row decoders RD corresponding to the power supply voltage Vcc instead of the program voltage Vpp1 or the read voltage Vpp2. To pass). As a result, the word line driving circuit 900 selects the program voltage Vpp1 or the read voltage Vpp2 from the high voltage generation circuit 800 by the sector address SA and the address A. By selectively supplying to the odd row decoder RDe or the even row decoder RDo of SA, parasitic capacitances generated between the high voltage generator circuit 800 and the row decoder 400 in the memory cell array (FIG. 2). C2) can be greatly reduced.

Referring to FIG. 10, when the power supply voltage Vcc is 2.5 V and a read operation is performed at 100 ns (nano second), a read voltage generated by the read voltage generation circuit 83 of the flash memory device according to the related art is described. (Vpp2) and the read voltage Vpp2 generated by the read voltage generation circuit 830 of the flash memory device according to the present invention (1), the read voltage generation circuit 83 of the flash memory device according to the prior art is compared. The read voltage Vpp2 old generated at has a voltage level of 4.2 V, whereas the read voltage Vpp2 new generated at the read voltage generator 830 of the flash memory device according to the present invention is 4.5 V at the same time. Has a voltage level of. This is a difference due to the coupling ratio between the capacitor C1 of the read voltage generator circuits 83 and 830 and the parasitic capacitor C2.

Then, the voltage level Vpxi new delivered to the row decoder RDi of the flash memory device according to the present invention, the voltage level W / L new delivered to the word line W / L, and the flash according to the related art. The voltage level Vpxi old transmitted to the row decoder RDi of the memory device is compared with the voltage level W / L old transmitted to the word line W / L (2, 3) and finally the word line W / L) is 4.2V, the word line (W / L new) of the flash memory device according to the present invention occupies 4.2V is the word line (W / L) of the flash memory device according to the prior art It is about 10ns faster than the point where old) is charged with 4.2V. At this time, the reason why the voltage of the word line (W / L) is 4.2V is compared because the memory of the word line (W / L) of '4.2V' is not erased (worse erased) during the read operation This is because the minimum voltage required to read the data of the cell. As described above, when the read operation speed of a general flash memory device is 100ns at an external power supply voltage of 2.5v, the speed reduction of 10ns is very large.

For reference, the parasitic capacitance value of FIG. 2 is about 61 pF in the case of a 16M-class flash memory device, and the loading of the row decoder is about 27.8 pF. However, in the flash memory device according to the present invention, the overall parasitic capacitance is reduced to about 47.1 pF. This value means a reduction of about 22.8% compared to the prior art, and means that the flash memory device according to the present invention has a faster program and read operation speed than the flash memory device according to the prior art under the same conditions.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

As described above, during the program or read operation, the program and read operation speed may be improved by selectively transferring the program voltage or the read voltage to odd row decoders or even row decoders connected to each sector, thereby reducing parasitic capacitance. .

Claims (3)

A memory cell array including a plurality of sectors having a plurality of floating gate type memory cells, a first group of row decoders for selecting one of corresponding word lines of each sector of the memory cell array, A flash memory device having a second group of row decoders for selecting one of corresponding word lines of sectors: A high voltage generation circuit for generating a program voltage having a predetermined voltage level during a program operation and generating a read voltage having a predetermined voltage level lower than the program voltage during a read operation; The program voltage or the read voltage from the high voltage generation circuit in response to a sector address, an address for selecting one of the first and second groups of row decoders, and first and second control signals; And a word line driver circuit for transferring one of the first and second groups of row decoders to a corresponding one of the row decoders. The method of claim 1, The word line driver circuit, A combination circuit for combining the sector address, the address, the first and second control signals, and outputting first, second and third control signals and inverted signals of the first control signal; A switch control circuit for outputting first and second switch control signals in response to the first control signal and the inversion signal; Selectively transmitting one of a power supply voltage, the program voltage, the read voltage, and the ground voltage to a corresponding row decoder in response to the first and second switch control signals and the second and third combination signals. Flash memory device comprising a switch circuit. The method of claim 2, The combination circuit, A first combining circuit for outputting the first combined signal combining the sector address, the address, and the first and second control signals; An inverter for outputting the inverted signal inverting the first combination signal; A second combining circuit for outputting the second combined signal combining the sector address, the first and second control signals, and And a third combining circuit for outputting the third combined signal combining the inverted signal and the first and second control signals.