KR20010053953A - Multi chip package - Google Patents

Multi chip package Download PDF

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Publication number
KR20010053953A
KR20010053953A KR1019990054529A KR19990054529A KR20010053953A KR 20010053953 A KR20010053953 A KR 20010053953A KR 1019990054529 A KR1019990054529 A KR 1019990054529A KR 19990054529 A KR19990054529 A KR 19990054529A KR 20010053953 A KR20010053953 A KR 20010053953A
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South Korea
Prior art keywords
semiconductor chip
leads
bonding pads
chip
semiconductor
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KR1019990054529A
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Korean (ko)
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도재천
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윤종용
삼성전자 주식회사
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Priority to KR1019990054529A priority Critical patent/KR20010053953A/en
Publication of KR20010053953A publication Critical patent/KR20010053953A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A multi-chip package is provided to reduce the number of wire by shortening a distance between a bonding pad and a lead. CONSTITUTION: The second semiconductor chip(130) is laminated on an upper portion of the first semiconductor chip(110). The first semiconductor chip(110) is connected electrically to the second semiconductor chip(130). A multitude of conductive lead(210) is printed on a tape(200). The tape(200) is connected electrically to the first and the second semiconductor chips(110,130). A solder bump(230) connects electrically the first semiconductor chip(110) with the leads(210). A wire(235) connects electrically the second semiconductor chip(130) with the leads(210). A molding portion(150) covers a predetermined portion of the tape(200) and the first and the second semiconductor chips(110,130).

Description

멀티 칩 패키지{Multi chip package}Multi chip package

본 발명은 멀티 칩 패키지에 관한 것으로, 더욱 상세하게는 리드들이 인쇄된 테이프에 하나의 반도체 칩을 접착시키고 리드들과 반도체 칩의 본딩패드들을 솔더범프로 접속시킨 후에, 테이프와 접착된 반도체 칩의 상부면에 다른 하나의 반도체 칩을 부착시키며 본딩패드들과 리드들을 와이어로 연결시킴으로써 제품을 박형화시킨 멀티 칩 패키지에 관한 것이다.The present invention relates to a multi-chip package. More particularly, the present invention relates to a multi-chip package, and more particularly, to bonding a semiconductor chip to a printed tape and connecting the leads and bonding pads of the semiconductor chip to solder bumps. The present invention relates to a multi-chip package having a thin product by attaching another semiconductor chip to an upper surface and connecting bonding pads and leads with wires.

전자·정보기기 등이 다기능화, 고속화, 대용향화 및 소형화됨에 따라 이들에 내장되는 반도체 칩 패키지 또한, 크기가 작고 메모리 용량은 큰 반도체 칩 패키지가 개발되고 있다.As electronic and information devices have become more versatile, faster, larger, and smaller, semiconductor chip packages embedded therein have also been developed with smaller chip sizes and larger memory capacities.

이에 따라, 최근에는 반도체 칩 크기의 120%에 근접하는 칩 스케이 패키지,예를 들어 파인 피치 볼 그리드 어레이 패키지(fine pitch ball grid array package)가 개발되었고, 반도체 칩 패키지의 실장면적을 증대시키고 메모리 용량을 증대시키기 위해서 2개의 반도체 칩을 패키징하여 하나의 제품을 만드는 멀티 칩 패키지를 기술이 소개되고 있다.Accordingly, in recent years, a chip skew package, for example, a fine pitch ball grid array package, which is close to 120% of the size of a semiconductor chip, has been developed, increasing the mounting area of the semiconductor chip package and increasing memory capacity. In order to increase the number of chips, a technology for introducing a multi-chip package in which two semiconductor chips are packaged to make a single product is introduced.

이와 같이 2개의 반도체 칩을 패키징하여 소정의 메모리 용량을 갖는 멀티 칩 패키지를 제작하는 방법에는 크게 2가지가 있는데, 하나는 패키징이 완료된 2개의 반도체 칩 패키지를 수직으로 적층시켜 멀티 칩 패키지를 형성하는 방법이고, 나머지 하나는 2개의 반도체 칩을 수직으로 적층시킨 후에 패키징하여 멀티 칩 패키지를 형성하는 방법이다.As described above, there are two methods for manufacturing a multi-chip package having a predetermined memory capacity by packaging two semiconductor chips. One is to vertically stack two packaged semiconductor chip packages to form a multi-chip package. The other method is a method in which two semiconductor chips are stacked vertically and then packaged to form a multi-chip package.

2가지 방법 중 후자에 소개된 멀티 칩 패키지의 제조 과정에 대해 도 1을 참조하여 개략적으로 설명하면 다음과 같다.A manufacturing process of the multi-chip package introduced in the latter of the two methods will be described with reference to FIG. 1 as follows.

폭방향 양측단부 쪽으로 본딩패드들(13)이 형성되고 소정크기를 갖는 제 1 반도체 칩(10)을 리드 프레임(20)의 다이패드(23)에 부착시킨다. 그리고, 제 1 반도체 칩(10)의 상부면 소정부분에 제 1 반도체 칩(10) 보다 크기가 작은 제 2 반도체 칩(30)을 접착제(40)를 이용하여 부착시키는데, 이때 제 1 반도체 칩(10)의 본딩패드들(13)은 제 2 반도체 칩(30)의 외부로 노출되어야 한다.Bonding pads 13 are formed toward both ends of the width direction, and the first semiconductor chip 10 having a predetermined size is attached to the die pad 23 of the lead frame 20. The second semiconductor chip 30 having a smaller size than the first semiconductor chip 10 is attached to the predetermined portion of the upper surface of the first semiconductor chip 10 by using the adhesive 40. At this time, the first semiconductor chip ( Bonding pads 13 of 10 should be exposed to the outside of the second semiconductor chip 30.

이후, 리드 프레임(20)과 제 1 및 제 2 반도체 칩(10,30)을 전기적으로 연결시키기 위해서 먼저, 제 1 반도체 칩(10)의 폭방향 양측 가장자리에 형성된 본딩패드들(13)과 이에 대응하는 각각의 리드들(25)을 제 1 와이어(15)로 연결시킨 다음에, 제 2 반도체 칩(30)의 본딩패드들(33)과 이에 대응하는 각각의 리드들(25)을제 2 와이어(35)로 연결시킨다. 그러면, 하나의 리드(25)에 제 1 및 제 2 와이어(15,35)가 본딩되는데, 리드(25)에서 제 2 와이어들(35)은 제 1 와이어들(15)의 뒷쪽에 본딩된다.Subsequently, in order to electrically connect the lead frame 20 and the first and second semiconductor chips 10 and 30, first, bonding pads 13 formed at both side edges of the first semiconductor chip 10 in the width direction thereof and After connecting the respective leads 25 to the first wire 15, the bonding pads 33 and the corresponding leads 25 of the second semiconductor chip 30 are connected to the second wire. (35). Then, the first and second wires 15 and 35 are bonded to one lead 25. In the lead 25, the second wires 35 are bonded to the rear side of the first wires 15.

그리고, 제 1 및 제 2 반도체 칩(10,30)이 수직으로 적층되는 멀티 칩 패키지에서는 도 1에 도시된 바와 같이, 반드시 제 1 반도체 칩(10)의 본딩패드들(13)이 가장자리에 형성되어야 하며, 제 2 반도체 칩(30)의 크기는 제 1 반도체 칩(10)의 크기보다 작아야 한다. 이는 앞에서 언급한 바와 같에 제 1 반도체 칩(10)의 상부면에 제 2 반도체 칩(30)이 적층되면 와이어 본딩 공정을 진행하기 위해서 제 1 반도체 칩(10)의 본딩패드들(13)이 제 2 반도체 칩(30)의 외부로 노출되어야 하기 때문이다.In the multi-chip package in which the first and second semiconductor chips 10 and 30 are vertically stacked, as shown in FIG. 1, bonding pads 13 of the first semiconductor chip 10 are formed on the edge. The size of the second semiconductor chip 30 should be smaller than that of the first semiconductor chip 10. As described above, when the second semiconductor chip 30 is stacked on the upper surface of the first semiconductor chip 10, the bonding pads 13 of the first semiconductor chip 10 may be formed in order to proceed with the wire bonding process. This is because the semiconductor chip 30 must be exposed to the outside.

한편, 와이어 본딩 공정이 완료되면, 제 1 및 제 2 반도체 칩(10,30)과, 제 1 및 제 2 와어어(15,35), 와이어(15,35)가 본딩된 리드들(25)의 단부 소정부분을 보호하기 위해서 제 1 및 제 2 반도체 칩(10,30)을 포함하여 리드(25)의 소정부분까지 에폭시 수지로 덮으므로, 제 1 빛 제 2 반도체 칩(10,30)의 외부에 몰딩물(50)을 형성한다.Meanwhile, when the wire bonding process is completed, the leads 25 to which the first and second semiconductor chips 10 and 30, the first and second wires 15 and 35, and the wires 15 and 35 are bonded. The first and second semiconductor chips 10 and 30 may be covered with an epoxy resin to cover a predetermined portion of the lead 25, including the first and second semiconductor chips 10 and 30 to protect a predetermined portion of the end portion of the lead 25. The molding 50 is formed on the outside.

상술한 바와 같이 제 1 및 제 2 반도체 칩을 수직으로 적층시킨 후에 제 1 및 제 2 반도체 칩과 리드들을 전기적으로 연결시키기 위해서 각각의 리드들에 2개씩의 와이어를 본딩시키고, 제 1 및 제 2 반도체 칩을 감싸는 몰딩공정을 진행 할 경우, 금형에 유입되는 에폭시 수지의 압력에 의해 와이어가 변형되거나 에폭시 수지가 흐르는 방향으로 와이어들이 휩쓸려 인접한 와이어들이 접촉되어 쇼트가 발생될 가능성이 높아진다.As described above, after vertically stacking the first and second semiconductor chips, two wires are bonded to the respective leads to electrically connect the first and second semiconductor chips and the leads, and the first and second When the molding process is wrapped around the semiconductor chip, the wire is deformed by the pressure of the epoxy resin flowing into the mold, or the wire is swept in the direction in which the epoxy resin flows, so that the adjacent wires are in contact with each other and a short may occur.

특히, 제 2 반도체 칩의 본딩패드들과 리드들 연결하는 제 2 와이어의 경우에 제 1 와이어보다 길이가 길이 때문에 제 2 와이어들에서 쇼트가 발생될 가능성이 크다.In particular, in the case of the second wire connecting the bonding pads and the leads of the second semiconductor chip, since the length is longer than that of the first wire, a short may occur in the second wires.

또한, 종래에서는 합금재질의 리드 프레임이 사용되고, 각 와이어들의 처짐을 방지하기 위해서 제 1 와이어와 제 2 와이어 사이, 제 1 및 제 2 반도체 칩들과 각 와이어들 사이의 높이가 어느 정도 유지시되어야 하기 때문에 멀티 칩 패키지의 크기가 커진다.In addition, in the related art, a lead frame made of an alloy material is used, and a height between the first and second semiconductor chips and the first and second semiconductor chips and the respective wires must be maintained to some extent to prevent sagging of each wire. This increases the size of the multichip package.

따라서, 본 발명의 목적은 상기와 같은 문제점을 감안하여 안출된 것으로써, 본딩패드들과 리드들 간의 거리를 최대한 짧게 형성하고, 본딩패드들과 리드들을 전기적으로 연결시켜 주는 와이어들의 개수를 줄여 몰딩공정에서 와이어들이 변형되거나 쇼트되는 현상을 최소화하는데 있다.Accordingly, an object of the present invention has been made in view of the above problems, forming the distance between the bonding pads and leads as short as possible, reducing the number of wires electrically connecting the bonding pads and leads molding This is to minimize the deformation or shorting of wires in the process.

본 발명의 다른 목적은 반도체 칩 패키지의 박형화시키고 입출력 핀들의 개수를 증가시켜 멀티 칩 패키지의 화이핀화를 실현시키는데 있다.Another object of the present invention is to realize thinning of a semiconductor chip package and increasing the number of input / output pins to realize the pinning of a multi-chip package.

본 발명의 또 다른 목적은 다음의 상세한 설명과 첨부된 도면으로부터 보다 명확해 질 것이다.Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

도 1은 종래의 멀티 칩 패키지 구조를 개략적으로 나타낸 단면도이고,1 is a cross-sectional view schematically showing a conventional multi-chip package structure,

도 2는 본 발명에 의한 테이프와 반도체 칩들이 전기적으로 연결된 상태를 나타낸 사시도이며,2 is a perspective view showing a state in which the tape and the semiconductor chip according to the present invention electrically connected,

도 3은 본 발명에 의한 멀티 칩 패키지의 구조를 나타낸 단면도이다.3 is a cross-sectional view showing the structure of a multi-chip package according to the present invention.

이와 같은 목적을 달성하기 위한 본 발명은 외부단자와 전기적으로 연결되는 리드들이 형성되고 리드들 주면에 소정크기의 오픈영역이 형성된 베이스 기판, 리드들이 형성된 방향과 대응되는 방향으로 본딩패드들이 형성되며 본딩패드들과 리드들이 대응되도록 베이스 기판의 일면에 부착되어 베이스 기판과 전기적으로 연결되는 제 1 반도체 칩, 제 1 반도체 칩의 본딩패드들과 리드들 사이에서 제 1 반도체 칩의 본딩패드들과 리드들을 전기적으로 연결시키는 솔더범프, 리드들과 대응되는 방향으로 본딩패드들이 형성되며 오픈영역으로 노출된 제 1 반도체 칩의 일면 소정영역에 부착되어 베이스 기판 및 제 1 반도체 칩과 전기적으로 연결되는 제 2 반도체 칩, 제 2 반도체 칩의 본딩패드들과 리드들을 전기적으로 연결시키는 와이어, 제 1 및 제 2 반도체 칩과 와이어를 포함하여 오픈영역의 외측 소정영역까지 감싸 제 1 및 제 2 반도체 칩과 와이어를 보호하는 몰딩물로 구성된다.In order to achieve the above object, the present invention provides a base substrate in which leads are electrically connected to an external terminal, a base substrate having an open area of a predetermined size formed on a main surface of the leads, and bonding pads are formed in a direction corresponding to the direction in which the leads are formed. Bonding pads and leads of the first semiconductor chip are attached to one surface of the base substrate so that the pads and the leads correspond to each other, and the bonding pads and the leads of the first semiconductor chip are electrically connected to the base substrate. Bond pads are formed in the direction corresponding to the solder bumps and the leads that are electrically connected to each other, and are attached to a predetermined region of one surface of the first semiconductor chip exposed to the open area, and are electrically connected to the base substrate and the first semiconductor chip. Chip, wires electrically connecting bonding pads and leads of a second semiconductor chip, first and second peninsulas It includes a molding to protect the first and second semiconductor chip and the wire, including the sieve chip and the wire to cover the predetermined area outside the open area.

이하, 본 발명에 의한 멀티 칩 패키지의 구조를 첨부된 도면 도 2 및 도 3을 참조하여 설명하면 다음과 같다.Hereinafter, the structure of a multichip package according to the present invention will be described with reference to FIGS. 2 and 3.

본 발명에 의한 멀티 칩 패키지(100)는 도 3에 도시된 바와 같이 제 1 반도체 칩(110), 제 1 반도체 칩(110)의 상부면에 적층되어 제 1 반도체 칩(110)과 전기적으로 연결되는 제 2 반도체 칩(130), 일면에 전도성의 리드들(210)이 인쇄되어 제 1 및 제 2 반도체 칩(110,130)과 전기적으로 연결되는 테이프(200), 제 1 반도체 칩(110)과 리드들(210)을 전기적으로 연결시키는 솔더범프(230), 제 2 반도체 칩(130)과 리드들(210)을 전기적으로 연결시키는 와이어(235) 및 제 1 및 제 2 반도체 칩들(110,130)을 포함하여 테이프(200)의 소정부분을 감싸는 몰딩물(150)로 구성된다.As shown in FIG. 3, the multi-chip package 100 according to the present invention is stacked on an upper surface of the first semiconductor chip 110 and the first semiconductor chip 110 to be electrically connected to the first semiconductor chip 110. The second semiconductor chip 130, the conductive leads 210 printed on one surface thereof, and the tape 200 electrically connected to the first and second semiconductor chips 110 and 130, and the first semiconductor chip 110 and the lead. A solder bump 230 for electrically connecting the holes 210, a wire 235 for electrically connecting the second semiconductor chip 130 and the leads 210, and the first and second semiconductor chips 110 and 130. It consists of a molding 150 surrounding a predetermined portion of the tape (200).

도 3에 도시된 바와 같이 제 1 반도체 칩(110)과 제 2 반도체 칩(130)의 폭방향 양측 가장자리에는 연결부재, 즉 솔더범프(230) 및 와이어(235)에 의해서 리드들(210)과 전기적으로 연결되는 본딩패드들(113,133)이 제 1 및 제 2 반도체 칩(110,130)의 장변을 따라 일렬로 형성된다.As shown in FIG. 3, the edges of the first semiconductor chip 110 and the second semiconductor chip 130 may be connected to the leads 210 by connecting members, that is, solder bumps 230 and wires 235. Electrically connected bonding pads 113 and 133 are formed in a line along the long sides of the first and second semiconductor chips 110 and 130.

여기서, 제 2 반도체 칩(130)은 제 1 반도체 칩(110)의 일면에 접착제(140)에 의해서 접착되는데, 제 1 반도체 칩(110)에 형성된 본딩패드들(113)이 제 2 반도체 칩(130)에 의해 가려지지 않도록 제 1 반도체 칩(110)의 크기보다 작은 제 2 반도체 칩(130)이 제 1 반도체 칩(110)의 상부면에 부착된다.Here, the second semiconductor chip 130 is bonded to one surface of the first semiconductor chip 110 by the adhesive 140, and the bonding pads 113 formed on the first semiconductor chip 110 are formed of the second semiconductor chip ( The second semiconductor chip 130 smaller than the size of the first semiconductor chip 110 is attached to the upper surface of the first semiconductor chip 110 so as not to be covered by the 130.

본 발명에 의한 테이프(200)는 도 2에 도시된 바와 같이 중앙에 본딩패드들(113)을 포함한 제 1 반도체 칩(110)의 상부면 소정부분이 외부로 노출되도록 오픈영역(220)이 형성되고, 오픈 영역(220)의 장변을 따라 제 1 반도체 칩(110)과 제 2 반도체 칩(130)을 외부단자와 전기적으로 연결시키는 리드들(210)이 서로 소정간각 이격되어 형성되는데, 리드들(210)은 오픈영역(220)의 내부 소정부분에서부터 오픈영역(220)의 외측으로 소정길이 연장된다.In the tape 200 according to the present invention, as shown in FIG. 2, an open region 220 is formed such that a predetermined portion of the upper surface of the first semiconductor chip 110 including the bonding pads 113 is exposed to the outside. The leads 210 electrically connecting the first semiconductor chip 110 and the second semiconductor chip 130 to external terminals are formed to be spaced apart from each other at predetermined intervals along the long side of the open region 220. Reference numeral 210 extends a predetermined length from the inside of the open area 220 to the outside of the open area 220.

도 2와 도 3에는 도시되어 있지 않지만 리드들(210)의 상부에는 리드들(210)을 보호하기 위한 커버필름(도시 안됨)이 부착된다.Although not shown in FIGS. 2 and 3, a cover film (not shown) for protecting the leads 210 is attached to the upper portions of the leads 210.

이와 같이 구성된 멀티 칩 패키지의 제조 방법을 개략적으로 설명하면 다음과 같다.The manufacturing method of the multi-chip package configured as described above will be described as follows.

도 3에 도시된 바와 같이 제 1 반도체 칩(110)의 상부면에 형성된 본딩패드들(133) 각각에 소정직경을 갖는 구형상의 솔더범프(230)을 형성하고, 오픈영역(220)에 위치한 리드들(210)의 일단과 솔더범프들이 마주보도록 제 1 반도체 칩(110)을 리드들(210)이 형성되지 않은 테이프(200)의 일면에 부착시킨다. 이때, 본딩패드들(113)은 오픈영역(220)을 통해 테이프(200)의 외부로 노출되며, 본딩패드들(113)의 상부에 형성된 솔더범프들(230)은 서로 대응되는 리드들(210)의 단부에 접촉된다.As shown in FIG. 3, a spherical solder bump 230 having a predetermined diameter is formed on each of the bonding pads 133 formed on the upper surface of the first semiconductor chip 110, and the lead is positioned in the open region 220. The first semiconductor chip 110 is attached to one surface of the tape 200 on which the leads 210 are not formed so that one end of the field 210 and the solder bumps face each other. In this case, the bonding pads 113 are exposed to the outside of the tape 200 through the open area 220, and the solder bumps 230 formed on the bonding pads 113 correspond to the leads 210. ) To the end of the

이후, 제 1 반도체 칩(110)과 테이프(200)에 소정온도의 열을 가하여 솔더범프(230)를 녹이므로 본딩패드들(113)과 리드들(210)을 전기적으로 접속시킨다.Thereafter, the solder bumps 230 are melted by applying a predetermined temperature to the first semiconductor chip 110 and the tape 200 to electrically connect the bonding pads 113 and the leads 210.

이어, 오픈 영역(220)을 통해 테이프(200)의 외부로 노출된 제 1 반도체 칩(110)의 상부면 소정부분에 접착제(140)를 부착하고, 접착제(140)의 상부면에 본딩패드들(133)이 형성되지 않은 제 2 반도체 칩(130)의 일면을 부착함으로써, 제 1 반도체 칩(110)의 상부면에 제 2 반도체 칩(130)을 적층시킨다.Subsequently, the adhesive 140 is attached to a predetermined portion of the upper surface of the first semiconductor chip 110 exposed to the outside of the tape 200 through the open area 220, and the bonding pads are attached to the upper surface of the adhesive 140. By attaching one surface of the second semiconductor chip 130 on which the 133 is not formed, the second semiconductor chip 130 is stacked on the upper surface of the first semiconductor chip 110.

계속해서, 와이어(235)를 생성하는 캐필러리(도시 안됨)를 이용하여 제 2 반도체 칩(130)의 본딩패드들(133)과 리드들(210)을 전기적으로 연결시키는데, 캐필러리에서 생성되는 와이어(235)의 일단을 본딩패드(133)에 본딩시킨 후에 캐필러리를 테이프(200) 쪽으로 이동시켜 캐필러리에서 생성된 와이어(235)의 타단을 리드들(210)에 본딩시킨다.Subsequently, a capillary (not shown) that generates a wire 235 is electrically connected to the bonding pads 133 and the leads 210 of the second semiconductor chip 130, in the capillary. After bonding one end of the generated wire 235 to the bonding pad 133, the capillary is moved toward the tape 200 to bond the other end of the wire 235 generated in the capillary to the leads 210. .

이와 같이 제 1 반도체 칩(110)과 제 2 반도체 칩(130)이 테이프(200)와 전기적으로 연결되면, 제 1 및 제 2 반도체 칩(110,130)과, 와이어(235) 및 리드들(210)을 보호하기 위해서 제 1 및 제 2 반도체 칩(110,130)과 와이어(235)를 포함한 오픈영역(220)의 외측 소정부분까지를 에폭시 수지로 감싼 후 에폭시 수지를 경화시켜 몰딩물(150)을 형성한다.As such, when the first semiconductor chip 110 and the second semiconductor chip 130 are electrically connected to the tape 200, the first and second semiconductor chips 110 and 130, the wire 235, and the leads 210 may be formed. In order to protect the mold, the molded part 150 is formed by wrapping the epoxy resin around the predetermined portion of the open area 220 including the first and second semiconductor chips 110 and 130 and the wire 235 with an epoxy resin. .

여기서, 제 1 반도체 칩(110)의 본딩패드들(113)과 리드들(210)은 솔더 범프(230)로 연결되기 때문에 본딩패드들(133)과 리드들(210)을 전기적으로 연결시키는 와이어(235)의 개수가 줄어들고, 도 3에 도시된 바와 같이 와이어(235)의 길이가 종래에 비해 짧아지므로, 몰딩 공정을 진행할 경우 에폭시 수지의 흐름에 의해 와이어들(235)에 변형되고 인접한 와이어들(235) 간에 쇼트가 발생될 확률이 줄어든다.Here, since the bonding pads 113 and the leads 210 of the first semiconductor chip 110 are connected to the solder bumps 230, a wire electrically connecting the bonding pads 133 and the leads 210 to each other. Since the number of the 235 is reduced and the length of the wire 235 is shorter than in the related art as shown in FIG. 3, when the molding process is performed, the wires are deformed and adjacent to the wires 235 by the flow of epoxy resin. There is a reduced chance of a short between 235.

또한, 반도체 칩들과 외부단자를 전기적으로 연결시키는 테이프의 두께가 종래의 리드 프레임의 두께보다 얇고 와이어의 높이가 종래에 비해 낮기 때문에 반도체 칩을 박형화할 수 있다.In addition, since the thickness of the tape electrically connecting the semiconductor chips and the external terminals is thinner than the thickness of the conventional lead frame and the height of the wire is lower than in the related art, the semiconductor chip can be thinned.

이상에서 설명한 바와 같이 본 발명은 2개 이상의 반도체 칩이 수직으로 적층되는 멀티 칩 패키지에서 어느 하나의 반도체 칩의 본딩패드들은 솔더범프를 이용하여 리드들의 단부에 탭본딩시키고, 나머나 하나의 반도체 칩의 본딩패드들은 와이어를 이용하여 리드들의 단부에 와이어 본딩시킴으로써, 멀티 칩 패키지에서 와이어의 개수를 최소화시킨다.As described above, in the multi-chip package in which two or more semiconductor chips are vertically stacked, the bonding pads of one of the semiconductor chips are tab-bonded to the ends of the leads using solder bumps, and the other one semiconductor chip is used. The bonding pads of the wires are wire bonded to the ends of the leads using wires, thereby minimizing the number of wires in the multi-chip package.

따라서, 에폭시 몰딩 컴파운드의 흐름으로 인해 와이어들이 에폭시 몰딩 컴파운드가 흐르는 방향으로 쏠리는 것을 최소화시킬 수 있어 제품의 신뢰성을 향상된다.Therefore, the wires can be minimized due to the flow of the epoxy molding compound in the direction in which the epoxy molding compound flows, thereby improving product reliability.

또한, 다이패드가 없고 와이어들이 이루는 루프의 높이가 낮기 때문에 멀티 칩 패키지의 두께가 박형화되는 이점이 있다.In addition, since there is no die pad and the height of the loop formed by the wires is low, the thickness of the multi-chip package is reduced.

Claims (3)

외부단자와 전기적으로 연결되는 리드들이 형성되고, 상기 리드들 주면에 소정크기의 오픈영역이 형성된 베이스 기판;A base substrate having leads formed electrically connected to an external terminal and having an open area of a predetermined size formed on a main surface of the leads; 상기 리드들이 형성된 방향과 대응되는 방향으로 본딩패드들이 형성되며, 상기 본딩패드들과 상기 리드들이 대응되도록 상기 베이스 기판의 일면에 부착되어 상기 베이스 기판과 전기적으로 연결되는 제 1 반도체 칩;Bonding first pads formed in a direction corresponding to a direction in which the leads are formed, and attached to one surface of the base substrate so as to correspond to the bonding pads and the leads and electrically connected to the base substrate; 상기 제 1 반도체 칩의 본딩패드들과 상기 리드들 사이에서 상기 제 1 반도체 칩의 본딩패드들과 상기 리드들을 전기적으로 연결시키는 솔더범프;Solder bumps electrically connecting the bonding pads of the first semiconductor chip and the leads between the bonding pads of the first semiconductor chip and the leads; 상기 리드들과 대응되는 방향으로 본딩패드들이 형성되며, 상기 오픈영역으로 노출된 상기 제 1 반도체 칩의 일면 소정영역에 부착되어 상기 베이스 기판 및 상기 제 1 반도체 칩과 전기적으로 연결되는 제 2 반도체 칩;Bonding pads are formed in a direction corresponding to the leads, and are attached to a predetermined region of one surface of the first semiconductor chip exposed to the open area and are electrically connected to the base substrate and the first semiconductor chip. ; 상기 제 2 반도체 칩의 본딩패드들과 상기 리드들을 전기적으로 연결시키는 와이어; 및Wires electrically connecting the bonding pads of the second semiconductor chip and the leads; And 상기 제 1 및 제 2 반도체 칩과 상기 와이어를 포함하여 상기 오픈영역의 외측 소정영역까지 감싸 상기 제 1 및 제 2 반도체 칩과 상기 와이어를 보호하는 몰딩물을 포함하는 것을 특징으로 하는 멀티 칩 패키지.And a molding to protect the first and second semiconductor chips and the wire, including the first and second semiconductor chips and the wire to cover a predetermined area outside the open area. 제 1 항에 있어서, 상기 베이스 기판은 상기 리드들이 패터닝된 테이프로, 상기 리드들은 상기 오픈 영역의 내측 소정부분에서부터 상기 오픈영역의 외측으로소정길이 연장되어 형성되는 것을 특징으로 하는 멀티 칩 패키지.The multi-chip package of claim 1, wherein the base substrate is a tape in which the leads are patterned, and the leads are formed by extending a predetermined length from an inner predetermined portion of the open area to the outside of the open area. 제 1 항에 있어서, 상기 제 2 반도체 칩의 크기는 상기 제 1 반도체 칩의 크기보다 작아 상기 제 1 반도체 칩의 일면에 상기 제 2 반도체 칩이 부착되면 상기 제 1 반도체 칩의 본딩패드들이 상기 제 2 반도체 칩의 외부로 노출되는 것을 특징으로 하는 멀티 칩 패키지.The method of claim 1, wherein the size of the second semiconductor chip is smaller than the size of the first semiconductor chip, and when the second semiconductor chip is attached to one surface of the first semiconductor chip, bonding pads of the first semiconductor chip are formed. 2 A multi-chip package, characterized in that exposed to the outside of the semiconductor chip.
KR1019990054529A 1999-12-02 1999-12-02 Multi chip package KR20010053953A (en)

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