KR20010048281A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the size of a pattern such as an overlay key or alignment key from being varied by reducing the path of a defocused image which transmits an insulating layer under a photoresist pattern and is reflected and transferred to a photoresist pattern in a photolithography process. CONSTITUTION: A pattern having a size greater than 2 micro meters is formed on a semiconductor substrate(100) where an insulating layer(102) is stacked. Before the pattern is formed, a reflecting layer(112b) is formed in a portion where the pattern is to be formed so that the size of the pattern is prevented from being varied. The reflecting layer is composed of metal or polysilicon.

Description

Method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing a change in the size of an overlay key for measuring overlay alignment between patterns.

Fabrication of integrated circuits requires implanting impurities into small regions of the silicon substrate and interconnecting the regions to form circuit components. Patterns defining these areas are formed by a photographic process. That is, first, the photoresist is spin-coated on top of the wafer, and then the photoresist layer is selectively exposed by irradiation of light such as ultraviolet rays, electron-beams or X-rays. Patterns in the photoresist layer are formed when the wafer is subsequently subjected to a developing step. The photoresist areas remaining after development protect the substrate areas it covers. The areas where the photoresist has been removed are subject to various processes for transferring the pattern onto the surface of the substrate, namely lift-off or etching.

In the above-described photographic process, an apparatus used to transfer patterns onto a photoresist-coated wafer, that is, a printer, an exposure tool, or an aligner, is a sub-system as follows. It includes; That is, (a) a light source providing optical energy to deform the photoresist, (b) an optical subsystem for focusing patterns on the surface of the wafer and controlling the exposure time, and (c) mobility to support the wafer to be exposed. Stages, (d) alignment subsystems such as manual alignment, (e) wafer handling subsystems, and (f) exposure systems. Here, the position of the stage must be very finely adjusted so that an image from an optical pattern transfer tool such as a mask or a reticle can be aligned with respect to patterns already printed on top of the wafer.

According to the conventional alignment method, an alignment key formed by a photographic process accompanied by etching in the previous stage by using a diffraction phenomenon using a short wavelength laser or an intensity difference using white light of a broadband band in an exposure facility. After reading the coordinate value of, calculate the correction value and proceed with the alignment, the exposure and development process is performed. The overlay key formed on the wafer is then used to measure the degree of overlap of the current pattern for the previous layer in a separate metrology system.

The alignment key used in the exposure facility and the overlay key used in the overlay metrology system have different patterns. A typical overlay key consists of a trench-shaped mother made of an etched pattern of the underlying layer as a reference, and a mesa-shaped son made of a photoresist pattern formed in the current photographic process. In the measurement system, signals of the mother and son are obtained by using an arbitrary light source, and the relative displacement of the son with respect to the mother is obtained by comparing the center of the mother and the son of the son at each measurement position through signal processing. If the measured displacement value is spec-in, proceed with the subsequent process such as etching process.If the measured value is spec-out, calculate the correction value for misalignment and then expose and develop again. Proceed with the process.

Therefore, in overlay alignment, obtaining accurate displacement value without measuring error at each measurement position determines alignment accuracy. If a change in the size of the overlay key for each position in the same wafer occurs, a measurement error may be caused and accurate overlay alignment may not be performed.

1 is a cross-sectional view showing a conventional overlay key region.

Referring to FIG. 1, auxiliary patterns such as an alignment key of an exposure facility or an overlay key of an overlay metrology facility are formed in a scribe line area that separates a chip from a chip so as not to affect a circuit operation. Typically, the scribe line region is opened during the etching process when the non-transmissive layer is deposited to remove the non-transmissive layer, so that only the oxide layer is continuously stacked.

For example, in the scribe line region during the photolithography process for forming a via hole, which is one of semiconductor back-end processes, an oxide layer 12 having a thickness of about 20000 μs is stacked up to the silicon substrate 10, and the scribe line Even in the region, the oxide film layer 12 has a thickness change of about 4000 kPa. Therefore, when the light transmitted through the thick oxide layer 12 under the photoresist pattern 14 is reflected from the silicon substrate 10 under the oxide layer 12 during the photolithography process and then comes out toward the photoresist pattern 14 again. The defocus image corresponding to twice the thickness of the oxide layer 12 is transferred to the photoresist pattern 14 (see the circled region of FIG. 1). At this time, if the defocus image is larger than the threshold value of the photoresist, the pattern image is affected and the size of the overlay key is changed.

In addition, since a change in the thickness of the oxide layer 12 in the scribe line region also causes a change in the size of the overlay key, a change in the size of the overlay key is caused for each position in the same wafer, resulting in measurement error or incapacity during measurement of overlay. Done. In particular, when the reticle is designed to apply an overdose so that more exposure energy is required than usual, this change in size of the overlay key appears more severe.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the size change caused by a defocused image of a large pattern such as an overlay key or an alignment key.

1 is a cross-sectional view of a conventional overlay key forming region.

2 is a graph showing the results of simulating the change in the size of the overlay key pattern on the exposed wafer.

3 is a graph showing the results of simulating the change in the size of the overlay key pattern on the oxide layer.

4 is a graph illustrating a comparison of spatial intensities according to degree of defocus for each pattern size.

5A and 5B are cross-sectional views illustrating scribe line regions and chip regions, respectively, according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 silicon substrate 102 insulating layer

104: first metal wiring 106: first interlayer insulating layer

108: first via hole 110: first via plug

112a: second metal wiring 112b: reflective film

114: second interlayer insulating layer 116: photoresist pattern

118: second via hole region

In order to achieve the above object, the present invention is a semiconductor device manufacturing method of forming a pattern having a size of 2㎛ or more on the semiconductor substrate on which the insulating layer is laminated, the pattern is formed before the step of forming the pattern A method of manufacturing a semiconductor device, comprising the step of forming a reflective film on a portion to be made, can prevent the size change of the pattern.

Preferably, the reflecting film is formed of metal or polysilicon.

Preferably, the reflecting film is formed so that the thickness of an insulating layer may be 10000 Pa or less.

According to the present invention, a reflective film is formed in advance on a portion where a large pattern having a pattern size of 2 μm or more, such as an overlay key or an alignment key, is to be formed, thereby reducing the thickness of the insulating layer on the pattern formation portion. Therefore, the size of the pattern may be prevented by reducing the path of the defocus image transmitted through the insulating layer under the photoresist pattern and then reflected and transferred to the photoresist pattern during the photolithography process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present inventors simulated the change in the size of the overlay key pattern in the exposed state of the bare wafer and in a state where a 20000 층 thick oxide layer was stacked on the exposed wafer to find the cause of the change in the size of the overlay key. . The size of the overlay key pattern is represented by the threshold after development (ADI CD).

Fig. 2 is a graph showing the results of simulation of the change in the size of the overlay key on the exposed wafer, where? Is the case where the dose of the photographing process is 1000 msec and ■ is the case where the dose is 1200 msec. Fig. 3 is a graph showing the results of simulation of the change of the overlay key size on the oxide layer, where is the case where the dose in the photolithography process is 1800 msec, × is the dose of 1400 msec, ■ is the dose of 1000 msec, and ◆ is the dose. Represents the case of 800 msec.

2 and 3, in the exposed wafer state, the size of the overlay key pattern increases as the optimum focus is formed and defocused near zero, but the change in exposure energy and focus change in the defocused state is increased. The fluctuation is small. In contrast, in a state where 20000 Å oxide films are stacked, an optimum focal point is formed at about 1 μm, and the size of the overlay key pattern at this time is about 1 μm larger than the exposed wafer state. In addition, the size of the overlay key pattern increases as the defocus is similar to the exposed wafer state in the oxide layer stacking state, but at the same point (circle region) defocused at about −3 μm, 0.5 μm compared to the exposed wafer state. The change in the size of the overlay key caused by the change in focus of the degree is more significant. In particular, it can be seen that as the exposure energy, that is, the dose, increases, the size of the overlay key becomes more severe.

FIG. 4 is a graph comparing the intensity of an spatial image according to the degree of defocus for each pattern size, wherein the focus is 0, +2, and +4 μm for patterns of 0.3 μm, 0.5 μm, and 3.0 μm. It is a graph simulated under the conditions. Here, the thickest line represents the condition that the focus is 0.0 mu m, and the thinnest line indicates the condition that the focus is +4 mu m.

Referring to FIG. 4, the small patterns B and A having sizes of 0.3 μm and 0.5 μm, respectively, have almost no spatial intensity due to the rapid loss of image information when defocus of 2 μm or more occurs. In contrast, the large pattern C having a size of 3.0 mu m widens the image intensity profile when defocusing at 2 mu m or more occurs, but still has a large spatial intensity. Therefore, it can be interpreted that the defocus image reflected from the underlying film of the photoresist pattern affects only a large pattern having a size of 2 μm or more.

If the threshold of the photoresist is determined at an intensity of 0.3, a pattern having a negative oblique profile larger than the original size will be formed by the reflected defocus image. The change in the pattern size due to the defocus image is intensified as the pattern is formed under high exposure energy, that is, at low spatial intensity.

5A and 5B are cross-sectional views illustrating a scribe line region and a chip region, respectively, according to an embodiment of the present invention, and a method for preventing a size change of an overlay key formed in a photo process for forming a second via hole. To illustrate.

Referring to FIGS. 5A and 5B, an insulating layer 102 is deposited on the silicon substrate 100 on which conductive devices such as transistors, bit lines, or capacitors are formed, and the devices are electrically connected from the first metal wiring. Insulate A first capping layer made of titanium (Ti) / titanium nitride (TiN) is deposited on top of the insulating layer 102 by depositing a metal, for example, aluminum by sputtering, on top of the insulating layer 102. Not deposited). The first capping layer and the first metal layer 104 are patterned by a photolithography process to form a first metal wiring 104, which is a wiring for the devices.

An oxide film is deposited to a thickness of about 10000 GPa on the resulting product on which the first metal wiring 104 is formed to form a first intermetal dielectric layer (IMD) 106, and chemical mechanical polishing (CMP). The surface of the first interlayer insulating layer 106 is planarized. Subsequently, the first interlayer insulating layer 106 is etched by a photolithography process to form a first via hole 108 exposing the surface of the first metal wiring 102. In the photolithography process for forming the first via hole 108, the first key is measured by measuring the relative displacement of the son to the mother of the overlay key formed in the previous step using the son of the overlay key formed of the photoresist pattern on the scribe line region. The overlap alignment between the metallization 104 and the first via hole 108 is performed. In addition, a mother (not shown) of the overlay key for the second metal wiring to be formed thereon upon formation of the first via hole 108 is formed on the scribe line region.

Subsequently, a metal, such as tungsten, is deposited on top of the resultant by chemical vapor deposition (CVD) and tungsten by chemical mechanical polishing (CMP) until the surface of the first interlayer insulating layer 106 is exposed. The layer is etched to form a first via plug 110 in the first via hole 108.

A second capping layer made of titanium (Ti) / titanium nitride (TiN) is deposited on top of the resultant on which the first via plug 110 is formed by depositing a metal, for example aluminum, by sputtering. (Not shown) is deposited. The second capping layer and the second metal layer are patterned by a photolithography process to form a second metal wire 112a electrically connected to the first metal wire 104 by the first via plug 110. Conventionally, although the second metal layer, which is a non-transmissive film, is removed from the scribe line region, in the present invention, the second metal layer is also patterned in the scribe line region to form the reflective film 112b on the portion where the overlay key pattern is to be formed in a subsequent process. In this case, an additional deposition process or an additional reticle is not required to form the reflective film 112b, and only a large pattern forming part may cause a change in size of the reticle for patterning the second metal wiring 112a. What is necessary is just to manufacture so that the reflective film 112b may be formed in it.

Also, by measuring the relative displacement of the son to the mother of the overlay key formed in the previous step by using the son of the overlay key formed in the scribe line area during the photolithography process for patterning the second metal wiring 112a, the first via hole ( 108 and the overlap alignment between the second metal wiring 112a is performed.

The second interlayer dielectric layer 114 is formed by depositing an oxide film with a thickness of about 10000 GPa on the upper part of the resultant product on which the second metal wiring 112a and the reflective film 112b are formed, and using the chemical mechanical polishing (CMP) method. The surface of the insulating layer 114 is planarized. Next, a photoresist pattern 116 is formed to open the region 118 where the second via hole is to be formed on the second interlayer insulating layer 114 through a photolithography process. At this time, the son of the overlay key made of the photoresist pattern 116 is formed in the scribe line region, the second metal wiring 112a and the second via by measuring the relative displacement of the son to the mother of the overlay key formed in the previous step Perform overlap alignment between holes.

According to the conventional method, during the photolithography process for forming the second via hole, the first interlayer insulating layer and the second interlayer insulating layer are stacked so that an oxide layer having a thickness of 20000 Å or more remains. Therefore, when light transmitted through an oxide layer having a thickness of about 20000 m under the photoresist pattern is reflected from the silicon substrate under the oxide layer and then comes out toward the photoresist pattern, a defocus image corresponding to twice the thickness of the oxide layer is formed. It is transferred to the resist pattern to cause a change in the size of the overlay key.

On the other hand, in the scribe line region of the present invention, since the reflective film 112b is stacked between the first interlayer insulating layer 106 and the second interlayer insulating layer 114, the oxide layer thickness of the portion where the overlay key is formed is increased. It is reduced to about 10000Å. Therefore, the light transmitted through the oxide layer 114 under the photoresist pattern 116 is reflected from the reflective film 112b instead of the silicon substrate 100, and then comes out toward the photoresist pattern 116. By reducing the reflection path of the light passing through), it is possible to prevent the size of the overlay key from changing.

Subsequently, although not shown, a second via hole exposing the surface of the second metal wiring 112a is formed by etching the second interlayer insulating layer 114 using the photoresist pattern 116 as a mask. A metal such as tungsten is deposited on top of the resultant by chemical vapor deposition (CVD), and the tungsten layer is etched by chemical mechanical polishing (CMP) until the surface of the second interlayer insulating layer 114 is exposed. A second via plug is formed in the via hole. Subsequently, a metal, such as aluminum, is deposited on the resultant by sputtering to deposit a third metal layer, and a third capping layer made of titanium (Ti) / titanium nitride (TiN) is deposited thereon. The third capping layer and the third metal layer may be patterned by a photolithography process to form a third metal interconnect electrically connected to the second metal interconnect 112a through the second via plug.

In the above-described embodiment, a method of preventing a change in the size of the overlay key formed in the scribe line region is illustrated, but the present invention can be applied to a pattern having a size of 2 μm or more formed in the memory cell region.

As described above, according to the present invention, a reflective film is formed on a portion where a large pattern having a pattern size of 2 μm or more, such as an overlay key or an alignment key, is to be formed in advance, thereby reducing the thickness of the insulating layer on the pattern forming portion. Therefore, the size of the pattern may be prevented by reducing the path of the defocus image transmitted through the insulating layer under the photoresist pattern and then reflected and transferred to the photoresist pattern during the photolithography process.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (3)

In the manufacturing method of the semiconductor device which forms the pattern which has a magnitude | size of 2 micrometers or more in the upper part of the semiconductor substrate in which an insulating layer is laminated | stacked, And forming a reflective film on a portion where the pattern is to be formed before the forming of the pattern, thereby preventing a change in size of the pattern. The method of manufacturing a semiconductor device according to claim 1, wherein the reflective film is formed of metal or polysilicon. The semiconductor device manufacturing method according to claim 1, wherein the reflective film is formed so that the thickness of the insulating layer is 10000 kPa or less.