KR20010047195A - Control Circuit of Fuse Information having Reduced Circuit Size - Google Patents

Abstract

PURPOSE: A fuse information control circuit is provided to reduce a space required in wiring to select a fuse information or a register information. CONSTITUTION: The circuit includes a fuse cell array comprising fuse cells(32a-32n) and a fuse input signal selection part(30). The fuse input signal selection part outputs a fuse information activation signal(VCCHB) as a fuse information control signal(VCCHBi), or outputs a fuse disable signal(F_DIS) as the fuse information control signal, according to the state of the fuse information activation signal. The fuse information activation signal is varied according to the increase of power supply voltage(VCC). The fuse cells generate fuse information as output signals(Fout_0-Fout_n) in response to the fuse information control signal, or generate a fuse register information(fuse_r) as the output signals. The fuse register information indicates the values(Reg_0-Reg_n) of registers which are set to control fuses.

Description

Fuse information control circuit that can reduce the circuit area {Control Circuit of Fuse Information having Reduced Circuit Size}

The present invention relates to a fuse information control circuit, and more particularly, to a fuse information control circuit that can reduce the circuit area.

In general, when it is difficult to predict the result at the time of circuit design, a method of changing the circuit structure of the semiconductor device in which the process is completed by using a fuse (FUSE) is widely used. In addition, a method of controlling a circuit structure using a register can be said to be one of general methods. However, in the case of using a fuse, once the fuse is blown, there is a disadvantage that it cannot be returned to its previous state. In addition, in the case of using a register, it is easy to change the circuit structure, but it is troublesome to input information necessary for the register in advance every time the device is operated. Thus, as shown in FIG. 1, the disadvantages of the above two methods can be compensated for by using a method that enables register operation only when necessary.

FIG. 1 is a block diagram illustrating a conventional fuse information control circuit, and is implemented as a fuse cell array including fuse cells 0 10a to 10 n.

Each fuse cell 10a to 10n illustrated in FIG. 1 includes a fuse information activation signal VCCHB, a register value Reg_0 to Reg_n, and a selection control signal applied from external registers 0 to n. Inputs mux_ctrl and selectively outputs fuse information or fuse register information in response to the selection control signal Mux_ctrl.

FIG. 2 is a circuit diagram illustrating each of the fuse cells 10a to 10n of the fuse information control circuit shown in FIG. 1 and includes a PMOS transistor MP21, a fuse F20, an NMOS transistor MN21, a latch 23, An inverter 24, a multiplexer 26 and an inverter 28 are included. Here, each fuse cell of FIG. 1 has the same structure as the circuit shown in FIG.

That is, the circuit of FIG. 2 is a circuit for determining whether the fuse is blown, and the voltage of the first node N1, that is, the fuse information, becomes a low level when the fuse F20 is blown. High level. In addition, the circuit of FIG. 2 uses a separate selection control signal Mux_ctrl in order to arbitrarily adjust the state of the output signal Fout when the fuse is blown or not blown. Select the information. To this end, each fuse cell must be supplied with a selection control signal Mux_ctrl.

As described above, the conventional fuse information control circuit requires a wiring WIRING in each fuse cell in order to receive the selection control signal Mux_ctrl, which requires a large amount of space in the circuit area.

An object of the present invention is to provide a fuse information control circuit that can reduce the space required for wiring for selecting fuse information or register information.

1 is a block diagram illustrating a conventional fuse information control circuit.

FIG. 2 is a circuit diagram illustrating a fuse cell of the circuit illustrated in FIG. 1.

3 is a block diagram illustrating a fuse information control circuit capable of reducing a circuit area according to an exemplary embodiment of the present invention.

4 is a detailed circuit diagram illustrating a fuse input signal selector of the circuit of FIG. 3.

FIG. 5 is a diagram for describing a relationship between a fuse information activation signal and a power supply voltage in the circuit shown in FIG. 4.

FIG. 6 is a detailed circuit diagram illustrating a fuse cell of the circuit illustrated in FIG. 3.

In order to achieve the above object, the fuse information control circuit can reduce the circuit area according to the present invention, according to the state of the fuse information activation signal (VCCHB) applied from the outside, select the fuse information activation signal (the fuse information control signal ( Fuse information or fuse in response to a fuse input control signal output from the fuse input signal selector and a fuse input signal selector which output as VCCHBi or select a predetermined fuse disable signal and output as a fuse information control signal VCCHBi. It is preferable that the fuse cell array is composed of a plurality of fuse cells that generate register information as an output signal.

Hereinafter, a fuse information control circuit capable of reducing a circuit area according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a fuse information control circuit capable of reducing a circuit area according to an exemplary embodiment of the present invention, wherein a fuse cell array including fuse cells 0 to fuse cells N (32a to 32n) and a fuse input signal selection unit are shown. (30).

The fuse input signal selection unit 30 selects the fuse information activation signal VCCHB and outputs the fuse information control signal VCCHBi according to the state of the fuse information activation signal VCCHB applied from the outside, or the predetermined fuse display. The enable signal F_DIS is selected and output as the fuse information control signal VCCHBi. Here, the fuse information activation signal VCCHB is a signal that is changed according to the increase of the power supply voltage VCC. Keep your level. As described above, the fuse information control signal VCCHBi may be output as it is or the fuse disable signal F_DIS may be output.

Fuse cells 0 to fuse cells 32a to 32n generate fuse information as output signals Fout_0 to Fout_n in response to the fuse information control signal VCCHBi output from the fuse input signal selector 30 or fuse registers. Information fuse_r is generated as output signals Fout_0 to Fout_n. Here, the fuse register information fuse_r represents values Reg_0 to Reg_n of registers 0 to n (not shown), which represent values set for fuse control.

FIG. 4 is a circuit diagram illustrating the fuse input signal selector 30 of the circuit shown in FIG. 3. Referring to FIG. 4, the fuse input signal selector 30 includes an inverter 42, a PMOS transistor MP41, and a transfer gate TG41.

The inverter 42 inverts the fuse information activation signal VCCHB and applies the inverted signal as a control signal of the PMOS transistor MP41 and the transfer gate TG41, respectively.

The PMOS transistor MP41 serves as the first transfer means, and outputs the fuse information activation signal VCCHB as the fuse information control signal VCCHBi in response to the fuse information activation signal VCCHB inverted in the inverter 42. do. Here, the first transfer means may be implemented as a transmission gate in addition to the PMOS transistor MP41. In this case, VCCHB may be applied to the NMOS transistor side of the transfer gate.

In addition, the transmission gate TG41 serves as the second transfer means, and in response to the fuse information activation signal VCCHB and the inverted fuse information activation signal, the transfer gate TG41 transmits the fuse disable signal F_DIS to the fuse information control signal VCCHBi. Output as. Here, the second transfer means may be implemented as one PMOS transistor or NMOS transistor instead of the transmission gate.

In FIG. 4, the fuse information activation signal VCCHB is an input signal for reading fuse information, and the fuse disable signal F_DIS may be defined as a signal for controlling the output of the fuse information. In addition, the fuse disable signal F_DIS may use the selection control signal Mux_ctrl which has been used in the past.

In addition, in the present invention, the fuse input signal selector 30 may be implemented to control the output of one fuse cell, and may be implemented to control the output of a plurality of fuse cells.

FIG. 5 is a diagram illustrating a relationship between a fuse information activation signal VCCHB and a power supply voltage VCC of the circuit illustrated in FIG. 4. The fuse information activation signal VCCHB gradually increases as the power supply voltage VCC is initially supplied and increased, and then becomes low when the power supply voltage reaches a stable state. That is, the VCCHB has a different level in the period in which the power supply voltage VCC increases and in a stable state.

That is, referring to FIG. 5, the fuse input signal selector 30 outputs the VCCHB as VCCHBi while the PMOS transistor MP41 is turned on while the VCCHB is at a high level. However, when the fuse information activation signal VCCHB is at a low level, the transfer gate TG41 is turned on to output the fuse disable signal F_DIS as VCCHBi. Accordingly, in the section before the power supply voltage VCC is applied and stabilized, that is, in the section T61 during the initial start-up, the VCCHB becomes VCCHBi as shown in FIG. 5, and in the stable state T62, the fuse discharge is performed. It can be seen that the enable signal F_DIS becomes VCCHBi.

FIG. 6 is a detailed circuit diagram illustrating each of the fuse cells 32a to 32n of the circuit shown in FIG. 3, and includes a PMOS transistor MP61, a fuse F60, a latch 61, a noah gate 65, and an inverter. 67).

Referring to FIG. 6, the gate of the PMOS transistor MP61 is connected to the fuse information control signal VCCHBi output from the fuse input signal selector 30, the source is connected to the power supply voltage VDD, and the drain is a fuse. It is connected to one side of (F60). A gate of the NMOS transistor MN61 is connected to the fuse information control signal VCCHBi, a drain is connected to the other side of the fuse F60, that is, the first node N1, and a source is connected to the reference potential VSS.

The latch 61 latches the voltage of the first node N1 as fuse information in response to the fuse information control signal VCCHBi. To this end, the latch 61 includes an NMOS transistor MN62 and a NOR gate 63. Here, the NMOS transistor MN62 and the NOR gate 63 form a feedback loop. The NOR gate 63 inverts the OR of the fuse information control signal VCCHBi and the signal of the first node N1, and outputs the result of the inverted AND. In addition, the NMOS transistor MN62 latches the voltage of the first node N1 by the output signal of the NOR gate 63.

The NOR gate 65 inverts the OR of the output signal of the latch 61 and the fuse register information fuse_r, and outputs the result of the inverted AND. The inverter 67 inverts the output signal of the NOR gate 65 and generates the output signal Fout as a result of the inversion.

3 to 6 will be described in detail the operation of the fuse information control circuit according to the present invention.

First, in the start-up period T61 where the power supply voltage VCC is initially applied, the VCCHB also rises while the power supply voltage VCC rises to the logic dress hold. At this time, in the fuse input signal selector 30 of FIG. 4, the PMOS transistor MP41 is turned on by the fuse information activation signal VCCHB to bring the VCCHBi to a high level. Here, the high level VCCHBi is applied to the inputs of the fuse cells 32a to 32n to turn on the NMOS transistor MN61. That is, the fuse information stored in the first node N1 is read while the VCCHBi increases, and when the VCCHBi transitions to the low level, the fuse cells 32a to 32n store the read information in the latch 61.

That is, the low level of the fuse information control signal VCCHBi indicates a state in which the VCCHB is low level, and the VCCHBi at this time indicates a low level fuse disable signal F_DIS that is not yet activated.

For example, when the fuse F60 is not blown, when the VCCHBi becomes low, the PMOS transistor MP61 is turned on so that the fuse information stored in the first node N1 transitions from the low level to the high level. . Thus, the output signal of the NOR gate 63 goes low and the NMOS transistor MN62 is turned off. Accordingly, the fuse information of the first node N1 is maintained at the high level by the latch 61 of the feedback loop structure.

In addition, when the fuse F60 is blown, when the VCCHBi is at the low level, the NMOS transistor MN61 is turned off, so that the first node N1 maintains the previous level. At this time, the output signal of the NOR gate 63 becomes a high level, and the NMOS transistor MN62 of the latch 61 is turned on by the high level output signal. Therefore, the fuse information of the first node N1 may be maintained at a high level.

As described above, the fuse information stored by the latch 61, that is, whether the fuse F60 is blown or not blown, can be obtained by referring to FIG. 5 after the VCCHB transitions to the low level. And an output signal Fout of the fuse cell via the inverter 67.

In addition, referring to FIG. 4, when the VCCHB is at a low level, the fuse input signal selector 30 receives the fuse disable signal F_DIS. That is, when the fuse disable signal F_DIS is activated to a high level, the VCCHBi output from the fuse input signal selector 30 of FIG. 4 becomes a high level again. Therefore, when VCCHBi becomes high level, the fuse information read from the fuse cells 32a to 32n is ignored, and the fuse register information fuse_r is generated as the output signal Fout.

If the fuse disable signal F_DIS is not activated at the high level when the fuse F60 is blown, the output signal of the NOR gate 63 is always at the high level and the output signal is turned on. (Fout) always goes high. However, in the present invention, the output signal Fout can be arbitrarily adjusted even when the fuse is blown by adjusting the VCCHBi by the VCCHB and the fuse disable signal F_DIS. In other words, if a desired input signal is applied using the fuse register information fuse_r, two effects may be obtained in a case where the fuse is blown or not blown.

In addition, in the present invention, the fuse disable signal F_DIS, which performs the same function as the conventional selection control signal Mux_ctrl, is applied only to the fuse input signal selector 30 and to the remaining fuse cells 32a to 32n. The advantage is that you don't have to.

According to the present invention, since the wiring of the signal can be reduced by not applying the selection control signal applied to each fuse cell in the related art, the circuit size can be reduced by saving the space required for the wiring during circuit design. have.

Claims (3)

According to the state of the fuse information activation signal VCCHB applied from the outside, the fuse information activation signal is selected and output as the fuse information control signal VCCHBi, or a predetermined fuse disable signal is selected to select the fuse information control signal ( A fuse input signal selector for outputting as VCCHBi); And A fuse cell array including a plurality of fuse cells configured to generate fuse information or fuse register information as an output signal in response to the fuse information control signal output from the fuse input signal selection unit; And the fuse information indicates a connection state of the fuse, and the fuse register information indicates a register value for controlling the fuse. The method of claim 1, wherein the fuse input signal selector, First transmitting means which is turned on in response to the fuse information activation signal and outputs the fuse information activation signal as the fuse information control signal; And And second transmission means which is turned on in response to the fuse information activation signal and outputs the fuse disable signal as the fuse information control signal. The method of claim 2, Each fuse cell of the fuse cell array, A first transistor having a gate connected to the fuse information control signal and a source connected to a power supply voltage; A fuse having one side connected to the drain of the first transistor and the other side connected to the first node; A second transistor having a drain connected to the first node, a fuse information control signal connected to a gate, and a reference potential connected to a source; Latch means for latching a signal of the first node as the fuse information in response to the fuse information control signal; Logical combining means for logically combining the output signal of the latching means and the fuse register information and outputting the logical combined result; And And an inverter for inverting an output signal of said logic combining means and generating said inverted result as said output signal.