KR20010041306A - Full and half-rate signal space detection for channels with a time-varying mtr - Google Patents

Abstract

The detector 400 of the present invention is provided for detecting a data value with a sampled data signal to provide temporarily separated data samples. The first detector base (462, 452, 458) is configured to determine the position of the first sample vector of the first signal space. The second detector section (454, 456, 460) is configured to determine the position of the second sample vector of the second signal space. The second detector section uses a logic statement to determine the position to couple the plurality of position indicators. Each position indicator provides a position of a second sample vector associated with each interface. The type of the logic statement is independent of the value of the position indicator. Also, the above location indicator is independent of all other location indicators.

Description

RATE SIGNAL SPACE DETECTION FOR CHANNELS WITH A TIME-VARYING MTR FOR A CHANNEL WITH TIME VARIABLE MTR < RTI ID = 0.0 >

A typical disk drive includes one or more disks mounted for rotation on a hub or spindle. A typical disc drive also includes a transducer supported by a hydro-dynamic air bearing that flares each disc. Both transducers and hydro dynamic air bearings are referred to as data heads. The drive controller is typically used to control the disk drive based on commands received from the host system. The drive controller retrieves information from the disc and controls the disc drive to store information from the disc.

In a typical disk drive, the electromechanical actuator is implemented in a negative feedback, closed loop servo system. The actuator moves the data head radially on the disk surface for a track seek operation and holds the transducer directly on the track on the disk surface to track the next operation.

Information is typically stored on a circular track on the surface of the disc by supplying a write signal to the data head to record information on the surface of the disc representing the data to be stored. In retrieving data from a disk, the drive controller controls the electromechanical actuator to generate a read signal, the data head flying on the disk and based on information stored on the disk. The read signal is typically decoded after conditioning the drive controller to recover the data.

Typical read channels include data heads, preconditioning logic (such as preamplifier and filter circuits), data detectors and recovery circuits, and error detection and correction circuits. The read channel is typically executed in a drive controller associated with the disk drive.

In a disk drive, it is important that the error rate (bit error rate) with respect to the number of bits is maintained at a relatively low level. To improve the bit error rate on the disk drive, or to increase the linear recording density of the disk drive, a maximum similarity sequence detection (MLSD) method is required. The above method can be performed using a known Viterbi algorithm. However, implementing the MLSD method directly is very costly. For example, the channel response following forward filtering is typically very long and will include more than 10 terms. Therefore, the Viterbi detector requires a 2 ^10-1 state, which is unrealistically complex. Therefore, other techniques have been explored to reduce this complexity and provide results using direct MLSD methods.

The above technique uses a Viterbi algorithm to cancel the terms with feedback and reduce the number of terms. For example, the Viterbi detector can only have four states by canceling the rest (including the main cursor) in addition to the two terms. The detector is referred to as a reduced state sequence predictor (RSSE).

Other techniques may select a channel response target that is preferably a white target but has a small number of terms. In the above system, the partial response (PR) target has been improved. One of the above targets is referred to as an enhanced extended partial response maximum similarity (E ² PRML) target. At high recording densities, the major error event (the difference between the two input sequences) encountered by the detector using the partial response target for a particular higher order partial response channel (E ² PRML) is typically +/- (2, - 2,2). The above error typically occurs when a tribit is shifted by one sample time or a quad bit is misinterpreted as a die bit, and vice versa. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and provides advantages different from the prior art.

The present invention relates to a disk drive, and more particularly to a data detector of a disk drive in which a data detector detects data encoded according to a code having a time variable constraint.

1 is a cross-sectional view of a disk drive in which an upper casing is removed, according to an embodiment of the present invention.

2 is a high level block diagram of the disk drive shown in FIG.

3 is a schematic diagram showing a magnetic channel and a corresponding readout circuit for more detailed illustration.

4-1 and 4-2 show positions of symbols corresponding to detectors according to one aspect of the present invention.

Figures 5-1 and 5-2 are waveforms illustrating major error events for a high density MLSD.

6 is a block diagram illustrating the detector structure of a detector according to an aspect of the present invention.

Figures 7-1 and 7-2 are views of an FTDS / DF tree for explaining the operation of the detector according to one aspect of the present invention.

8 is a block diagram illustrating the structure of one embodiment of the 3D / 4D signal space detector of the present invention.

9 is a block diagram illustrating the structure of one embodiment of the half-rate 3D / 4D signal space detector of the present invention.

A relatively new class of code has recently been investigated. The above code is based on the proposed maximum transition behavior (MTR) in a way that removes the major error in a higher order partial response channel, such as a higher density maximum likelihood sequence detector (MLSD) or enhanced extended partial response maximum similarity (E ² PRML) . The MTR code operates to reduce the minimum euclidean distance between the data samples of the magnetic recording channel.

For example, the MTR = 2 code limits the continuous transition operation of the write current to two. In essence, the MTR = 2 code removes the encoded data of all patterns including two or more consecutive transitions. As a result, the MTR = 2 code removes all patterns that cause major error events for MLSD detectors with high recording density and higher order PR channels.

Using the MTR constraint, one detector, referred to as a 3D-110 detector, is implemented and its performance is determined by a delay tree search fixed with a decision feedback (FDTS / DF (2)) of depth 2 at a high symbol density It is comparable. The detector consists of considering the vectors of the three received samples in a three-dimensional space. The three plane boundaries are computed and used to divide the signal space into two regions, each of which corresponds to determining +1 or -1 for the currently processed bit. The 3D-110 detector also includes a forward filter that removes the precursor inter-symbol interference (ISI) term, the two post-cursor ISI terms must be 1 and 0, and the cursor also returns 1. A feedback filter is executed that removes all but the rest of the two postcursor ISI terms. Therefore, the same discrete time channel pulse response can be represented as 110 without conveying an error through the detector. The above constraint on the channel response is used to simplify the detector structure.

While the magnetic channel natural response approaches 110 targets at high recording densities, it deviates significantly from 110 targets at low recording densities. Therefore, constraining the pulse response for the particular 110 target results in a reduction in performance compared to FDTS / DF (2) at low recording densities. Even at high densities, the performance of the actual elements of the detector can also change the channel response from the 110 target. For example, a finite impulse response (FIR) filter of limited length may be used to cause such variations.

Thus, while 3D-110 channels provide significant advantages in performance and / or simplicity for other detectors (more complex FTDS / DF (2) detectors), they include the above-mentioned disadvantages.

The present invention relates to a system for handling the above problems and providing other advantages.

The detector of the present invention is provided to detect a data value in a sampled data signal to provide temporarily separated data samples. The first detector portion is configured to determine the position of the first sample vector in the space of the first signal. The second detector portion is configured to determine the position of the second sample vector in the space of the second signal. The second detector portion uses a logic statement to determine its position to couple multiple position indicators. Each location indicator provides the location of a second sample vector associated with an individual boundary surface. The type of the logic statement is independent of the value of the position indicator. Also, each position indicator is independent of all other position indicators.

Referring to Figure 1, a rotatable disk drive system suitable for incorporating the teachings of the present invention is referenced 110 in schematic form. A plurality of information storage disks 112 are journaled around the spindle motor assembly 114 in the housing 116. [ Each disk 112 has a plurality of concentric circular recording tracks, each represented schematically 118 for recording information. Each track 118 is subdivided into a number of sectors, denoted 120. The data may be stored in or retrieved from the disc 112 with reference to a particular track 118 and sector 120. The actuator arm assembly 122 is preferably rotationally mounted at the corner of the housing 116. Actuator arm assembly 122 includes a head gimbal assembly 122 that carries a slider 125 or transducer 126 having a read / write head for reading and writing information to and from disk 112, respectively Carry. The voice coil motor 128 is configured to precisely rotate the actuator arm assembly 122 back and forth so that the transducer 126 moves on the disk 112 along the arc 130. The control circuit 132 controls the position of the transducer 126 and processes information to retrieve it from the disc 112 or write it to the disc 112.

2 shows a high-level block diagram of the control circuit 132 of the disk drive system 110. In FIG. The microcontroller 134 directly executes all the main functions of the disk drive system 110. The read / write support and interface control circuitry is represented by 136 and the motor and actuator controller 138 is connected to the microcontroller 134 by common data, address, and control bus 140. The general circuitry 136 provides a hardware interface between the disk drive system 110 and the host computer system (not shown) via the communication bus 142. The general circuit 136 also provides an interface between the motor and actuator controller 138 and the read / long channel 144. The read / write channel 144 receives the signal of the preamplifier 143 that receives the signal of the transducer 126. The read / write channel 144 operates as an interface between the microcontroller 134 and the transducer 126 via line 145. The read / write channel 144 also provides a signal for the line 146 to the motor and the actuator controller 138. The controller 138 provides as an interface between the microcontroller 134 and the motor assembly 114 via line 148 and through the line 150 as an interface between the microcontroller 134 and the actuator arm assembly 122 do.

3 is a schematic diagram of the magnetic channel 160 and the read channel block 162 and is provided for a better understanding of the notation used. The channel 160 includes a recording medium such as a disk 112 and a transducer 126 as is well known. The read channel block 162 includes an adder 164, a front filter 166, a sampler 186, a forward filter 168, an adder 170, a detector 172 and a feedback filter 174. The read channel block 162 is generally implemented in the read / write channel 144 shown in FIG. The input 176 to the magnetic channel 166 is preferably a sequence of data bits, and the data bits for the current time _k are represented by a _k . According to one aspect of the present invention, the sequence of input bits is preferably encoded according to a code that implements an MTR = 2 code constraint, wherein the bits are represented by a transition of zero, and a zero value is represented by a non- (NRZI) format.

When the data bit is read from the magnetic channel, the data bit is provided as the readback signal 178. The readback signal 178 is typically corrupted by the noise 180 represented by n (t) added to the readback signal 178 by the adder 164. The noise n (t) and the adder 164 appear only as representatives of the noise that damages the readback signal 178 and are therefore not part of the actual hardware implementation. The noise n (t) impairs the feedback signal 178 to form a damaged read signal 182.

The damaged read signal 182 is provided to the front filter 156. The front filter 156 prevents aliasing as an example and filters the high frequency noise and provides a filtered output 184 to the sampler 186. The sampler 186 samples the filtered output 184 and may be implemented as an analog to digital converter. The sampling signal generated by the sampler 186 is supplied to a forward filter 168.

The forward filter 168 is preferably operated alone or combined with other filtering to light the noise of the readback signal and supply the modified readback signal 188 (also designated as r _k ) to the adder 170. An example of the forward filter 168 is a finite impulse response (FIR) filter that includes multiple taps. The forward filter 168 removes all precursor inter symbol interface (ISI) terms. The post-cursor ISI term is allowed to be a natural value, since no constraint applies to the channel coefficients. The detector 172 is arranged to output a sequence 190 Quot;).

Print Is an estimate of the input data sequence. Print Is also provided to feedback filter 174, which is used to provide feedback signal 192 to adder 170. [ The feedback signal 192 is added to the output r _k by the forward filter 168. The combination of the signals is provided to the decision unit 172 at the output 194 (also designated y _k ) of the adder 170. In one embodiment of the present invention, the feedback filter 174 is for removing all but two post-cursor ISI terms. In another embodiment, it is intended to remove all but three post-cursor ISI terms.

For a feedback filter that removes all but two post-cursor terms, assuming that all of the previous decisions made by decision unit 172 are correct, the same discrete-time channel response includes three terms (1, f ₁ , f ₂ ).

Therefore, at time k, the noise-free input (y _k ) for the decision device 172 can be described as follows.

Equation 1; y _k = a _k + f ₁ a _k-1 + f ₂ a _k-2

Where a _k is the input data at time k.

The 3D signal space detector (3D-SSD) can be implemented by first considering the symbol positions of the three-dimensional space. As described in detail below, the detector maps all possible symbols representing an input data sequence to a three-dimensional space. A detector obtains a sample vector comprising a contribution from a plurality of input samples formed respectively from a plurality of terms representing input data samples of the input sample sequence. The sample vectors are mapped to the same position in the three-dimensional space. The detector then determines, at each time point, which of the three dimensional space and which data sampler is closest to the sample vector. This is similar to determining a path that corresponds to a minimum Euclidean distance between a desired sample value and an observed value for a fixed delay detector, such as an FDTS / DF detector, or a 6 sample look-ahead head partial response channel. The partial response channel is described in Patel, Rutledge et al., &Quot; Perofrmance Data For Six Sample Look-Ahead 1,7 ML Detection Channel ", IEEE Trans. Magn. Vol. 29, No. 6, pp. 4012-4014 and Yamasaki et al., "A 1, 7 Code EEPR4 Read Channel IC with Analog Noise Whitened Detector", PROC. of ISSCC, 1997, pp. 316-317.

Each pair of possible symbols indicating different detector determinations must be separated by an interface. The plane boundary is combined by a logic rule such that the signal space is divided into two regions, one corresponding to a detector decision of +1 and the other corresponding to a detector decision of -1. As the sample vector falls into a three-dimensional vector associated with the interface, the binary decision is based on the detector output And is released by the detector 172 in accordance with the detection signal. Also as discussed below, the detector structure can be simplified by eliminating redundant planes and eliminating each symbol farther than the minimum Euclidian distance associated with the code.

Figures 4-1 and 4-2 illustrate a vector space for a detector that analyzes an input sequence with three terms including a sample vector known as an observation vector. More specifically Figures 4-1 and 4-2 also include three axes y " _k-2 (also designated by numeral 204). Axis y " _k-2 extends into and out of the plane of the paper including Figs. 4-1 and 4-2.

The one symbol is removed based on the MTR constraint and all possible residual symbols, all possible residual symbols representing the three dimensional observation vector, and are mapped to the positions shown in Figures 4-1 and 4-2. The planar boundary is configured to divide the symbols of the three-dimensional space defined by the location. The observation vector is mapped to the location, and the detector provides a determination based on where the observation vector belongs to the location associated with the planar boundary.

The axis of the position is defined as follows.

Equation 2; y _k = a _k + f ₁ a _k-1 + f ₂ ak-2

Equation 3; y _k-1 = a _k-1 + f ₁ a _k-2

Equation 4; y " _k-2 = a _k-2

Where y'k-1 and y " k-2 are generally canceled available past decisions (i.e., and And the detector input at time k-1 and time k-2 with inter-symbol interference due to the decision on the time k-2. Since the detector processes the three input samples as the observation vector, the detector must determine for input bit a _k-2 at each time k in the detection process (i. E. The input bit, which is the two time intervals previously received) .

Table 1

Table 1 shows all possible input sequences that can be represented by an observation vector. Table 1 includes an index referring to index numbers 0-7 corresponding to 2n (n = 3) possible symbols. Table 1 also provides an equation of y _k , y ' _k-1 and y " _k-2 , including possible symbols recorded at the terms ak-2, ak-1 and ak, do.

Figures 5-1 and 5-2 show waveforms 206,208, 210, and 212 showing the major error events observed for the MLSD detector at the high density and high order partial response targets. In FIG. 5-1, the error event is generated when the tri-bit waveform 206 is shifted one time interval to produce the shifted tri-bit 208. The error event in Figure 5-2 is generated when quad bit waveform 210 is detected as die bit waveform 212 and vice versa.

In order to eliminate the above main error event, the input data is preferably encoded according to the MTR = 2 constraint rejecting the tri-bit. Therefore, in Table 1, either symbol 2 or symbol 5 , Since these symbols indicate the presence of a tribit. For example, = + 1, then symbol 5 corresponds to a sequence of input bits of type (+1, -1, +1, -1) containing three consecutive transitions and should be removed. For the same reason, = -1, then symbol 2 should be removed.

The location of Figure 4-1 Lt; RTI ID = 0.0 > mapped < / RTI > Symbol 2 is mapped to the position shown in FIG. 4-1. Obviously, the position shown in Figure 4-2 = ≪ RTI ID = 0.0 > + 1 < / RTI > Symbol 5 is removed.

y "k-1 = +1 and -1 are represented by x's and 0's, respectively.

Figures 4-1 and 4-2 also show the slicer planes A, B, C and D used to partition the various symbols mapped to the position. Four slicer planes are used first. However, to simplify the detector structure as described above, the number of planes is limited to three (e.g., planes C, D are combined to form a new plane E). To further simplify the detector structure, the direction of the plane is limited.

Plane A is provided to separate symbols 0 and 4 (symbols 1 and 5 in Figure 4-1). In the case of an optimal detector, the crystal boundary is a plane bisecting a line connecting the separated symbol pairs. However, the system is simply limited, not in the three-dimensional space, but in the plane to separate the projection from the space. The above constraint is implemented by selecting the two contribution tables that contribute the best to the distance between two symbols. y " _k-2 coordinate is kept continuously because two symbols corresponding to different crystals in the input bit a _k-2 are easily separated for this axis. Of the remaining two coordinates (except for very low symbol densities) The y ' _k-1 coordinate further contributes to the distance between symbols 0 and 4 than the y _k coordinate, so the symbol is projected onto the y'k-1, y "k-2 surface. Slicer plane A is limited to rotate in the vertical _{y 'k-1 y "k} -2 surface.

The projection of the plane A to the selected surface is represented by a line whose direction changes as the slider plane can rotate. All points of the lie have the same distance from the symbol of the projected pair.

In Table 1, the coordinates of the projections of symbols 0 and 4 on the surface of y ' _k-1 y " _k-2 are given by (1 + f ₁ , +1) and (1-f ₁ , -1) The equation of A can be obtained as follows.

Equation 5; (y ' _k-1 - (-1 + f ₁ )) ² + (y " _k-2 - 1) ²

= (y ' _k-1 - (1 - f ₁ )) ² + (y " _k-2 + 1) ²

The above expression is simplified as follows.

Equation 6; _{y "k-2 + f 1} y 'k-1 -f 1 = 0

Using a similar procedure, the equation for slicer plane B separating symbols 3 and 7 (and also symbols 2 and 6 in FIG. 4-2) can be expressed as:

Equation 7; _{y "k-2 + f 1} y 'k-1 + f 1 = 0

From here = -1, and plane C separates symbols 3 and 5. Plane C is limited to only rotating perpendicular to y _k y " _k-2 , since the coordinates contributing to the intersymbol distance are the coordinates corresponding to y _k and y" _k-2 axes. The plane equation is derived by finding a line bisecting the projections of the two symbols to the yky " k-2 surface.

The above operation = + 1, it is repeated for the plane D separating the symbols 2 and 4.

The above procedure yields the following four position identification equations.

Equation 8; _{A: sgn (y "k-} 2 + f 1 y 'k-1 - f 1)

Equation 9; _{B: sgn (y "k-} 2 + f 1 y 'k-1 + f 1)

Equation 10;

From here to be.

Equation 11;

From here to be.

The position identification equations C and D are also combined to yield

Equation 12;

Equation 12 is further simplified by the setting (f ₁ -f ₂ ) = 1. This simplification negatively affects the detector performance because the two symbols separated by the plane at the main low channel density are farther apart than separated by the planes A and B. [ Therefore, small changes in direction and position on the plane do not affect the relative positions of the received samples associated with the plane. Therefore, Equation 12 can be simplified as follows.

Equation 13;

By subtracting y'k-1 and y " k-2 from equations 3 and 4, the following relationship is obtained for the three position identifications.

Equation 14;

Equation 15;

Equation 16;

Here, DELTA A, DELTA B and DELTA E are offset values as follows.

Equation 17;

Equation 18;

Equation 19;

In general, the offset value is implemented as a short FIR filter with a binary input, two input multiplexers or a look-up table.

The decision logic can be implemented by moving the test points through the three dimensional signal space and recording the relative positions of the points associated with the plane. The corresponding detector output is obtained by finding the closest symbol at the location for the test point. Logic rules or statements are obtained in combination with cases that result in the same output decision from the detector. However, in the case of the above three-dimensional case logic rules can be simply obtained by inspection. By mapping the boundary decision from -1 to 0, the logic rule can be expressed as:

Equation 20;

Where " · " represents a logic AND operation, and " + " represents a logic OR operation.

Figure 6 is a structural block diagram illustrating a 3D-SSD detector 214 in accordance with an aspect of the present invention. The detector 214 includes delay operators 216 and 218, a multiplier 220, adders 222, 224 and 226, slicers 228, 230 and 234, an AND circuit 236 and an OR circuit 238. As shown in FIG. 6, y _k is provided to a delay operator 216 that provides y _k-1 at output 240. The term is provided to a delay operator 218 that provides y _k-2 at its output 242. The multiplier 220 receives f ₁ at its input 244. The addition circuit 222 receives the offset value (ΔE) from the input 246 from the input unit 244, and receives a y _k and y _k-2 at the other two inputs. The adder circuit 226 receives the offset A at the first input 252 and receives the output 250 of the multiplier 220 and y _k-2 of the delay operator 218 at the other input. The outputs of the adder circuits 222, 224, and 226 are provided to the slicers 228, 230, and 234, respectively. The outputs 229, 231, 235 of the slicers 228, 230, 234 are directed to circuits 236, 238 as shown.

The output 256 of the circuit 238 Lt; / RTI > Therefore, the detector 214 uses one multiplier, three slicers, three adders, and three two-input multiplexers. A similar 3D-110 detector can be implemented using three slicers, three adders and a two-input multiplexer.

The detector 214 is configured to have the advantage that at each time only one of the two symbols 2 and 5 of Table 1 is provided at the signal space location. This is because the MTR = 2 code removes one of the two symbols.

However, the major error events associated with Figures 5-1 and 5-2 may be eliminated using time varying transition behavior constraints. The above constraint allows a tribit, but it can be started at a predetermined interval. In one embodiment, the time varying transition behavior constraint allows the tri-bit to start only at times of other (e.g., even or odd) numbers.

A relaxed constraint of this type enables the development of code with a high ratio. Hence, in the case of a time variable MTR code, it can have both symbols 2 and 5 provided at the signal position every other time. In order to implement the 3D detector according to the invention, a change must be made to accommodate the change in the code constraint.

To better understand the changes needed to detect encoded data according to a code having a time variable code constraint, a signal space detector according to the present invention can be understood with reference to a FDTS / DF tree of depth 2. Figure 7-1 shows a tree 280 with a root starting at an odd number of time intervals k-3 (designated 282). Figure 7-2 shows a tree 284 with a root starting at an even number of time intervals k-3 (designated 286).

The present invention proceeds under the assumption that a tribit is possible at even times. While the root of the tree 280,284 shows the value of a _k-3 , the next branch going from left to right along the tree returns the sample values a _k-2 , a _k-1 , a _k, and a _{k +} Respectively. The corresponding time interval is shown along the bottom of each tree and is represented by 288, 290, 292, 294 in Figures 7-1, 296, 298, 300, 302 in Figure 7-2.

Looking at trees 280 and 284, one can see that either path 2 or path 5 is rejected because it violates code constraints. For example, in Figure 7-1, path 5 concludes from the tree because it releases the tri-bit patterns (+ 1, -1, + 1, -1) starting at even time intervals. Therefore, while the route corresponds to an even number of time intervals, the state is equal to MTR = 2 of the previously described detector. On the other hand, as shown in FIG. 7-2, both branches 2 and 5 are allowed while the route corresponds to an odd time interval (while the tri-bit is allowed to start in an odd time interval).

To realize the coding gain for FDTS / DF (2) with time varying MTR codes, the suspicious path can be removed at even times and stored every moment. However, the presence of paths 2 and 5 increases the chance of a wrong section of the selected tree 280 or 284. In fact, as the user density increases, the above error begins and becomes very large, thereby eliminating the benefit of the code rate of the time varying MTR code.

Therefore, according to one aspect of the present invention, branches 2 and 5 extend beyond the next step in time (beyond time k). The above extension is labeled 2A, 2B, 5A, 5B in Fig. 7-1 and 7-2 is also indicated by the designations 304, 306, 310, 312, 314, 316 and 318. The extension of paths 2 and 5 does not affect the pruning of the branch as shown in Figure 7-1. Path 2 is still allowed and Path 5 is still not allowed. However, in Figure 7-2, the extension of the path in the extra time interval enables pruning of the branch 2B. That is, branch 2A is still allowed in FIG. 7-2 because it does not violate the time variable MTR code constraint. However, branch (2B) does not violate the code constraint because it represents a tri-bit that starts at even time intervals. Similarly, the branch of Figure 7-2 is allowed while branch 5A is being removed.

The remaining symbols after the pruning of FIG. 7-2, represented by paths 2A and 5B, correspond to +/- (2, -2,2,2) type error events. Therefore, the distance between the two symbols should be considerably larger than the minimum Euclidean distance for the code.

A three-dimensional / four-dimensional signal space detector (3D / 4D SSD) in one aspect of the invention that allows samples with three post-cursor ISI terms is implemented. The detector provides three-dimensional and four-dimensional detection. In three-dimensional detection, the detector selects the data value by determining the position of the sample vector of the three-coordinate signal space. In four-dimensional detection, the detector uses the position of the sample vector in the four-coordinate signal space to determine the data value.

3D / 4D SSDs work well with encoded data using time-varying MTR codes. When using MRT codes with 2 MTR constraints for odd time intervals and 3 MTR constraints for even time intervals, the 3D detection system is used in odd time and the 4 dimensional detection system is used in even time.

The sample vector used in the 3D / 4D SSD preferably consists of a sample combination defined by the following general sample equation.

Equation 30;

Equation 31;

Equation 32;

Equation 33;

Where y _k is the current sample provided to the detector, Is the (kx) -th detected data value, and a _kx is the kx-th input value having the detected current input value as the ak-3 input value.

Therefore, in the three-dimensional portion of the 3D / 4D SSD, the sample vector _{y k-1, y k-} 2, and based on a combination of y _k-3, the sample vector in a four-dimensional part is _{y k, y k-1,} y _k-2 , y _k-3 .

During purely three-dimensional detection, the position of the three-dimensional sample vector is determined in a three-dimensional space defined by the following three axes.

Equation 34;

Equation 35;

Equation 36;

Each of the three axes is formed by canceling the contribution of at least one input value that contributes to each common sample. This can be seen by defining the axis at the sample's end using the general sample equations 30-33. The definition of axis is as follows.

Equation 37;

Equation 38;

Equation 39;

In another embodiment of the present invention, the 3D / 4D SSD uses an interface in a three-dimensional signal space to determine data values at odd intervals. The above interface is determined in a similar manner with respect to equations 5-19 that yield the following four position identifiers.

Equation 40;

Equation 41;

Equation 42;

Equation 43;

The sgn (equation) gives the signal of the equation and the values ΔA, ΔB, ΔC, Δ are given offsets as follows.

Equation 44;

Equation 45;

Equation 46;

Equation 47;

Here, the planes C and D Is -1 and +1 respectively. During the mapping from -1 to 0 in equations 40,43, the detector output will be equal to the detector value .

Equation 48;

Equation 49;

Where " " represents a logic AND operation, and " + " represents a logic OR operation.

When trying to detect data values in even time, the 3D / 4D SSD determines the location of the 4D sample vector in the 4 coordinate signal space. As described above, during a four-dimensional detection four-dimensional sample vector is based on a combination of _{y k, y k-1,} y k-2, y k-3 described by Equations 30-33. During four-dimensional detection, the position of the four-dimensional sample vector is determined in a four-coordinate space defined by the following four axes.

Equation 50;

Equation 51;

Equation 52;

Equation 53;

In the four-coordinate signal space, the position of the four-dimensional sample vector is compared to the position of the boundary separating the two symbols corresponding to paths 2A and 5B in FIG. 7-2.

In the four-coordinate signal space (y ''' _k-3 , y " _k-2 , y _k ) of the 3D / 4D SSD, samples 2A and 2B are (1, -1 + f, 1-f ₁ + f ₂ , 1 + f ₁ -f ₂ + f ₃ ) and (-1,1-F ₁ , -1 + F ₁ -F ₂ , -1-F ₁ + F ₂ -F ₃ ). Of the four coordinates, the coordinates y ''' _k-3 and y _k contribute most to the distance between samples 2A and 5B. Using the above-described projection technique, the plane P between 2A and 5B is described as follows.

Equation 54;

This equation is simplified as follows.

Equation 55;

Using the above equation 39, substituting y ''' _k-3 , the equation 55 is as follows.

Equation 56;

Using the above-described techniques, the location identifier P is defined as follows.

Equation 57;

ΔP is defined as follows.

Equation 58;

Since the two symbols 2A and 5B correspond to error events in the form +/- (2, -2,2,2), the distance between the two symbols should be significantly greater than the minimum Euclidean distance for the code. Therefore, equation 57 does not significantly affect the performance of the detector and is further simplified.

Equation 59;

In the four-dimensional detection, the position identifiers A, B, C and D of equations 40-43 used for three-dimensional detection are continuously valid. Using the above location identifier and the location identifier P of equation 59, the four-dimensional logic detection equation at odd times is:

Equation 60;

Here, "·" represents a logic AND operation, "+" represents a logic OR operation, and A, B, C, D and P contain a mapping of 0 to -1 where necessary.

No location identifiers are dependent on other location identifiers. That is, each may be determined without reference to another location identifier. The four-dimensional logic statement of equation 60 does not depend on the value of the location identifier.

In one embodiment of the invention, the 3D / 4D SSD is implemented using the detector of the full speed of FIG. The detector 400 includes delay operators 402,404 and 406, multipliers 408, adders 410,412,414 and 418, slicers 420,422,424,426 and 428, AND circuits 452,454 and 456, OR circuits 458,460 and multiplexers 462,464.

Delay operators 402,404 and 406 are connected in series and provide outputs 403,405 and 407, respectively. Delay operator 402 receives y _k at the input and likewise a series of delay operators 402,404 and 406 provides y _k-1 , y _k-2 , y _k-3 at each output 403,405,407.

The multiplier 408 receives f1 and yk-2 at its input and produces a product of two values at its output, which is connected to adder circuits 416 and 418. [

In addition to receiving the output of multiplier 408, addition circuit 418 also receives yk-3 and A. The adder circuit 418 combines the inputs to produce an output that is provided to a slicer 428 that produces a 1 if the sum is greater than or equal to 0 and a zero when less than or equal to zero. The adder circuit 418 and the slicer 428 perform the functions described by equation (40).

The adder circuit 416 receives the output of the multiplier 408 along with y _k-3 and? B. The adder circuit 416 provides the sum of the output values to the slicer 426, which operates in a manner similar to the slicer 428. The adder circuit 416 and the slicer 426 also perform the functions described by equation (41).

The adder circuits 410 and 412 receive y _k-1 and y _k-3 , respectively. The adder circuits 410 and 412 also receive? C and? D, respectively. The adder circuit 410 subtracts y _k-1 from y _{k- 3} and y _k-1 to produce an output supplied to the slicer 420 operating in a manner similar to the slicers 426, 428. The adder circuit addition circuit 410 and the slicer 420 execute the function of the equation (43).

The adder circuit 414 receives y _k , y _k-3 and? P and supplies the sum to a slicer 424 that operates the same as the slicer 426. The adder circuit 414 and the slicer 424 also perform the function of equation (59).

Detection of the data value during the odd bit time is determined by the AND circuit 452, the OR circuit 458 and the multiplexer 462, and executes the logic of equations (48, 49). The multiplexer 462 The output of the slicer 420 indicating the location identifier C or the output of the slicer 422 indicating the location identifier D based on the value of the location identifier C. Especially The output of the slicer 420 is passed Is 1, the output of the slicer 422 is passed.

The output of the multiplexer 462 is supplied to the AND circuit 452 along with the output of the slicer 426 indicating the location identifier B. [ The AND circuit 452 performs a logical AND operation on the input value, supplies the output to the OR circuit 458, and also receives the output of the slicer 428 indicating the location identifier A. [ The OR circuit 458 performs a logic OR operation on the two output values and provides the output to the multiplexer 464 and passes the output value if the detected current value is a time that does not allow the tri-bit.

The AND circuits 454 and 456, the OR circuit 460, and the multiplexer 464 provide the necessary detection logic for the time when the tri-bit is allowed. In particular, the above components perform the function of equation (60).

The AND circuit 454 receives the outputs of the slicers 422, 424, and 426, respectively, indicating the location identifiers (D, P, B) and provides a logic AND output with the inputs as a banner. The AND circuit 456 receives the output of the slicers 420 and 426, respectively, which represent the location identifiers C and D, respectively. The outputs of the AND circuits 454 and 456 are received by the OR circuit 460 together with the output of the slicer 428 indicating the location identifier A. The OR circuit 460 performs a logic OR operation on its input to produce an output that is passed by the multiplexer 464 to the detected value if the tri-bit is allowed.

In another embodiment of the 3D / 4D SSD, the detector is implemented as a half rate detector operable at twice the frequency of the input symbol. The block diagram of the detector is shown as detector 498 in FIG.

Detector 498 has two inputs 500, 502, each receiving y _k , y _k-1 . The two delay circuits 504 and 506 delay the signals for the inputs 500 and 502 for two time periods resulting in y _k-2 , y _k-1 in lines 508 and 510, respectively.

Lines 508 and 510 are connected to circuit 512 having an even time period and include multiplier 540, adder circuits 514, 516, 518, 520 and 522, slicers 524, 526, 528, 530 and 532, AND circuits 534 and 536 and an OR circuit 538 . The circuit 512 with an even time period operates in a manner similar to that of the detector 400 portion of FIG. 8 in relation to detecting data values in even time periods. Therefore, the AND circuits 534 and 536 and the OR circuit 538 perform the same logic operation as the OR circuits 460 of the AND circuits 454 and 456 and the detector 400. The output of the even-period circuit 512 is the sum of the detected values to be.

The detector 498 of FIG. 9 includes two odd-period circuits 550 and 552, each executing a function of equations 49,48. In particular, the odd-numbered period circuit 552 includes adders 554, 556, 558, slicers 560, 562, 564, AND circuit 566 and OR circuit 568, (AND) circuit 582 and an OR circuit 584. The AND circuit 582 and the OR circuit 584 are connected in series.

An addition circuit (570 572 554 556), putting together a y _k-2 to the f ₁ and product y ₀ and ΔA, ΔB _{0, 1} ΔA, ΔB ₁ of the _k-1 produced by the respective multiplier 590. The adder circuits 574 and 558 subtract y _k from y _{k -2} and ΔC ₀ and ΔD _1, respectively. ₀ ΔA, ΔB and ΔC ₀ is _0, and each equal to the value of the equation 44,45,46, Is equal to zero. ΔA ₁ , ΔB ₁ and ΔD ₁ are respectively the same as in equations (44), (45) and (47) Is equal to 1.

The outputs of the adder circuits 570, 572, 574, 554, 556, 558 are supplied to the slicers 576, 578, 580, 560, 562, 564, respectively. Each slicer generates 0 if the value at each input is greater than or equal to 0, and 0 if the value is less than or equal to 0.

The outputs of the slicers 578 and 580 are fed to an AND circuit 582, which performs a logic AND function on the two inputs. The output to the AND circuit 582 is supplied to the OR circuit 584 along with the output of the slicer 576. [ The OR circuit 584 performs a logic OR operation on the two inputs to produce a possible detection output corresponding to equation (48).

The outputs of the slicers 562 and 564 are fed to an AND circuit 566, which performs a logic AND function on the two inputs. The output of the AND circuit 566 is supplied to the OR circuit 568 together with the output of the slicer 560. [ RO circuit 568 performs a logic OR operation on the two inputs to produce a possible detection output corresponding to equation 49. [

Therefore, even-time circuits 552, Lt; RTI ID = 0.0 > 0 < / RTI > and 1, respectively. The assumption above Before it is determined Gt; 498 < / RTI > First Is determined by an odd period circuit 512, The value of Calculated using the correct assumptions for Used to select a value. The above selection is performed by the multiplexer 592 RTI ID = 0.0 > 0 < / RTI > Pass the value The circuit 550 of the even period Pass the value.

The present invention therefore implements a signal space detector for the MTR coded channel. Since no constraint is applied to the channel response, the detector can be used in a wide range of user densities. The signal space detector is also implemented in accordance with the present invention with a time variable MTR code in addition to MTR = 2. With the MTR = 2 code, the detector provides a major gain for the 3D-110 detector at low user densities. This performance is improved as time variant MTR codes at high ratios, especially at high densities.

The present invention is configured to determine a first signal space _{y '''k-3,}y''k-2,y' location of a sample vector in a _{k-1 y k-3,} y k-2, y k-1 And a detector (400) of the disk drive (110) including a first detector base (462, 452, 458). Detector 400 is also a second signal space _{y '''k-3,}y''k-2,y' k-1, the location of a second sample vector in _{y k y k-3, y} k-2, 454, 456, 460, 464 configured to determine y _k-1 , y _k . The determination is made using the logic statements of equation (60) to combine multiple position indicators (A, B, C, D, P). Each position indicator provides a position 0 or 1 of a second sample vector associated with each interface A, B, C, D, P. The logic statement and the location identifier are independent of the values of the other location identifiers.

The present invention is also implemented as a method. The method includes a first signal space _{y '''k-3,}y''k-2, y each boundary of _{the' k-1 A, B,} C, the location of a sample vector related to D y _k-3, y B, C, and D, indicating two or more position indicators A, B, C _-2 , y _k-1 . The first data value Is determined based on the position indicator. Each location identifier, each second signal space _{y '''k-3,}y''k-2,y' k-1, the interface of y _k A, B, the second related to C, D, P At least two additional position identifiers A, B, C, D, and P indicating the positions of the sample vectors y _k-3 , y _k-2 , y _k-1 , y _k are determined. The second data value Is determined by combining additional location identifiers using the colonic equation 60. The format of the colonic equation 60 is independent of the value of the additional location identifier.

The invention may also be practiced as a signal space detector configured to perform the steps described above.

While a number of features and advantages of various embodiments of the present invention have been set forth in detail with a detailed description of the structure and function of various embodiments of the present invention, the above description is intended to be illustrative and not restrictive within the scope of the present invention, . For example, a particular element may be altered according to a particular partial response target and MTR code while substantially retaining the same functionality without departing from the spirit or scope of the present invention, and may be varied according to the particular application to the detection system have. Although the preferred embodiment has been described with respect to a signal space detector for a disk drive system, those skilled in the art can use other systems, such as a tape drive, an optical drive, or a magneto optical drive system, without departing from the spirit of the present invention.

Claims (20)

A detector of a disk drive for detecting a data value by using a sample vector formed in each of a plurality of temporarily discrete data samples, A first detector configured to detect a first data value by determining a position of a first sample vector in a first signal space; And And a second detector portion configured to detect a second data value by determining a position of a second sample vector in a second signal space, the determination using a logic statement to combine a plurality of position indicators, Wherein the position indicator provides a position of a second sample vector associated with each boundary surface, the value of the logic statement and the position indicator being independent of the value of the other position indicator. 2. The detector of claim 1, wherein the first signal space has (N-1) coordinates and the second space has N coordinates. 2. The method of claim 1 wherein the data sample is based on an input value that is encoded using a time variable maximum transition behavior constraint that alters between a first constraint and a second constraint for a plurality of times Detector. 4. The apparatus of claim 3, wherein the first detector section detects a data value that matches the encoded input value under a first constraint condition, and the second detector section detects a data value that matches the encoded input value under the second constraint condition . 2. The apparatus of claim 1, wherein the first detector portion determines a position of a first sample vector by using a plurality of position indicators, each of the position indicators providing a position of a first sample vector associated with each interface Lt; / RTI > 6. The detector of claim 5, wherein the at least one interface is used by both the first detector base and the second detector base. 7. The detector of claim 6 wherein all interfaces used by the first detector base are used by the second detector base and the second detector unit uses an additional interface. 8. The detector of claim 7, wherein the position indicator associated with the additional interface is determined based on the coordinates of a second signal space that is not partially provided to the first signal space. 2. The method of claim 1, wherein the position indicator is one of a first value and a second value, the first value indicating that the sample vector is on a first side of each interface, On the second side of the detector. CLAIMS 1. A method of detecting a data value based on a sampled read signal of a disk drive including data samples provided at a plurality of times, (a) determining at each of at least two indicators each location indicator indicating a location of a sample vector associated with a respective interface in a first signal space; (b) determining a first data value based on the location indicator; (c) determining at least two additional position indicators, each additional position indicator indicating a position of a second sample vector associated with each interface in a second signal space; And (d) determining a second data value by combining the additional position indicator with a decision equation having a format that is independent of the value of the further position indicator. 11. The method of claim 10, wherein each value of the additional location indicator is independent of each other. 11. The method of claim 10, wherein the second signal space comprises four coordinates and the first signal space comprises three coordinates. 13. The method of claim 12, wherein the sample vector comprises three temporally separated data samples and the second sample vector comprises four temporally separated data samples. The method of claim 13 wherein the four coordinates of the second signal space _{(a k + f 1 a k} -1 + f 2 a k-2 + f 3 a k-3), (a k-1 + f 1 a k _{-2 + f 2 a k-3} ), (a k-2 + f 1 a k-3) and (includes a _k-3), a _k is the k-th input values f _1, f ₂ and f ₃ is a proportional constant. The method of claim 14, wherein the three coordinates of the first signal space are (a _k-1 + f ₁ a _k-2 + f ₂ a _k-3 ), (a _k-2 + f ₁ a _k- (a _k-3 ). < / _RTI > The method of claim 15 wherein the three coordinates of the first signal space, each _{(a k + f 1 a k} -1 + f 2 a k-2 + f 3 a k-3), (a k-1 + f 1 a _{k-2 + f 2 a k} -3 + ), (a _k-2 + f ₁ a _k-3 + + ) And (a _k-3 + + + ). ≪ / RTI > 11. The method of claim 10, wherein a 5 coordinate interface is present in the second signal space. 11. The method of claim 10 wherein the read signal is based on an input value encoded using a time varying maximum transition behavior constraint that varies periodically between a first constraint and a second constraint for a plurality of times How to. 11. The method of claim 10, wherein steps (a) and (c) occur simultaneously. CLAIMS What is claimed is: 1. A detector for detecting data provided as a sampled read signal read from a disk of a disk drive and comprising a plurality of samples of data at a time, A receiver configured to receive a data sample; And And detection means coupled to the receiver for detecting coded data according to a code having a time varying maximum transition behavior constraint.