KR100485397B1 - Full and half-rate signal space detection for channels with a time-varying mtr - Google Patents

Abstract

The detector 400 of the present invention is provided for detecting data values with sampled data signals to provide temporarily separated data samples. The first detector portions 462, 452, 458 are configured to determine the position of the first sample vector in the first signal space. The second detector portions 454, 456, 460 are configured to determine the position of the second sample vector in the second signal space. The second detector section uses a logic statement to determine the position to combine the plurality of position indicators. Each position indicator provides the position of a second sample vector associated with each boundary. The form of the logical statement is independent of the value of the position indicator. In addition, the position indicator is independent of all other position indicators.

Description

Full and half speed signal space detection for channels with time-varying MTR {FULL AND HALF-RATE SIGNAL SPACE DETECTION FOR CHANNELS WITH A TIME-VARYING MTR}

The present invention relates to a disk drive and more particularly to a data detector of a disk drive for detecting data encoded according to a code in which the data detector has a time varying limitation.

Typical disk drives include one or more disks mounted for rotation on a hub or spindle. Typical disk drives also include transducers supported by hydrodynamic air bearings that fly each disk. Transducers and hydrodynamic air bearings are collectively referred to as data heads. Drive controllers are typically used to control disk drives based on commands received from the host system. The drive controller retrieves information on the disk and controls the disk drive to store information from the disk.

In conventional disk drives, electromechanical actuators operate in negative feedback, closed-loop servo systems. The actuator moves the data head radially on the disk surface for a track search operation and holds the transducer directly on the track on the disk surface for the track tracking operation.

The information is typically stored in concentric tracks on the surface of the disk by supplying a recording signal to the data head for recording the information on the surface of the disk representing the data to be stored. Upon retrieving data from the disc, the drive controller controls the electromechanical actuator to cause the data head to fly over the disc to generate a readout signal based on the information stored on the disc. The read signal is typically adjusted and then decoded in the drive controller to recover the data.

Typical readout channels include data heads, preconditioning logic (such as preamplifier circuits and filter circuits), data detectors and recovery circuits, and error detection and correction circuits. Read channels are typically executed in a drive controller associated with a disk drive.

In a disk drive, it is important that the error rate (bit error rate) for the number of bits written is maintained at a relatively low level. In order to improve bit error rate performance in disk drives, or to increase linear write density in disk drives, a maximum likelihood sequence detection (MLSD) method is required. The above method can be executed using a known Viterbi algorithm. However, running the MLSD method directly is very expensive. For example, the channel response following forward filtering will typically be very long and include more than 10 terms. The Viterbi detector therefore requires 2 ^10-1 states, which is unrealistically complex. Therefore, other techniques have been studied that reduce this complexity but provide results close to those of the direct MLSD method.

One such technique is to apply the Viterbi algorithm to the reduced number of terms by deleting the terms with feedback. For example, by deleting all but two terms (and including the main cursor), the Viterbi detector can have only four states. The detector is referred to as a reduced state sequence estimator (RSSE).

Another technique is to select a channel response target with a small number of terms, rather than a fully bleached target. In the above system, the partial response (PR) target has been improved. One of the above targets is referred to as an enhanced extended partial response maximum likelihood (E ² PRML) target. At high recording densities, for some higher order partial response channel (E ² PRML), the major error event (difference between the two input sequences) encountered with the detector used as the partial response target is generally +/- (2,- 2, 2) was observed. The above error typically occurs when a tribit is shifted by one sample time or a quadbit is mistaken as a dibit, and vice versa. The present invention seeks to address several of the above problems and provides advantages over the prior art.

1 is a top view of a disk drive implementing the features of the present invention and with the upper casing removed.

FIG. 2 is a high level block diagram of the disk drive shown in FIG. 1.

3 is a schematic diagram illustrating a magnetic channel and corresponding readout circuitry to further illustrate the notation used herein.

4-1 and 4-2 illustrate an arrangement of symbols corresponding to a detector according to one aspect of the present invention.

5-1 and 5-2 are waveforms showing major error events for high density MLSDs.

6 is a block diagram illustrating a detector structure of a detector according to an aspect of the present invention.

7-1 and 7-2 are diagrams of an FTDS / DF tree for explaining the operation of a detector according to one aspect of the present invention.

8 is a block diagram showing the structure of one embodiment of the 3D / 4D signal space detector of the present invention.

Figure 9 is a block diagram showing the structure of one embodiment of a half speed 3D / 4D signal space detector of the present invention.

A relatively new class of code has recently been investigated. The code above suggests a maximum maximal shift operation proposed by removing major error events in higher order partial response channels such as high density maximum like sequence detector (MLSD) or enhanced extended partial response maximum similarity (E ² PRML). transition run) (MTR). The MTR code is operative to increase the minimum Euclidean distance between data samples in the magnetic recording channel.

For example, the MTR = 2 code limits the continuous transition operation of the write current to two. In essence, the MTR = 2 code removes the encoding data of all patterns that contain two or more consecutive transitions. As a result, the MTR = 2 code eliminates all patterns that cause major error events for MLSD detectors in high recording density and higher-order PR channels.

Using the MTR constraint, its performance is one detector referred to as a 3D-110 detector, which is almost similar to a fixed delay tree search with decision feedback (FDTS / DF (2)) of depth 2 at high symbol density. Was developed. The detector consists of considering a vector of three received samples in three-dimensional space. Three planar boundaries are calculated and used to divide the signal space into two regions, each of which corresponds to determining +1 or -1 for the bit currently being processed. The 3D-110 detector also eliminates precursor intersymbol interference (ISI) terms, and the two post cursor ISI terms include a forward filter to be 1 and 0, where the cursor is It is also normalized to 1. A feedback filter is implemented that removes all but two post-cursor ISI terms. Therefore, the same discrete time channel pulse response can be expressed as 110 by not passing an error through the detector. The above constraint on the channel response is used to simplify the detector structure.

The magnetic channel natural response approaches 110 targets at high recording densities, but deviates significantly from 110 targets at low recording densities. Therefore, constraining the pulse response for this particular 110 target results in performance degradation compared to the FDTS / DF2, especially at low write densities. Even at high densities, implementing the actual element in the detector can also vary the channel response from the 110 target. For example, using a finite impulse response (FIR) filter of limited length can cause such variation.

Thus, while the 3D-110 channel offers significant advantages in performance and / or simplicity over other detectors (more complex FTDS / DF (2) detectors), it includes the disadvantages described above.

The present invention is directed to a system that addresses many of the above issues and provides other advantages.

The detector of the present invention is provided to detect a data value within a sampled data signal to provide a temporarily separated data sample. The first detector portion is configured to determine the position of the first sample vector in the space of the first signal. The second detector portion is configured to determine the position of the second sample vector in the space of the second signal. The second detector portion uses a logic statement to combine multiple position indicators to determine the position. Each position indicator provides the position of a second sample vector relative to an individual boundary surface. The form of the logical statement is independent of the value of the position indicator. Each position indicator is also independent of all other position indicators.

Referring to FIG. 1, a rotating disk drive system suitable for incorporating the teachings of the present invention is referred to 110 in schematic form. A number of information storage disks 112 are journaled around the spindle motor assembly 114 in the housing 116. The disc 112 has a plurality of concentric circular recording tracks for recording information, respectively, and is schematically represented by 118. Each track 118 is subdivided into a number of sectors, represented by 120. Data may be stored on or retrieved from disk 112 with reference to particular track 118 and sector 120. Actuator arm assembly 122 is preferably rotatably mounted at one corner of housing 116. Actuator arm assembly 122 has a head gimbal assembly 122 each having a slider 125 or transducer 126 having a read / write head that writes information onto the disc 112 and reads information from the disc. . Voice coil motor 128 is adapted to precisely rotate actuator arm assembly 122 back and forth so that transducer 126 moves across disk 112 along arc 130. The control circuit 132 controls the position of the transducer 126 to process information to be received from or written to the disk 112.

2 is a high level block diagram of the control circuit 132 of the disk drive system 110. The microcontroller 134 directly executes all the main functions of the disk drive system 110. The read / write support and interface control circuitry is represented at 136 and the motor and actuator controller 138 is connected to the microcontroller 134 by a general purpose data, address, and control bus 140. Circuitry 136 generally provides a hardware interface between disk drive system 110 and a host computer system (not shown) via communication bus 142. In addition, the circuit 136 generally provides an interface between the motor and actuator controller 138 and the read / write channel 144. Read / write channel 144 receives a signal from cast amplifier 143 which receives a signal from transducer 126. Read / write channel 144 acts as an interface between microcontroller 134 and transducer 126 via line 145. Read / write channel 144 also provides signals to motor and actuator controller 138 via line 146. Controller 138 serves as an interface between microcontroller 134 and motor assembly 114 via line 148 and as an interface between microcontroller 134 and actuator arm assembly 122 via line 150. Is provided.

3 is a schematic diagram of magnetic channel 160 and read channel block 162 and is provided to better understand the notation used herein. Channel 160 includes recording media, such as disk 112 and transducer 126, as is known. Read channel block 162 includes adder 164, front filter 166, sampler 186, forward filter 168, adder 170, detector 172, and feedback filter 174. Read channel block 162 is generally executed on read / write channel 144 shown in FIG. The input 176 to the magnetic channel 166 is preferably a sequence of data bits, with the data bits for the current time period _k represented by a _k . According to one aspect of the present invention the sequence of input bits is preferably encoded according to a code that imposes an MTR = 2 code constraint, where the bits are non-zero where zero values are represented by transitions and zeros are represented by non-transitions. It is provided in Return Inversion (NRZI) format.

When data bits are read from the magnetic channel, the data bits are provided as readback signal 178. The readback signal 178 is typically damaged by noise 180 represented by n (t) added to the readback signal 178 by the adder 164. The noise n (t) and adder 164 are merely to express the noise damaging the readback signal 178 and are not part of the actual hardware implementation. In some cases, noise n (t) is provided and corrupts the feedback signal 178 to form a corrupted read signal 182.

The damaged read signal 182 is provided to the front filter 156. The front filter 156 is implemented with an analog low pass filter that, for example, prevents aliasing and filters the high frequency noise to provide a filtered output 184 to the sampler 186. Sampler 186 samples the filtered output 184 and may be implemented as an analog to digital converter. The sampling signal generated by the sampler 186 is supplied to the forward filter 168.

The forward filter 168 preferably operates alone or co-operates with other filtering to bleach the noise of the readback signal and to supply the adder 170 with the modified readback signal 188 (also designated r _k ). One example of forward filter 168 is a finite impulse response (FIR) filter comprising a plurality of taps. The forward filter 168 removes all precursor intersymbol interface (ISI) terms. The post-cursor ISI term is allowed to estimate the natural value because no constraint is imposed on the channel coefficients. Detector 172 has a sequence 190 at the output (also To be provided).

Print Is an estimate of the input data sequence a _k . Print Is also provided to a feedback filter 174 that is used to provide a feedback signal 192 to the adder 170. The feedback signal 192 has a forward filter 168 added to the output r _k . The combination of these signals is provided to the determining device 172 at the output 194 of the adder 170 (also designated as y _k ). In one embodiment of the present invention, feedback filter 174 is for removing all but two post-cursor ISI terms. In another embodiment, the filter is for removing all but three post-cursor ISI terms.

For a feedback filter that removes all but two post-cursor terms, assuming all previous decisions made by decision device 172 are correct, the same discrete time channel response includes three terms (1, f ₁ , f ₂ ).

Therefore, at time k, the noise-free input y _k to the determining device 172 can be written as

Equation 1; y _k = a _k + f ₁ a _k-1 + f ₂ a _k-2

Where a _k is the input data at time k.

The 3D signal space detector 3D-SSD may be implemented by first considering the symbol arrangement of the 3D space. As will be explained in detail below, the detector maps all possible symbols representing the input data sequence into a three-dimensional space. The detector then obtains a sample vector that includes contributions from a plurality of input samples each formed from a plurality of terms representing an input data sample in the input sample sequence. The sample vector is then mapped to three-dimensional space in the array. The detector then determines which of the possible data symbols in the three-dimensional space is closest to the sample vector at each time interval. This can be either fixed delay detectors such as FDTS / DF detectors or "Perofrmance Data For A Six Sample Look-Ahead 1,7 ML Detection Channel" by Patel, Rutledge et al., November 1993 IEEE Trans. Magn. Vol. 29, No. 6, pp. 4012-4014 and Yamasaki et al., "A 1, 7 Code EEPR4 Read Channel IC With Analog Noise Whitened Detector", PROC. of ISSCC, 1997, pp. It is analogous to determining the path that corresponds to the minimum Euclidean distance between the desired sample value and the observed value for a partial response channel with the capability of foresight as described in 316-317.

Each pair of possible symbols indicating different detector decisions should be separated by an interface. The planar boundaries are combined by logic rules such that the signal space is divided into two regions, one of which corresponds to a detector decision of +1 and the other corresponds to a detector decision of -1. As the sample vector falls into the three-dimensional vector space associated with the interface, the binary decision results in a detector output ( Is emitted by the detector 172. As also described below, the detector structure can be simplified by removing the extra plane and also removing individual symbols farther than the minimum Euclidean distance associated with the code.

4-1 and 4-2 show vector spaces for detectors that analyze an input sequence with three terms making up a sample vector known as an observation vector. In particular, FIGS. 4-1 and 4-2 show the symbol arrangement of the Lorentz channel at a symbol density of 2.25. The array has axis y _k (designated number 200) and axis y ' _k-1 (designated number 202). The arrangements shown in FIGS. 4-1 and 4-2 also include a third axis y '' _k-2 (designated number 204). Axis y '' _k-2 extends into and out of the plane of the paper comprising 4-1 and 4-2.

As described, some symbols are removed based on MTR constraints, and all possible residual symbols that can represent three-dimensional observation vectors are mapped to the arrangements shown in FIGS. 4-1 and 4-2. The planar boundary is then configured to divide the symbols of the three-dimensional space defined by the arrangement. The observation vector is mapped to this location, and the detector provides a determination based on whether the observation vector is in an array associated with the plane boundary.

The axis of this position is defined as follows.

Equation 2; y _k = a _k + f ₁ a _k-1 + f ₂ a _k-2

Equation 3; y ' _k-1 = a _k-1 + f ₁ a _k-2

Equation 4; y " _k-2 = a _k-2

Where y ' _k-1 and y " _k-2 are generally removed available past decisions (ie, at time k and Detector input at time k-1 and time k-2 with intersymbol interference resulting from the determination of " Since the detector processes three input samples as an observation vector, it must determine the input bits a _k-2 (ie, the input bits received two time intervals earlier) at each time k in the detection process.

Table 1

Table 1 shows all possible input sequences that can be represented by observation vectors. Table 1 includes an index referring to index numbers 0-7 corresponding to 2 ⁿ (n = 3) capable symbols. Table 1 also includes the possible symbols recorded in terms of a _k-2 , a _k-1 and ak and the axes (y _k , y ' _k-1 and y'' _k-2 ) recorded in terms of the channel response. Provides an evaluation of.

5-1 and 5-2 show waveforms 206, 208, 210 and 212 representing the major error events observed for MLSD detectors at high density and higher order partial response targets. In FIG. 5-1, an error event is generated when the tribit waveform 206 is shifted by one time interval to produce the shifted treebit 208. In FIG. 5-2 an error event is generated when quadbit waveform 210 is detected as dibit waveform 212 and vice versa.

In order to eliminate the above major error event, the input data is preferably encoded according to the MTR = 2 constraint which rejects the tribit. Therefore, in Table 1, either symbol 2 or symbol 5 It should be rejected according to the value of because these symbols indicate the presence of a tribit. For example, If = + 1, symbol 5 corresponds to a sequence of input bits (+1, -1, +1, -1) in the form of three consecutive transitions and must be removed. For the same reason, If = -1, symbol 2 should be removed.

The arrangement of Figure 4-1 Assuming = 1, we have all possible symbols mapped to it. Symbol 2 is not mapped to the arrangement shown in FIG. 4-1. Similarly, the arrangement shown in FIGS. 4-2 At = + 1 we have all possible symbols mapped to it. Note that symbol 5 is removed.

The symbols corresponding to y " _k-2 = + 1 and -1 are represented by x's and 0's, respectively.

4-1 and 4-2 also show slicer planes A, B, C and D used to divide the various symbols mapped to the arrangement. First, four slicer planes are used. However, to simplify the detector structure as described above, the number of planes is limited to three (e.g., planes C and D are combined to form a new plane E). To further simplify the detector structure, the direction of the plane is limited.

Plane A is provided to separate symbols 0 and 4 (and symbols 1 and 5 of FIG. 4-1). In the case of an optimal detector, the decision boundary is the plane that bisects the lines connecting the separated pairs of symbols. For simplicity, however, the system is limited to positioning the plane to separate its projection on the surface rather than separating the two symbols in three-dimensional space. The above constraint is implemented by selecting two coordinates that contribute best to the distance between two symbols. It can be seen that the y " _k-2 coordinates must be maintained because the two symbols corresponding to the different decisions for input bit a _k-2 are easily separated on the axis. Of the other two coordinates (very low symbol density is The y ' _k-1 coordinates contribute more to the distance between the symbols 0 and 4 than the y _k coordinates, so the symbols are projected onto the y' _k-1 and y " _k-2 surfaces. Therefore, the slicer plane A is constrained to rotate perpendicular to the y ' _k-1 y " _k-2 surface.

Therefore, the projection of plane A onto the selected surface is represented by a line that changes direction because the slicer plane is allowed to rotate. All points of the line have the same distance from the projected symbol pair.

In Table 1, it can be seen that the coordinates of the projections of symbols 0 and 4 on the surface of y ' _k-1 y " _k-2 are given by (1 + f ₁ , +1) and (1-f ₁ , -1), respectively. Therefore, the equation of plane A can be obtained as follows.

Equation 5; (y ' _k-1 -(-1 + f ₁ )) ² + (y " _k-2-1 ) ²

= (y ' _k-1- (1-f ₁ )) ² + (y " _k-2 + 1) ²

The above expression is simplified and calculated as follows.

Equation 6; y " _k-2 + f ₁ y ' _k-1 -f ₁ = 0

Using a similar procedure, the equation for slicer plane B separating symbols 3 and 7 (also symbols 2 and 6 in Figures 4-2) can be expressed as follows.

Equation 7; y " _k-2 + f ₁ y ' _k-1 + f ₁ = 0

When = -1, plane C separates symbols 3 and 5. Plane C is limited to rotating only vertically to y _k y " _k-2 because the coordinates that contribute best to the intersymbol distance are the coordinates corresponding to the y _k and y" _k-2 axes. The plane equation is derived by finding a line that bisects the projection of two symbols onto the y _k y " _k-2 surface.

The above operation Repeated for plane D separating symbols 2 and 4 when = + 1.

The above procedure yields the following four position identification equations.

Equation 8; A: sgn (y " _k-2 + f ₁ y ' _k-1 -f ₁ )

Equation 9; B: sgn (y " _k-2 + f ₁ y ' _k-1 + f ₁ )

Equation 10;

From here to be.

Equation 11;

From here to be.

The location identification equations C and D are also combined to yield

Equation 12;

Equation 12 can be further simplified by setting (f ₁ -f ₂ ) = 1. The above simplification has a negligible effect on detector performance because at two major low channel densities the two symbols separated by the plane are further apart than those separated by planes A and B. Therefore, small changes in plane direction and position do not affect the relative position of the received sample relative to the plane. Therefore, Equation 12 can be simplified as

Equation 13;

By subtracting y ' _k-1 and y " _k-2 in equations 3 and 4, the following relationship is obtained for three position identifiers.

Equation 14;

Equation 15;

Equation 16;

Where ΔA, ΔB and ΔE are offset values provided by

Equation 17;

Equation 18;

Equation 19;

Offset values are typically implemented as short FIR filters with binary inputs, two input multiplexers, or lookup tables.

Decision logic can be implemented by moving the test point through the three-dimensional signal space and recording the relative position of the point relative to the plane. The corresponding detector output is obtained by finding the nearest symbol in the batch for the test point. It is obtained by combining the cases where logic rules or statements generate the same output decision from the detector. However, in the three-dimensional case described herein, logic rules can simply be obtained by inspection. By mapping the boundary decision from -1 to 0, the logic rule can be written as follows.

Equation 20;

Here "·" represents a logic AND operation, and + represents a logic OR operation.

6 is a structural block diagram illustrating a 3D-SSD detector 214 in accordance with an aspect of the present invention. Detector 214 includes delay operators 216 and 218, multiplier 220, summing circuits 222, 224 and 226, slicers 228, 230 and 234, AND circuit 236 and OR circuit 238. As shown in FIG. 6, y _k is provided to delay operator 216 providing y _k−1 at output 240. The term is provided to delay operator 218 providing y _k-2 at its output 242. Multiplier 220 receives f ₁ at its input 244. Summing circuit 222 receives the offset value (ΔE) at its one input 244 and receives a y _k and y _k-2 at the other two inputs. Summing circuit 226 receives an offset value ΔA at its first input 252 and receives y _k-2 of delay operator 218 and output 250 of multiplier 220 at its other input. . The outputs of the summation circuits 222, 224, 226 are provided to the slicers 228, 230, 234, respectively. Outputs 229, 231, 235 of slicers 228, 230, 234 are directed to circuits 236, 238 as shown. The output 256 of the circuit 238 is To provide. The detector 214 therefore uses one multiplier, three slicers, three adders and three two-input multiplexers. Similar 3D-110 detectors can be implemented using three slicers, three adders and a two-input multiplexer.

delete

In the above discussion, the detector 214 is constructed by taking advantage of the fact that at each time interval only one of the two symbols 2 or 5 of Table 1 is provided in the signal space arrangement. This is because the MTR = 2 code always removes one of the two symbols.

However, the major error event described above with reference to FIGS. 5-1 and 5-2 may be eliminated using time varying transitional constraints. The above constraint allows for a tribit but allows it to start at a predetermined interval. In one embodiment, time-varying transitional constraints cause the tree bits to start at different time intervals numbered differently (ie, even or odd). This type of relaxed constraint allows the deployment of code with a high rate. Thus, with a time-varying MTR code, it may have both symbols 2 and 5 provided in the signal arrangement at different time intervals. In order to implement a 3D detector in accordance with the present invention, changes must be made to accommodate changes in code constraints.

delete

In order to better understand the changes required to detect data encoded according to a code with time-varying code constraints, the signal space detector according to the invention can be understood with reference to a FDTS / DF tree of depth two. 7-1 shows a tree 280 with roots starting at an odd time interval k-3 (designated 282). 7-2 shows a tree 284 with roots starting at an even time interval k-3 (designated 286).

In general, the discussion proceeds under the assumption that tribits are allowed to start at even time intervals. While the roots of the trees 280 and 284 show the values of a _k-3 , the next branch running from left to right along the tree is the sample values a _k-2 , a _k-1 , a _k and a _{k + 1} . Illustrated. The time interval is shown along the bottom of each tree and is represented by 288,290,292 and 294 in FIGS. 7-1 and 296,298,300 and 302 in FIG. 7-2.

Looking at trees 280 and 284, we see that either path 2 or 5 is rejected because it violates code constraints. For example, in Fig. 7-1, path 5 is simplified from the tree because it represents a tribit pattern (+ 1, -1, + 1, -1) starting at odd time intervals. Therefore, where the route corresponds to an odd time interval, the situation is equal to the MTR of detector 2 previously described. On the other hand, as shown in Figure 7-2, branches 2 and 5 are allowed where the root corresponds to an even time interval (where the tribit is allowed to start at an even time interval).

In order to realize the coding gain for the FDTS / DF (2) detector with time-varying MTR code, the problematic path can be eliminated at odd times and recovered at even times. However, the presence of paths 2 and 5 increases the likelihood that the section of the tree 280 or 284 to be selected is wrong. In fact, as the user density increases, the error begins to become large enough to eliminate the benefit of the code rate of time varying MTR codes.

Therefore, according to one aspect of the present invention branches 2 and 5 extend (by time interval k) one step further. This extension is labeled 2A, 2B, 5A, 5B in FIGS. 7-1 and 7-2 and is indicated by indication numbers 304,306,310,312,314,316 and 318. The extension of paths 2 and 5 does not affect the pruning of the branches as shown in Figure 7-1. Path 2 is still allowed and path 5 is still not allowed. However, in Fig. 7-2, the extension of the path by one extra time interval enables the pruning of the branch 2B. That is, branch 2A is still permitted in FIG. 7-2 because it does not break time varying MTR code constraints. However, branch 2B violates code constraints because it represents a tribit starting at an odd time interval. Similarly, the branches of Figures 7-2 are allowed, but branch 5A can be removed.

The remaining symbols after pruning in FIGS. 7-2 represented by paths 2A and 5B correspond to error events of the form +/- (2, -2,2,2). Therefore, the distance between the two symbols must be significantly greater than the minimum Euclidean distance for the code.

In one aspect of the invention, a 3D / 4D signal space detector (3D / 4D SSD) is implemented that allows a sample with three post-cursor ISI terms. The detector provides three-dimensional and four-dimensional detection. In three-dimensional detection, the detector selects a data value by determining the position of the sample vector in the three coordinate signal space. In four-dimensional detection, the detector uses the position of the sample vector in the four-coordinate signal space to determine the data value.

3D / 4D SSDs work well with data encoded using time-varying MTR codes. When used with MRT codes with two MTR constraints for odd time intervals and three MTR constraints for even time intervals, the three-dimensional detection system is used for odd times and the four-dimensional detection system is used for even times.

The sample vector used in the 3D / 4D SSD is preferably constructed from sample combinations defined by the following general sample equation.

Equation 30;

Equation 31;

Equation 32;

Equation 33;

Where y _k is the current sample provided to the detector, Is the (kx) th detected data value and _akx is the _kxth input value where the current input value being detected is _ak-3 input value.

Therefore, in the three-dimensional part of the 3D / 4D SSD, the sample vector is based on the combination of y _k-1 , y _k-2 , y _k-3 , and in the four-dimensional part the sample vector is y _k , y _k-1 , y based on the combination of _k-2 , y _k-3 .

While purely three-dimensional detection, the position of the three-dimensional sample vector is determined in three-dimensional space defined by the following three axes.

Equation 34;

Equation 35;

Equation 36;

Each three axis is formed by deleting the contribution of at least one input value that contributes to each general sample. This can be seen by defining the axis by a sample using the general sample equation 30-33. The definition of axis is as follows.

Equation 37;

Equation 38;

Equation 39;

In another embodiment of the present invention, the 3D / 4D SSD determines the data value at odd time intervals using the interface in the three-dimensional signal space. The above boundary is determined in a manner similar to that described above in connection with Equation 5-19, which yields the following four position identifiers.

Equation 40;

Equation 41;

Equation 42;

Equation 43;

Where sgn (expression) gives the expression symbol and the values ΔA, ΔB, ΔC, Δ are the offsets given by

Equation 44;

Equation 45;

Equation 46;

Equation 47;

Where planes C and D Is used when -1 and +1 respectively. When mapping from -1 to 0 in equation 40-43, the detector output depends on the detector value To provide.

Equation 48;

Equation 49;

Here "·" represents a logical AND operation, and "+" represents a logical OR operation.

When trying to detect data values in even time intervals, the 3D / 4D SSD determines the position of the 4D sample vector in the 4 coordinate signal space. As mentioned above, during four-dimensional detection, the four-dimensional sample vector is based on the combination of y _k , y _k-1 , y _k-2 , y _k-3 described by Equation 30-33 above. During four-dimensional detection, the position of the four-dimensional sample vector is determined in four coordinate spaces defined by the following four axes.

Equation 50;

Equation 51;

Equation 52;

Equation 53;

In the four coordinate signal space, the position of the four-dimensional sample vector is compared with the position of the boundary separating two symbols corresponding to paths 2A and 5B of FIGS. 7-2.

In the 4 coordinate signal space (y ''' _k-3 , y'' _k-2 , y' _k-1 , y _k ) of 3D / 4D SSD, samples 2A and 5B are respectively (1, -1 + f, 1) -f ₁ + f ₂ , 1 + f ₁ -f ₂ + f ₃ ) and (-1,1-f ₁ , -1 + f ₁ -f ₂ , -1-f ₁ + f ₂ -f ₃ ) Is located. Of the 4 coordinates, the coordinates y ''' _k-3 and y _k contribute most to the distance between samples 2A and 5B. Using the projection technique described above, the plane P between 2A and 5B is described as follows.

Equation 54;

This equation is simplified as follows.

Equation 55;

Substituting y ''' _k-3 using equation 39 above, equation 55 is

Equation 56;

Using the techniques described above, the location identifier P is defined as follows.

Equation 57;

ΔP is defined as follows.

Equation 58;

Since the two symbols 2A and 5B correspond to error events in the form of +/- (2, -2,2,2), the distance between the two symbols must be significantly greater than the minimum Euclidean distance for the code. Therefore, equation 57 is further simplified without significantly affecting the detector performance.

Equation 59;

In four-dimensional detection, the position identifiers A, B, C and D of equations 40-43 used for three-dimensional detection are valid continuously. Using the position identifier above and the position identifier P in equation 59, the four-dimensional logic detection equation in the even time period is

Equation 60;

Where "·" represents a logical AND operation, "+" represents a logical OR operation, and A, B, C, D and P contain a mapping of 0 to -1 where necessary.

No location identifier depends on another location identifier. That is, each may be determined irrespective of other location identifiers. The format of the four-dimensional logic statement in equation 60 does not depend on the value of the location identifier.

In one embodiment of the invention, the 3D / 4D SSD is implemented using the full speed detector 400 of FIG. Detector 400 includes delay operators 402, 404, 406, multipliers 408, summing circuits 410, 412, 414, 416, 418, slicers 420, 422, 424, 426, 428, AND circuits 452, 454, 456, OR circuits 458, 460, and multiplexers 462, 464.

Delay operators 402, 404, 406 are connected in series and provide outputs 403, 405, 407, respectively. Delay operator 402 receives y _k at its input, and likewise a series of delay operators 402, 404, 406 provide y _k-1 , y _k-2 , y _k-3 at their respective outputs 403, 405, 407.

Multiplier 408 receives f1 and y _k-2 at its input and produces a product of two values at its output connected to summing circuits 416 and 418.

In addition to receiving the output of the multiplier 408, the summation circuit 418 also receives y _k-3 and ΔA. The summation circuit 418 sums the inputs together to produce an output provided to the slicer 428 that generates 1 when the sum is zero or more and zero when it is less than or equal to zero. Adder circuit 418 and slicer 428 together perform the function described by equation (40).

Summing circuit 416 receives the output of multiplier 408 with y _k-3 and ΔB. Summing circuit 416 provides the sum of its input values to slicer 426 operating in a similar manner to slicer 428. Adder circuit 416 and slicer 426 together perform the function described by equation (41).

Summing circuits 410 and 412 receive y _k-1 and y _k-3 , respectively. In addition, summing circuits 410 and 412 receive ΔC and ΔD, respectively. Summing circuit 410 subtracts y _k-1 from y _{k- 3} plus ΔC to produce an output that is supplied to slicer 420 operating in a similar manner as slicers 426 and 428. Summing circuit 410 and slicer 420 execute the function of equation 42. Summing circuit 412 subtracts y _k-1 from y _{k- 3} plus ΔD to produce an output that is supplied to slicer 422 operating in a similar manner as slicers 426 and 428. Summing circuit 412 and slicer 422 together perform the function of equation 43.

The summation circuit 414 receives y _k , y _k-3 and ΔP and supplies the sum to the slicer 424, which operates in the same way as the slicer 426. Summing circuit 414 and slicer 424 together perform the function of equation 59.

Detection of data values during odd bit times is determined by AND circuit 452, OR circuit 458 and multiplexer 462, which execute the logic of equations (48, 49). Multiplexer 462 is Pass either the output of slicer 420 representing position identifier C or the output of slicer 422 representing position identifier D based on the value of. Especially Is 0, the output of slicer 420 is passed Is 1, the output of the slicer 422 is passed.

The output of the multiplexer 462 is supplied to the AND circuit 452 along with the output of the slicer 426 representing the position identifier B. AND circuit 452 performs a logical AND operation on the input value, and supplies an output to OR circuit 458, which also receives the output of slicer 428 representing position identifier A. The OR circuit 458 performs a logical OR operation on the two outputs and supplies the outputs to the multiplexer 464 which, if detected, is present at a time interval that does not allow tribits. Pass the output value.

AND circuits 454 and 456, OR circuits 460, and multiplexer 464 provide the necessary detection logic during the time interval when the tribit is allowed. In particular, the above components perform the function of equation 60.

The AND circuit 454 receives the outputs of the slicers 422, 424, 426 representing the position identifiers D, P, and B, respectively, and provides a logical AND output based on the input. The AND circuit 456 receives the output of slicers 420 and 426 representing the location identifiers C and D, respectively, and provides a logical AND output based on the input. The outputs of the AND circuits 454 and 456 are received by the OR circuit 460 with the output of the slicer 428 representing the position identifier A. The OR circuit 460 performs a logical OR operation on its input to produce an output passed by the multiplexer 464 to the detected value if tribits are allowed.

In another embodiment of a 3D / 4D SSD, the detector is implemented as a half speed detector capable of operating at twice the frequency of the input symbol. The block diagram of the detector is shown as detector 498 of FIG.

Detector 498 has two inputs 500 and 502 that receive y _k and y _k-1 , respectively. Two delay circuits 504 and 506 delay the signal on inputs 500 and 502 for two time periods, generating y _k-2 and y _k-1 on lines 508 and 510, respectively.

Lines 508 and 510 are connected to an even-time periodic circuit 512 that includes a multiplier 540, adder circuits 514, 516, 518, 520, 522, slicers 524, 526, 528, 530, 532, AND circuits 534, 536, and OR circuits 538. The even-time period circuit 512 operates in a manner similar to the portion of the detector 400 of FIG. 8 associated with detecting data values of even time periods. Thus, the AND circuits 534, 536 and the OR circuit 538 perform the same logical operations as the AND circuits 454, 456 and OR circuit 460 of the detector 400. The output of the circuit 512 of even-time period is the detected value to be.

The detector 498 of FIG. 9 includes two odd-time periods of circuits 550 and 552, each of which perform the function of equations 49 and 48, respectively. In particular, the odd-time period circuit 550 includes a summation circuit 554, 556, 558, a slicer 560, 562, 564, an AND circuit 566, and an OR circuit 568, while the odd period circuit 552 is a summation circuit 570, 572, 574. , Slicers 576, 578, 589, AND circuit 582, and OR circuit 584.

Summing circuit (570 572 554 556) is added to y _k-2 to the f ₁ and y and multiplies ₀ ΔA, ΔB _{0, 1} ΔA, ΔB ₁ of the _k-1 produced by the respective multiplier 590. Summing circuits 574 and 558 subtract y _k from the terms y _k-2 and ΔC ₀ and ΔD ₁ , respectively. ΔA ₀ , ΔB _0, and ΔC ₀ are the same as the values in equations 44,45,46, respectively, Is equal to 0. ΔA ₁ , ΔB _1, and ΔD ₁ are the same as in equations 44,45,47, respectively Is equal to 1.

The outputs of the summation circuits 570, 572, 574, 554, 556, 558 are supplied to the slicers 576, 578, 580, 560, 562, 564, respectively. Each slicer produces +1 if the value at each input is zero or more and zero if it is less than or equal to zero.

The outputs of slicers 578 and 580 are supplied to an AND circuit 582, which performs a logical AND function on the two inputs. The output of the AND circuit 582 is supplied to the OR circuit 584 with the output of the slicer 576. OR circuit 584 performs a logical OR operation on the two inputs to produce a possible detection output corresponding to equation 48.

Outputs of slicers 562 and 564 are supplied to AND circuit 566, which performs a logic AND function on the two inputs. The output of AND circuit 566 is supplied to OR circuit 568 along with the output of slicer 560. RO circuit 568 performs a logical OR operation on the two inputs to produce a possible detection output corresponding to equation 49.

Thus, odd-time period circuits 552 and 550 Suppose is equal to 0 and 1 respectively, and calculate a possible detection value based on this assumption. The assumptions above Before is determined Is needed in the detector 498 because it is calculated. First Is determined by an even-time period of circuit 512, The value of Calculated using the exact assumptions about Used to select a value. The choice above In circuit 552 of an odd-time period when 0 is 0 Pass the value Is an even period in circuit 550 This is done by multiplexer 592 passing the value.

Therefore, the present invention implements a signal space detector for the MTR coded channel. Since no constraint applies to the channel response, the detector can be used over a wide range of user densities. Signal space detectors are also implemented in accordance with the present invention having MTR = 2 constraints, as well as time-varying MTR codes. The MTR = 2 code gives the detector significant gains over the 3D-110 detector at low user densities. Performance is further improved as a fast time varying MTR code, especially at high densities.

The invention is configured to determine the position y _k-3 , y _k-2 , y _k-1 of the sample vector in the first signal space y ''' _k-3 , y'' _k-2 , y' _k-1 The detector 400 of the disk drive 110 including the first detector units 462, 452, and 458 is provided. The detector 400 also includes positions y _k-3 , y _k-2 , of the second sample vector in the second signal space y ''' _k-3 , y'' _k-2 , y' _k-1 , y _k . second detector portions 454, 456, 460, 464 configured to determine y _k-1 , y _k . Decisions are made using the logic of equation 60 to combine a number of position indicators (A, B, C, D, P). Each position indicator provides the position (0 or 1) of the second sample vector relative to each interface A, B, C, D, P. Logical statements and position identifiers are independent of the value of other position identifiers.

The invention is also implemented as a method. The method includes the position y _k-3 , y of the sample vector associated with each boundary A, B, C, D in the first signal space y ''' _k-3 , y'' _k-2 , y' _{k-1 determining} at least two location identifiers A, B, C, D representing _k-2 , y _k-1 . Then, the first data value Is determined based on the location identifier. At least two location identifiers (A, B, C, D and P) are determined, where each additional location identifier is each second signal space y ''' _k-3 , y'' _k-2 , y ' _k-1 , y _k represent positions y _k-3 , y _k-2 , y _k-1 , y _k of the second sample vector associated with each interface A, B, C, D, P. Second data value Is determined by combining additional location identifiers using decision equation 60. The format of decision equation 60 is independent of the value of the additional location identifier.

The invention can also be implemented as a signal space detector configured to carry out the steps described above.

Although a number of features and advantages of the various embodiments of the present invention have been described in the foregoing description in conjunction with the structures and functions of the various embodiments of the present invention, the foregoing description is for the purpose of description and in particular the broader meaning of the terms presented in the appended claims. It is understood that modifications may be made in detail to the structure and arrangement of parts within the principles of the invention to the extent indicated by. For example, a particular element may be altered according to a particular partial response target and MTR code while substantially maintaining the same functionality without departing from the spirit or scope of the present invention. Many of the features and advantages of the various embodiments of the present invention Although described in the foregoing description together with the structure and function of the various embodiments of the present invention, the above description is for the purpose of explanation, and in particular to the extent indicated by the broad meaning of the terms expressed in the appended claims. Understand that changes can be made in detail with respect to structures and arrangements. Furthermore, although the preferred embodiments described herein relate to signal space detectors for disk drive systems, those skilled in the art will recognize that the present invention is directed to other systems, such as tape drives, optical drives, or magneto optical drive systems. It will be appreciated that it can be applied without departing.

Claims (20)

A detector in a disk drive for detecting data values by using a sample vector formed from each of a plurality of temporarily separated data samples, A first detector section configured to detect a first data value by determining a position of the first sample vector in the first signal space; And A second detector portion configured to detect a second data value by determining a position of a second sample vector in a second signal space, wherein the determination is made by using a logic statement to combine a plurality of position indicators; Each position indicator provides a position of a second sample vector associated with each boundary surface, wherein the values of the logical statement and the position indicator are independent of the values of the other position indicators. The detector of claim 1, wherein the first signal space has (N-1) coordinates and the second space has N coordinates. 2. The method of claim 1, wherein the data sample is based on an input value encoded using a time varying maximum transitional operating constraint that varies between the first and second constraints over a plurality of time intervals. Detector. The method of claim 3, wherein the first detector detects a data value corresponding to an input value encoded under a first constraint, and the second detector detects a data value corresponding to an input value encoded under a second constraint. The detector, characterized in that. The method of claim 1, wherein the first detector portion determines the position of the first sample vector by using a plurality of position indicators, each position indicator providing a position of the first sample vector associated with each boundary surface. Detector. 6. A detector as claimed in claim 5, wherein said at least one interface is used by both the first detector section and the second detector section. 7. The detector according to claim 6, wherein all the interfaces used by the first detector section are used by the second detector section, and the second detector section uses an additional interface. 8. The detector of claim 7, wherein the position indicator associated with the additional boundary is determined based in part on a coordinate of a second signal space not provided in the first signal space. The method of claim 1, wherein the position indicator is one of a first value and a second value, wherein the first value indicates that the sample vector is present on the first side of each boundary, and the second value indicates that the sample vector is angulated. A detector, wherein said detector is on the second side of the interface. A method of detecting a data value based on a sampled read signal comprising data samples read from a disc of a disc drive and provided at a plurality of time intervals, the method comprising: (a) determining at least two location identifiers each representing a location of a sample vector associated with each boundary in the first signal space; (b) determining a first data value based on said location identifier; (c) determining at least two additional location identifiers each representing a location of a second sample vector associated with each boundary in a second signal space; And (d) determining a second data value by combining an additional location identifier using a decision equation, wherein the format of the decision equation is independent of the value of the additional location identifier. 11. The method of claim 10 wherein the respective values of the additional location identifiers are independent of each other. 12. The method of claim 10, wherein the second signal space comprises four coordinates and the first signal space comprises three coordinates. 13. The method of claim 12, wherein the sample vector comprises three temporarily separated data samples and the second sample vector comprises four temporarily separated data samples. The method of claim 13, wherein the four coordinates of the second signal space are (a _k + f ₁ a _k-1 + f ₂ a _k-2 + f ₃ a _k-3 ), (a _k-1 + f ₁ a _k-2 + f ₂ a _k-3 ), (a _k-2 + f ₁ a _k-3 ), and (a _k-3 ), where a _k is the kth input and f ₁ , f ₂ and f ₃ is a proportionality constant. 15. The apparatus of claim 14, wherein the three coordinates of the first signal space are (a _k-1 + f ₁ a _k-2 + f ₂ a _k-2 ), (a _k-2 + f ₁ a _k-3 ) and (a _k-3 ). The method of claim 15, wherein the second sample vector is respectively (a _k + f ₁ a _k-1 + f ₂ a _k-2 + f ₃ a _k-3 ), (a _k-1 + f ₁ a _k-2 + f ₂ a _k-3 + ), (a _k-2 + f ₁ a _k-3 + + ) And (a _k-3 + + + Four samples with 11. The method of claim 10, wherein there are five coordinate boundaries in the second signal space. 11. The method of claim 10, wherein the read signal is based on an input value encoded using a time varying maximum transition operation constraint that varies periodically between the first and second constraints over a plurality of time intervals. How to. The method of claim 10 wherein step (a) and step (c) occur simultaneously. A detector for detecting data read from a disk of a disk drive and provided at multiple time intervals as a sampled read signal comprising data samples, the detector comprising: A receiver configured to receive a data sample; And And a detection means coupled to the receiver for detecting data coded according to a code having a time varying maximum transitional operating constraint.