KR20010039812A - Ferroelectric random access memory device having a reference circuit which generates a reference voltage changed according to a variation of a polarization state of a ferroelectric capacitor - Google Patents

Abstract

PURPOSE: A ferroelectric random access memory(RAM) device including a reference circuit generating a reference voltage varying according to a polarization state variation of a ferroelectric capacitor of a memory cell is provided to generate an optimum reference voltage having a middle value of bit line voltages corresponding to data state even if the polarization state of the ferroelectric capacitor varies. CONSTITUTION: The ferroelectric random access memory device(1000) includes: a memory cell array(800) which includes a plurality of memory cells arranged in a matrix form of column and row, and wherein each memory cell has a ferroelectric capacitor and an access transistor; a sense amplifier circuit sensing data state of each memory cell using a reference voltage; a dumping voltage supplying circuit(200) which includes a reference circuit providing the reference voltage to the sense amplifier circuit and wherein the reference circuit generates dumping voltages having different level each other when the power is supplied; a polarization state discriminating circuit(100) which has a plurality of dummy cells each including a ferroelectric capacitor and an access transistor, and discriminates the polarization state of each ferroelectric capacitor in response to the dumping voltages corresponding to each dummy cell, and outputs pass/fail signals corresponding to each dummy cell as a discrimination result, and each pass/fail signal indicates whether a voltage corresponding to the polarization state of the ferroelectric capacitor is lower or higher than the corresponding dumping voltage; a decoder circuit(400) generating selection signals by decoding the pass/fail signals from the polarization state discriminating circuit; and a reference voltage generating circuit(600) generating distribution voltages of different level corresponding to each selection signal when the power is supplied and outputting one of the distribution voltages as the reference voltage in response to the selection signals.

Description

FERROELECTRIC RANDOM ACCESS MEMORY DEVICE HAVING A REFERENCE CIRCUIT WHICH GENERATES A REFERENCE VOLTAGE CHANGED ACCORDING TO A VARIATION OF A POLARIZATION STATE OF A POLARIZATION FERROELECTRIC CAPACITOR}

TECHNICAL FIELD The present invention relates to integrated circuit memories, and more particularly, to a ferroelectric random access memory device.

Ferroelectric random access memory (hereinafter referred to as "FRAM") uses a ferroelectric capacitor as a storage element of each memory cell. Each memory cell stores a logic state based on the electrical polarization of the ferroelectric capacitor. Ferroelectric capacitors have a dielectric comprising a ferroelectric such as lead zirconate titanate (PZT) between both electrodes or plates. When a voltage is applied to the plates of the ferroelectric capacitor, the ferroelectric is polarized in the electric field direction. The switching threshold for changing the polarization state of the ferroelectric capacitor is called the coercive voltage. Ferroelectric capacitors represent hysteresis, and currents in the polarization state flow to the capacitor. If the voltage applied to the capacitor is greater than the forced voltage, the ferroelectric capacitor will change the polarization states according to the polarity of the applied voltage. The polarization state is maintained after the power is removed, resulting in non-volatile. The ferroelectric capacitor may vary between polarization states within about 1 ns (nanosecond), wherein about 1 ns is erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EPEROMs), or flash EEPROM. Faster than the program time of most other nonvolatile memories, such as

The data stored in the memory cell is read as follows. First, a voltage is applied across the electrodes of the ferroelectric capacitor of the memory cell. Then, the amount of change in charges induced on the bit line connected to the memory cell is sensed. In order to detect the change amount of charges induced on the bit line, that is, the voltage change on the bit line, a reference voltage having an intermediate value between a voltage corresponding to data '1' and a voltage corresponding to data '0' is generated. Requires a circuit. In general, a reference voltage is generated by using a reference cell including a ferroelectric capacitor having the same characteristics as a memory cell.

The main problem in detecting the polarization state of ferroelectric capacitors in a memory cell is the fact that the field / polarization characteristic loop (hysteresis loop) of the ferroelectric capacitor changes over time, which can cause any This is due to aging due to the polarization of. In general, hysteresis curves eventually deteriorate due to changes in polarization characteristics that occur over time. This is a fundamental physical phenomenon due to the non-reversibility of at least a portion of the ferroelectric under the electric field / polarization cycle. This change in ferroelectric makes it very difficult to use a reference cell containing a ferroelectric capacitor to determine the polarization state of the ferroelectric memory cell.

Various methods have been proposed to overcome the above mentioned problems. One of them is USP No. 5,432,731, entitled "FERROELECTRIC MEMORY CELL AND METHOD OF SENSING AND WRITING THE POLARIZATION STATE THEREOF", incorporated by reference. One capacitor ferroelectric memory cell having a reference cell disclosed in the '731 patent is shown in FIG. 1.

The reference cell 12 of the '731 patent is configured such that a reference voltage is supplied on a bit line (BITC) according to a voltage dumping structure. More specifically, as shown in FIG. 1, the '731 patent discloses a reference cell 12, which includes a first switching transistor 35 and a second switching transistor 37. And a reference capacitor 39. The gate of the first switching transistor 35 is connected to the REF WORD line 40 and the source is connected to the BITC line 25. One plate of the reference capacitor 39 is connected to ground and the other plate is connected to the drain of the first switching transistor 35 and to the source of the second switching transistor 37. The drain of the second switching transistor 37 is connected to a reference potential REF INIT, and the gate is connected to receive a reference initial signal.

By generating a DC level reference voltage using the voltage dumping structure of the '731 patent described above, the above-described problem (problem when using a reference cell including a ferroelectric capacitor) can be solved. However, memory cells also suffer from a change in the hysteresis loop of the ferroelectric capacitor over time. That is, as shown in FIG. 2A, the polarization state of the ferroelectric capacitor of the memory cell is initially changed according to an ideal hysteresis curve (indicated by the solid line), and the ferroelectric capacitor of the memory cell deteriorates after a predetermined time has elapsed. Or along the weakened hysteresis curve (indicated by dashed lines). As can be seen in FIG. 2A, the polarization level of the ferroelectric capacitor in which data '1' is stored is reduced from point "C" to point "C", while the polarization level of the ferroelectric capacitor in which data "0" is stored is point "A". Is increased from "to point" A '".

Referring to FIG. 2B, which shows a change in voltage and time induced on a bit line according to a data state, the rate at which the bit line voltage corresponding to data '1' (D1) decreases and the data '0' (D0) correspond to The rate at which the bit line voltage increases is different. As a result, after a predetermined time t1 elapses, an optimal sensing margin (the sensing margin MD1 between the bit line voltage corresponding to the data '1' and the reference voltage VREF and the bit line voltage corresponding to the data '0'). It is impossible to ensure that the sense margin MD2 between the reference voltage VREF and the reference voltage VREF is set equal to or greater than the required margin. For example, when the detection margin MD1 is smaller than the required margin and the detection margin MD0 is larger than the required margin at time t1 of FIG. 2B, the sensing operation of the data MD1 is impossible. Therefore, when the hysteresis curve is deteriorated as shown in FIG. 2A, the reference circuit of FIG. 1 is used to generate a reference voltage VREF having an intermediate value between the bit line voltage of data '1' and the bit line voltage of data '0'. It is impossible to do. This means that the lifetime of the FRAM device is shortened or the reliability is degraded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ferroelectric random access memory device including a reference circuit for generating a reference voltage that varies with a change in polarization state of a ferroelectric capacitor of a memory cell over time.

Another object of the invention is a ferroelectric comprising a reference circuit that generates an optimal reference voltage having an intermediate value of the bit line voltages corresponding to the data states, even if the polarization state of the ferroelectric capacitor of the memory cell changes over time. It is to provide a random access memory device.

1 is a circuit diagram showing a ferroelectric random access memory device according to the prior art;

2A is a graph showing ideal hysteresis characteristics and degraded hysteresis characteristics;

2B is a graph showing changes in voltage and time corresponding to data states stored in ferroelectric memory cells;

3 is a block diagram showing a ferroelectric random access memory device in accordance with the present invention;

4 is a preferred embodiment of the polarization state determination circuit of FIG. 3;

5 is a preferred embodiment of the dumping voltage generator of FIG. 3;

6 is a preferred embodiment of the driver circuit of FIG. 3;

7 is a preferred embodiment of the data input circuit of FIG. 3;

8 is a block diagram illustrating the decoder circuit of FIG. 3;

9A-9C show preferred embodiments of each decoder of the decoder circuit shown in FIG. 8;

10 is a preferred embodiment of the reference voltage generator circuit of FIG. 3;

11 is a preferred embodiment of the default value control circuit of FIG. 3;

12 is a timing diagram for explaining the operation of the polarization state determination circuit; And

FIG. 13 is a diagram illustrating a relationship between bit line induced voltages and dumping voltages corresponding to data '1' and data '0'.

* Description of the symbols for the main parts of the drawings *

100: polarization state determination circuit 200: dumping voltage supply circuit

300: data input circuit 400: decoder circuit

500: latch circuit 600: reference voltage generation circuit

700: default value control circuit 800: memory cell array

900: reference circuit 1000: FRAM

The reference circuit of the present invention for achieving the above object will be used as a circuit for generating a reference voltage in a nonvolatile semiconductor memory device, that is, a ferroelectric random access memory device. The reference circuit includes a polarization state determination circuit, a decoder circuit, and a reference voltage generator circuit. The polarization state determination circuit generates dummy paths having ferroelectric capacitors to generate pass / fail signals indicating a degree of change in the polarization state of the ferroelectric capacitor generated over time. The pass / fail signals thus generated are decoded by the decoder circuit, and the reference voltage generator circuit internally generates reference voltages of different levels using a power supply voltage, and uses the pass / fail signals as selection information. One of the reference voltages is output.

According to such a reference circuit, it is possible to generate an optimum reference voltage in response to the change in the polarization state of the ferroelectric capacitor generated over time.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention are described in detail below on the basis of reference drawings.

The novel reference circuit according to the present invention is used in ferroelectric random access memory devices (FRAM devices) and automatically tracks the polarization state change of the ferroelectric capacitors over time by using dummy cells with ferroelectric capacitors. And the polarization state change so tracked is reflected in the reference voltage. That is, the reference voltage is automatically changed in response to the change in the polarization state of the ferroelectric capacitor of the memory cell. Therefore, the reference circuit of the present invention changes according to the change in polarization state, and generates an optimal reference voltage having an intermediate value between the voltage corresponding to data '1' and the voltage corresponding to data '0'. As a result, not only the life of the FRAM device can be extended, but also the reliability can be improved.

A FRAM device having a reference circuit for generating the reference voltage as described above is shown in FIG. 3 in block diagram form. The FRAM device 1000 of the present invention includes a memory cell array 800 and a reference circuit 900. The memory cell array 800 is for storing data information, and includes memory cells (not shown) each having ferroelectric capacitors and sense amplifiers (not shown) for sensing data of each memory cell. The reference circuit 900 automatically tracks the polarization state change of the ferroelectric capacitor over time and supplies the memory cell array 800 with a reference voltage VREF that varies according to the tracked polarization state change. The reference circuit 900 includes a polarization state discriminating circuit 100, a dumping voltage supplying circuit 200, a data input circuit 300, and a decoder circuit. circuit 400, latch circuit 500, reference voltage generating circuit 600, and default value control circuit 700. The circuit configuration and operation description for each block 100 to 700 of the above-described reference circuit 900 will be described in detail below with reference to FIGS. 4 to 11.

4, a preferred embodiment of the polarization state determination circuit according to the present invention is shown. The polarization state determining circuit 100 includes a plurality of dummy cells 110, dummy sense amplifiers 118 corresponding to the dummy cells 110, first dummy bit lines DBLj, j = 1 to 8, And second dummy bit lines DBLjB. Each dummy cell 110 includes an access transistor 112 and a ferroelectric capacitor 114. Each capacitor is manufactured substantially the same as ferroelectric capacitors provided to the memory cell array 800. One plate electrodes of the ferroelectric capacitors 114 are respectively connected to corresponding first dummy bit lines DBL1 to DBL8 through current paths of corresponding access transistors 112, and the other plate electrodes are dummy plate lines. Commonly connected to (DPL). Gates of the access transistors 112 are commonly connected to the dummy word line DWL.

Here, half of the dummy cells 110, for example, the dummy cells 110 connected to the first dummy bit lines DBL1 to DBL4, may have data of a first logic state (eg, data '1'). ), And the remaining dummy cells 110, for example, the dummy cells 110 connected to the first dummy bit lines DBL5 to DBL8, may store data in a second logic state (eg, data ' 0 ') respectively.

4, capacitors C1 to C8 respectively corresponding to the second dummy bit lines DBL1B to DBL8B are further provided to the polarization state determination circuit 100. One plate electrodes of the capacitors C1 to C8 are connected to receive the dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP0_4 provided from the dumping voltage supply circuit 200, respectively, and the other plate electrodes are connected to the corresponding NMOS. The transistors 116 are connected to corresponding second dummy bit lines DBL1B to DBL8B, respectively. The NMOS transistors 116 are simultaneously turned on / off according to the logic state of the switch control signal DMPRS.

The dummy sense amplifiers 118 are connected between the first dummy bit lines DBL1 to DBL8 and the second dummy bit lines DBL1B to DBL8B, respectively. Each dummy sense amplifier 118 senses a voltage difference between the corresponding first and second dummy bit lines, and according to the detection result, the dummy sense amplifier 118 detects the voltage of the corresponding first dummy bit line in a first logic state (eg, Power supply voltage) or a second logic state (eg, ground voltage) and amplify the voltage of the second dummy bit line to a second logic state or a first logic state, respectively. That is, the corresponding first and second dummy bit lines are set to logic states opposite to each other by corresponding sense amplifiers. The logic states of the first dummy bit lines sensed and amplified by the dummy sense amplifiers 118 are used as pass / fail signals PF1 to PF8 respectively corresponding to the dummy cells 110.

The first dummy bit lines DBL1 to DBL8 are connected to the decoder circuit 400 of FIG. 3 through NMOS transistors 120, and the NMOS transistors 120 are in a logic state of a switch control signal DYSW. At the same time turn on / off. The first and second dummy bit lines DBL1 to DBL8 and DBL1B to DBL8B are precharged to the ground voltage through corresponding NMOS transistors (or bit line precharge transistors) 122. The NMOS transistors 122 are simultaneously turned on when the precharge signal DBLP is at a logic high level, and constitute a precharge circuit.

According to this circuit configuration, the polarization state determination circuit 100 responds to each of the ferroelectric capacitors 114 in response to a plurality of dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP0_4 provided from the dumping voltage supply circuit 200. Determine the polarization state. The polarization state determination circuit 100 generates pass / fail signals PFj, j = 1 to 8 corresponding to each of the dummy cells 110 as a determination result. Here, the dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP0_4 have different voltage levels and correspond to the dummy cells 110, respectively. As a result, the pass / fail signals PF1 to PF8 may be configured such that voltages corresponding to polarization states of corresponding ferroelectric capacitors (voltages respectively induced in corresponding bit lines) are higher than corresponding dumping voltages. Or low.

For example, when the bit line induced voltage corresponding to the polarization state of the ferroelectric capacitor corresponding to the dummy bit line DBL1 is higher than the corresponding dumping voltage, the corresponding pass / fail signal PF1 is at a high level, that is, “1”. Has. In addition, when the bit line induced voltage corresponding to the polarization state of the ferroelectric capacitor corresponding to the dummy bit line DBL1 is lower than the corresponding dumping voltage, the corresponding pass / fail signal PF1 has a low level, that is, "0". Have In contrast, when the bit line induced voltage corresponding to the polarization state of the ferroelectric capacitor corresponding to the dummy bit line DBL5 is higher than the corresponding dumping voltage, the corresponding pass / fail signal PF5 is at a high level, that is, "1". Has Then, when the bit line induced voltage corresponding to the polarization state of the ferroelectric capacitor corresponding to the dummy bit line DBL5 is lower than the corresponding dumping voltage, the corresponding pass / fail signal PF5 becomes low level, that is, "0". Have Therefore, when the voltages induced in the dummy bit lines DBL1 to DBL4 are higher than the corresponding dumping voltages, the signals PF1 to PF4 all have a "1" indicating a pass state. Similarly, when the voltages induced in the dummy bit lines DBL5 to DBL8 are lower than the corresponding dumping voltages, the signals PF5 to PF8 all have a "0" indicating a pass state.

Referring again to FIG. 3, the dumping voltage supply circuit 200 includes a dumping voltage generator 220 and a driving circuit 240. A preferred embodiment of the dumping voltage generator 220 is shown in FIG. 5, and a preferred embodiment of the drive circuit 240 is shown in FIG. 6. In FIG. 5, the dumping voltage generator 200 is a voltage divider using a plurality of resistors 251 to 260 and NMOS transistors 261 to 264 connected as shown, and those skilled in the art have learned. Well known to The signal labeled “VDMP_DEN” is used to prevent power loss that may occur in the dumping voltage generator 200 after the reference circuit 900 generates the proper reference voltage VREF.

In FIG. 6, the driving circuit 240 transmits the dumping voltages VDMP1_A to VDMP1_D and VDMP0_A to VDMP0_D generated by the dumping voltage generator 220 positioned at the front end to the polarization state determination circuit 100. A plurality of drivers 240_1 to 240_8 corresponding to the voltages VDMP1_A to VDMP1_D and VDMP0_A to VDMP0_D, respectively. The drivers 240_1 to 240_8 are commonly activated or deactivated by a signal labeled "RDVEN". Although a detailed circuit of the driver 240_1 for only one dumping voltage VDMP1_A is shown in the figure, the drivers 240_2 to 240_8 respectively corresponding to the remaining dumping voltages will be configured in the same manner. This drive circuit 240 is used to reduce the burden (eg, signal line loading for delivering the dumping voltage) of the dumping voltage generator 220 connected to the polarization state determination circuit 100. The drivers 240_1 to 240_8 output stable dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP0_4 at substantially the same level as the voltages provided from the dumping voltage generator 220, respectively.

Referring to Fig. 7, a preferred embodiment of a data input circuit according to the present invention is shown. The data input circuit 300 of FIG. 7 is for supplying data '1' and data '0' to be written to the dummy cells 110 provided to the polarization state determination circuit 100 at power up, and are connected as shown. PMOS transistors 302, 304, 306, 308 and NMOS transistors 310, 312, 314, 316. The NMOS transistors 310, 312, 314, 316 are simultaneously turned on / off in accordance with the logic state of the signal labeled "DINEN", and the PMOS transistors 302, 304, 306, 308 are switched to "DINENB". It is simultaneously turned on / off according to the logic state of the indicated signal. The signal DINEN is a signal that is activated during a write operation (described in detail below) of the dummy cells 110 to be performed at power up. When power is supplied to the FRAM device in which the reference circuit 900 of the present invention is implemented, half of the dummy cells 110 provided to the polarization state determination circuit 100 are connected to the data '1 through the data input circuit 300. 'Is written, and data' 0 'is written to the remaining dummy cells through the data input circuit 300. This will be described in detail later.

8, a block diagram illustrating a decoder circuit in accordance with the present invention is shown. The decoder circuit 400 of FIG. 8 decodes the pass / fail signals PF1 to PF8 output from the polarization state determination circuit 100 to select an optimal reference voltage according to the polarization state change of the ferroelectric capacitor. (SEL1 to SEL6) are generated. The decoder circuit 400 is composed of seven decoders 402-414 to have a three-stage decoding structure. Detailed circuitry of each decoder is shown in Figs. 9A to 9C. In this circuit configuration, when the signal denoted as "DEC_EN" is maintained at the low level, the output signals SEL1 to SEL6 of the decoder circuit 400 are kept in the low level inactive state.

All output signals of the decoder circuit 400 when all of the signals PF1 to PF8 output from the polarization state determination circuit 100 indicate a pass state '11110000' or a fail state '00001111'. SEL1 to SEL6 remain in the low level inactive state. The selection signals SEL1 to SEL6 are latched in the latch circuit 500. In addition, when the output signals PF1 to PF8 of the polarization state determination circuit 100 have abnormal values due to particles during the manufacturing process, the output signals SEL1 to SEL6 of the decoder circuit 400 are all at a low level. Will remain inactive. For example, when the output signals PF1 to PF4 of the polarization state determination circuit 100 have values such as "1011", "1101", and "1110", the output signals SEL1 to SEL6 of the decoder circuit 400. ) All remain low level inactive. Similarly, when the output signals PF5 to PF8 of the polarization state determination circuit 100 have values such as "1000", "0100", and "0010 ', the output signals SEL1 to SEL6 of the decoder circuit 400. ) All remain low level inactive.

In the above-mentioned cases, the reference voltage VREF of the default value is output from the reference voltage generating circuit 600. The output signals SEL1 to the decoder circuit 400 may be output from the reference voltage generator circuit 600 so that the reference voltage VREF having a level lower or higher than the default value is output from the reference voltage generator circuit 600. Any one of SEL6) is activated to a high level. This is described in detail later.

10, a preferred embodiment of a reference voltage generator circuit according to the present invention is shown. The reference voltage generator circuit 600 of FIG. 10 is activated by a signal labeled "REFEN", and output signals LAT1 to LAT6 of the latch circuit 500 and output signals VREF_DEN of the default value control circuit 700. In response, the reference voltage VREF is output. The signal VREF_DEN is high level while referring to FIG. 11 showing the default value control circuit 700, while power is supplied and the output signals LAT1 to LAT6 of the latch circuit 500 are all held at a low level. Has In contrast, when any one of the output signals LAT1 to LAT6 is at the high level, the signal VREF_DEN is at the low level. In Fig. 11, the signal labeled "VCCH" is a signal that is maintained at a high level when power is supplied and the power is raised above a certain level.

After the power is supplied, the output terminal VREF of the reference voltage generating circuit 600 is charged to a predetermined voltage (hereinafter referred to as "default voltage") through the NMOS transistor 664 turned on by the signal VREF_DEN. Then, as described above, when the pass / fail signals PF1 to PF8 output from the polarization state determination circuit 100 all have pass states or fail states, and pass / fail signals due to particles during the manufacturing process. When the ones PF1 to PF8 have abnormal logic values, the output signals SEL1 to SEL6 of the decoder circuit 400 are all kept at a low level. This causes the NMOS transistors 658, 660, 662, 666, 668, 670 of FIG. 10 to be turned off by the output signals LAT1-LAT6 of the latch circuit 500. Therefore, the reference voltage generator circuit 600 outputs the default voltage as the reference voltage VREF. On the other hand, when any one of the output signals SEL1 to SEL6 of the decoder circuit 400 becomes high level, the output signal VREF_DEN of the default value control circuit 700 becomes low level, which is a reference voltage generator circuit. Causes 600 to generate a reference voltage VREF at a level lower or higher than the default voltage.

As described above, when power is supplied to the FRAM device in which the reference circuit 1000 of the present invention is implemented, half of the dummy cells 110 provided to the polarization state determination circuit 100 have a data input circuit 300. Data '1' is written through), and data '0' is written through the data input circuit 300 to the remaining dummy cells. After data is written to the polarization state determination circuit 100, a read operation for determining the polarization states of the dummy cells provided to the polarization state determination circuit 100 is performed. Description of this will be described in detail with reference to FIG. 12. 12 is an operation timing diagram for explaining a write operation and a read operation of the polarization state determination circuit.

First, an operation for writing data to the dummy cells of the polarization state determination circuit 100 will be described. Referring to FIG. 12, the control signals DINEN, VREF_DEN, VDMP_DEN, and RDVEN at power up are all activated to a high level. The PMOS and NMOS transistors 302-316 of the data input circuit 300 are both turned on by the low-high transition of the control signal DINEN and the high-low transition of the control signal DINENB, resulting in a polarization state. The output signal lines PF1 to PF4 of the discrimination circuit 100 are respectively charged to a high level, and the other output signal lines PF5 to PF8 are respectively charged to a low level. At the same time, the dumping voltage supply circuit 200 generates different levels of dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP0_4 according to the low-high transition of the control signals VDMP_DEN and RDVEN. At this time, the decoder circuit 400 is inactivated by the control signal DEC_EN maintained at the low level.

Under these conditions, the first and second dummy bit lines DBL1 to DBL8 and DBL1B to DBL8B are connected to the ground voltage Vss through corresponding NMOS transistors 122 turned on by the high level precharge signal DBLP. Each is precharged). After the precharge signal DBLP transitions from the logic high level to the logic low level, the dummy word line signal DWL transitions from the logic low level to the logic high level, resulting in an access transistor ( 112 is turned on.

Then, as shown in FIG. 12, as the switch control signal DMPRS is activated high, dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to different levels provided from the dumping voltage supply circuit 200. VDMP_4 is transferred to corresponding second dummy bit lines DBL1B to DBL8B, respectively. As the dummy plate line signal DPL is activated in the form of a pulse, a voltage is applied from the dummy plate line DPL to the first dummy bit line across the ferroelectric capacitor of each dummy cell. That is, a negative voltage is applied across the ferroelectric capacitor. After a predetermined time has elapsed, the voltage applied across the capacitor is removed as the dummy plate line (DPL) signal is deactivated. As a result of this operation, the ferroelectric capacitor of each dummy cell has a polarization state at point " A "

Under this condition, as shown in FIG. 12, each of the first dummy bit lines DBL1 to DBL4 becomes PMOS transistors 302 of the data input circuit 300 as the switch control signal DYSW is activated to a high level. Driven (or charged) to the power supply voltage Vcc supplied through ˜308, the remaining first dummy bit lines DBL5 to DBL8 are connected to the NMOS transistors 310 to 316 of the data input circuit 300. Grounded through. In this case, since a positive voltage is applied across the ferroelectric capacitors 114 of the dummy cells 110 connected to the first dummy bit lines DBL1 to DBL4 having the power supply voltage Vcc, the first dummy bit line Polarization states of the ferroelectric capacitors 114 of the dummy cells 110 connected to the fields DBL1 to DBL4 are changed from the point "A" to the point "C". That is, data '1' is written in the dummy cells 110 connected to the dummy bit lines DBL1 to DBL4.

In contrast, ideally, since there is no voltage difference across the ferroelectric capacitors 114 of the dummy cells 110 connected to the grounded first dummy bit lines DBL5 to DBL8, the first dummy bit lines DBL5. The polarization states of the ferroelectric capacitors 114 of the dummy cells 110 connected to ˜DBL8 continue to remain at the point “A” state. That is, data '0' is written in the dummy cells 110 connected to the first dummy bit lines DBL5 to DBL8. Then, after the dummy plate line signal DPL is activated again in the form of a pulse, the switch control signal DYSW and the dummy word line signal DWL are sequentially deactivated. Through this series of processes, the write operation of the polarization state determination circuit is terminated. As the write operation is terminated, the control signals DINEN and DINENB are inactivated to the low level and the high level, respectively, so that the data input circuit 300 is electrically disconnected from the polarization state determination circuit 100.

After the write operation performed at power-up is completed, the ferroelectric capacitor 114 of each of the dummy cells 110 to generate the reference voltage VREF according to the polarization state of the ferroelectric capacitor 114 provided to each of the dummy cells 110. The polarization state of is determined. This is described in detail below with reference to FIG. 12.

First, the first and second dummy bit lines DBL1 to DBL8 and DBL1B to DBL8B are connected to the ground voltage Vss through corresponding NMOS transistors 122 turned on by the high level precharge signal DBLP. Each is precharged. After the precharge signal DBLP transitions from the high level to the low level, the dummy word line signal DWL transitions from the low level to the high level, so that the access transistors 112 of the dummy cells 110 are It is turned on at the same time.

Then, as shown in FIG. 12, as the switch control signal DMPRS is activated high, the dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP_4 from the dumping voltage supply circuit 200 become NMOS transistors. The data is transferred to the corresponding second dummy bit lines DBL1B to DBL8B through 116. As the dummy plate line signal DPL is activated in the form of a pulse, a voltage is applied from the dummy plate line DPL to the corresponding first dummy bit line across the ferroelectric capacitor of each dummy cell 110. That is, a negative voltage is applied across the ferroelectric capacitor. After a predetermined time elapses, the voltage applied across the capacitor is removed as the dummy plate line signal is deactivated. As a result, the polarization states of the ferroelectric capacitors of the dummy cells connected to the dummy bit lines DBL1 to DBL4 in which the data '1' is stored are switched from the point "C" to the point "A" in FIG. 2A, while the data '0'. The polarization states of the ferroelectric capacitors of the dummy cells connected to the stored dummy bit lines DBL5 to DBL8 are returned to the point "A" via the point "D" at the point "A". The voltages of the first dummy bit lines DBL1 to DBL8 induced by the ferroelectric capacitors having such switched polarization states are of high level as a result of the level comparison with the dumping voltages by the corresponding sense amplifiers 118. It will be amplified to a supply voltage or a low level ground voltage. The logic states of the first dummy bit lines DBL1 to DBL8 thus set are output to the decoder circuit 400 as pass / fail signals PF1 to PF8 when the switch control signal DYSW is activated. In more detail, the logic states of the pass / fail signals PF1 to PF8 are determined as follows.

Referring to FIG. 13, the dumping voltages VDMP1_1 to VDMP1_4 and VDMP0_1 to VDMP0_4 supplied to the polarization state determination circuit 100 may include a bit line induced voltage VD1 and a data “0” corresponding to data “1”. Is present between the bit line induced voltage VD0 corresponding to. Specifically, the dumping voltages VDMP1_1 to VDMP1_4 exist between the intermediate value Vm of the voltages VD1 and VD0 and the voltage VD1, and the dumping voltages VDMP0_1 to VDMP0_4 are the voltage. (Vm, VD0) exists between. By using the dumping voltages having the voltage distribution, and the dummy cells 110 in which data '0' and data '1' are stored in half, the polarization state of the ferroelectric capacitor changed over time can be determined.

For example, when the voltage VD1 of the first dummy bit line induced by the dummy cell in which data '1' is stored is higher than the corresponding dumping voltage, the voltage of the first dummy bit line is changed by the corresponding sense amplifier. Amplified to a power supply voltage Vcc representing 1 '. In contrast, when the voltage VD1 of the first dummy bit line induced by the dummy cell in which data '1' is stored is lower than the corresponding dumping voltage, the voltage of the first dummy bit line is set by the corresponding sense amplifier. It becomes the ground voltage (Vss) representing '0'. Similarly, when the voltage VD0 of the first dummy bit line induced by the dummy cell in which data '0' is stored is lower than the corresponding dumping voltage, the voltage of the first dummy bit line is changed by the corresponding sense amplifier. It becomes the ground voltage Vss indicating 0 '. In contrast, when the voltage VD0 of the second dummy bit line induced by the dummy cell in which data '0' is stored is higher than the corresponding dumping voltage, the voltage of the first dummy bit line is set by the corresponding sense amplifier. Amplified to a power supply voltage (Vcc) representing '1'.

As can be seen from the foregoing description, before the hysteresis curve is changed, the logic states on the first dummy bit lines DBL1 to DBL4 connected to the dummy cells in which the data '1' is stored by the corresponding sense amplifiers 118. Logic states on the first dummy bit lines DBL5 to DBL8 having a high level of logic '1', that is, a power supply voltage level and connected to the dummy cells in which data '0' is stored, are corresponding to the sense amplifiers 118. Has a low level of logic '0', that is, a ground voltage level. This means that the pass / fail signal goes high level (logic '1') when data '1' is read in its original state, and the pass / fail signal goes low level (logic '0' when data '0' is read in its original state. ') Means.

If the hysteresis curve of the ferroelectric capacitor decays as indicated by the dotted line in FIG. 2A as time passes, the voltage VD1 of the bit line induced by the dummy cell in which data '1' is stored is lowered and data '0' The voltage VD0 of the bit line induced by this stored dummy cell becomes high. As a result, the first dummy bit lines (e.g., VDMP1_4, VDMP1_3 in FIG. 13) higher than the voltage VD1 (for example, point X in FIG. For example, DBL4 and DBL3 each have a ground voltage representing data '0' by corresponding sense amplifiers. Each of the remaining first dummy bit lines (eg, DBL1, DBL2) has a power supply voltage representing the data '1' originally written.

As a result, a read operation on the dummy cells connected to the first dummy bit lines DBL1 and DBL2 is normally performed, while a read operation on the dummy cells connected to the first dummy bit lines DBL3 and DBL4 is normally performed. Not executed (a read failure occurs). Therefore, the pass / fail signals PF1 and PF2 corresponding to the first dummy bit lines DBL1 and DBL2 become logic high levels, and the pass / fail corresponding to the first dummy bit lines DBL3 and DBL4. The fail signals PF3 and PF4 are at a logic low level.

Similarly, the first dummy bit line (e.g., DBL8) associated with the dumping voltage (e.g., VDMP0_4, VDMP1_3 in FIG. 13) at a level lower than the voltage VD0 (e.g., point Y in FIG. 13) that is so high. ) Has a power supply voltage representing data '1' by the corresponding sense amplifier. Each of the remaining first dummy bit lines (eg, DBL5, DBL6, DBL7) has a ground voltage representing the data '0' originally written. As a result, the pass / fail signals PF5, PF6, and PF7 corresponding to the first dummy bit lines DBL5, DBL6, and DBL7 go low, and the pass / fail corresponding to the first dummy bit lines DBL8. The fail signal PF8 goes high.

The pass / fail signals PF1 to PF8 generated according to the method as described above are decoded by the decoder circuit 400, and the selection signals SEL1 to SEL6 according to the decoding result are stored in the latch circuit 500. Stored. Then, the reference voltage generator circuit 600 internally generates different levels of distribution voltages, and in accordance with the selection signal being activated among the selection signals SEL1 to SEL6 output from the latch circuit 500. The division voltage of any one of the generated division voltages is output as an optimal reference voltage VREF according to the change in the polarization state of the ferroelectric capacitor. If the cases described above occur, that is, the pass / fail signals PF1 to PF8 output from the polarization state determination circuit 100 all have pass states or fail states, or pass / fail signals due to particles during the manufacturing process. If the ones PF1 to PF8 have abnormal logic values, a default value will be output as the reference voltage VREF.

According to the present invention, not only a read operation for generating the selection signals SEL1 to SEL6 but also an operation for writing data '1' and data '0' is performed only at power-up. Since the selection signals SEL1 to SEL6 generated at power up are stored in the latch circuit 500, the reference voltage VREF is stored in the latch circuit 500 without a read operation of the polarization state determination circuit 100. It will be automatically generated according to the selection signals SEL1 to SEL6. And, the reference circuit 900 according to the present invention can be applied to both the "open bit line structure" as well as the "folded bit line structure" well known in the art. Self-explanatory

As described above, the polarization state of the ferroelectric capacitor that changes over time can be determined by the logic states of the pass / fail signals. Therefore, the reference circuit of the FRAM device according to the present invention can generate a reference voltage having an intermediate value of the bit line voltages corresponding to the data states even if the polarization state of the ferroelectric capacitor of the memory cell changes over time.

Claims (17)

A memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns, each memory cell having a ferroelectric capacitor and an access transistor; A sense amplifier circuit for sensing a data state of each memory cell using a reference voltage; A reference circuit providing the reference voltage to the sense amplifier circuit, The reference circuit includes a dumping voltage supply circuit for generating dumping voltages each having a different level when power is supplied; A polarization state determination circuit having a plurality of dummy cells each including a ferroelectric capacitor and an access transistor, and determining a polarization state of each of the ferroelectric capacitors in response to the dumping voltages corresponding to each of the dummy cells; The polarization state determination circuit outputs pass / fail signals corresponding to each of the dummy cells as a determination result, wherein each of the pass / fail signals is higher than a corresponding dumping voltage to a polarization state of the ferroelectric capacitor. Low or not; A decoder circuit for decoding the face / fail signals output from the polarization state determination circuit to generate selection signals; Generating reference voltages internally to generate different levels of distribution voltages corresponding to the selection signals when the power is supplied, and outputting one of the distribution voltages as the reference voltage in response to the selection signals; A ferroelectric random access memory device comprising a circuit. The method of claim 1, And a latch circuit coupled between the decoder circuit and the reference voltage generator circuit, the latch circuit latching the selection signals. The method of claim 2, The plurality of dummy cells are divided into dummy cells of a first group and a second group, wherein the dummy cells of the first group store data of a first logic state and the dummy cells of the second group are of a second logic state. A ferroelectric random access memory device for storing data. The method of claim 3, wherein The polarization state determination circuit, A plurality of first dummy bit lines connected to the dummy cells, respectively; Second dummy bit lines corresponding to the first dummy bit lines, respectively; A plurality of first switch transistors coupling the first dummy bit lines to the decoder circuit in response to a first switch control signal such that logic states on the first dummy bit lines are output as the pass / fail signals; A plurality of capacitors respectively corresponding to the dumping voltages, each capacitor having a first plate electrode connected to a corresponding dumping voltage and a second plate electrode connected to a corresponding second dummy bit line through a second switch transistor; Second switch transistors respectively corresponding to the capacitors operate in response to a second switch control signal; A first logic connected between each of the first and second dummy bit lines, each sensing a voltage difference between corresponding first and second dummy bit lines and as a result of the first logic A plurality of sense amplifiers that amplify to one of a state and a second logic state, And logic states of the pass / fail signals are determined by logic states of first dummy bit lines sensed and amplified by corresponding sense amplifiers. The method of claim 4, wherein And the dumping voltages are between voltages corresponding to data of the first logic state and data of the second logic state. The method of claim 5, And the polarization state determination circuit further comprises a bit line precharge circuit for charging the first and second dummy bit lines to a ground voltage. The method of claim 5, The reference circuit additionally includes a data input circuit coupled to the first dummy bit lines, wherein the data input circuit includes dummy cells of the first group in response to a data input signal activated when the power is applied. A ferroelectric random access memory device for transmitting a power supply voltage to first dummy bit lines corresponding to and transmitting a ground voltage to first dummy bit lines corresponding to the dummy cells of the second group, respectively. A memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns, each memory cell having a ferroelectric capacitor and an access transistor; A sense amplifier circuit for sensing a data state of each memory cell using a reference voltage; A reference circuit providing the reference voltage to the sense amplifier circuit, The reference circuit includes a dumping voltage supply circuit for generating dumping voltages each having a different level when power is supplied; A polarization state determination circuit having a plurality of dummy cells each including a ferroelectric capacitor and an access transistor, and determining a polarization state of each of the ferroelectric capacitors in response to the dumping voltages corresponding to each of the dummy cells; The polarization state determination circuit outputs pass / fail signals corresponding to each of the dummy cells as a determination result, wherein each of the pass / fail signals is higher than a corresponding dumping voltage to a polarization state of the ferroelectric capacitor. Low or not; A decoder circuit for decoding the face / fail signals output from the polarization state determination circuit to generate selection signals; Internally generate different voltage distribution voltages corresponding to the selection signals when the power is supplied, and output one of the distribution voltages as the reference voltage when any one of the selection signals is activated A reference voltage generator circuit; A control signal is generated when the power is applied, and the control signal is deactivated when any one of the selection signals is activated, and the control signal is kept activated when all of the selection signals remain inactive. Consists of circuits, And the reference voltage generator circuit outputs a default value as the reference voltage in response to the control signal generated when all of the selection signals remain in an inactive state. The method of claim 8, And the default value is any one of the division voltages, and the division voltage output as the reference voltage when any one of the selection signals is activated is higher or lower than the default value. The method of claim 9, And an output terminal of the reference voltage generator circuit is precharged to the default value by the control signal. The method of claim 8, When all of the pass / fail signals have a logic state of a pass state, when all of the pass / fail signals have a logic state of a fail state, or when the pass / fail signals have abnormal logic states, the decoder Circuitry deactivates all of the selection signals. The method of claim 8, And a latch circuit coupled between the decoder circuit and the reference voltage generator circuit, the latch circuit latching the selection signals. The method of claim 12, The plurality of dummy cells are divided into dummy cells of a first group and a second group, wherein the dummy cells of the first group store data of a first logic state and the dummy cells of the second group are of a second logic state. A ferroelectric random access memory device for storing data. The method of claim 13, The polarization state determination circuit, A plurality of first dummy bit lines connected to the dummy cells, respectively; Second dummy bit lines corresponding to the first dummy bit lines, respectively; A plurality of first switch transistors coupling the first dummy bit lines to the decoder circuit in response to a first switch control signal such that logic states on the first dummy bit lines are output as the pass / fail signals; A plurality of capacitors respectively corresponding to the dumping voltages, each capacitor having a first plate electrode connected to a corresponding dumping voltage and a second plate electrode connected to a corresponding second dummy bit line through a second switch transistor; Second switch transistors respectively corresponding to the capacitors operate in response to a second switch control signal; A first logic connected between each of the first and second dummy bit lines, each sensing a voltage difference between corresponding first and second dummy bit lines and as a result of the first logic A plurality of sense amplifiers that amplify to one of a state and a second logic state, And logic states of the pass / fail signals are determined by logic states of first dummy bit lines sensed and amplified by corresponding sense amplifiers. The method of claim 14, And the dumping voltages are between voltages corresponding to data of the first logic state and data of the second logic state. The method of claim 15, And the polarization state determination circuit further comprises a bit line precharge circuit for charging the first and second dummy bit lines to a ground voltage. The method of claim 15, The reference circuit additionally includes a data input circuit coupled to the first dummy bit lines, wherein the data input circuit includes dummy cells of the first group in response to a data input signal activated when the power is applied. A ferroelectric random access memory device for transmitting a power supply voltage to first dummy bit lines corresponding to and transmitting a ground voltage to first dummy bit lines corresponding to the dummy cells of the second group, respectively.