KR20010037709A - A circuit for controlling operation region of dynamic random access memory - Google Patents

Abstract

PURPOSE: A circuit is provided to increase operation speed at a low voltage by differently setting a precharge voltage of a local bit line and a precharge voltage of a global bit line. CONSTITUTION: The circuit includes a pair of local bit lines(MO,MO'), the first and second cell mat drivers(103,104), the first and second sense amplifier drivers(105,106) and sense amplifiers(107,108). The local bit lines read data of cell mats(101,102) having cell blocks for storing data and transfer the read data to a pair of global bit lines(M1,M1'). The first and second cell mat drivers precharge the local bit lines with a reference voltage(VBLR) in response to a switch signal(LBLPre) before an operation and transfer the data signal of the local bit lines to the global bit lines by a switch(SW). The first and second sense amplifier drivers precharge the global bit lines with voltages(V1,V2) higher than the reference voltage before the operation. The precharge voltage of the sense amplifier driver is higher than the precharge voltage of the cell mat driver. The sense amplifiers amplify the data signal of the global bit lines and transfer to a peripheral circuit.

Description

A CIRCUIT FOR CONTROLLING OPERATION REGION OF DYNAMIC RANDOM ACCESS MEMORY}

The present invention relates to a DRAM operating area control circuit for dividing a bit line into a local bit line and a global bit line and precharging them to different voltage levels to level up sensing voltages. It relates to a DRAM operating area control circuit for widening the operating area and improving the sensing speed.

In the trend toward low voltage operation of DRAMs, the sensing margin and speed of the bit line have a significant effect on the operating margin of the chip.

Accordingly, the present invention broadens the operating range for the low voltage, improves the sensing speed, and reduces the chip size so that the DRAM can be operated at a low voltage, which will be described later.

FIG. 1 is an operation circuit diagram of a conventional DRAM. As shown in FIG. 1, a local bit line (MO, MO ') and a global bit line (M1, M1') for transmitting data, and a cell block for storing data Cell mats 11 and 12, each of which is positioned below and above the cell mats 11 and 12, and reads data from cell blocks selected by the cell mats 11 and 12 at a constant level. The first and second sense amplifiers 21 and 22, which are amplified by the first and second sense amplifiers 21 and 22, and the global bit line before operation. Located between the first and second sense amplifier drivers 31 and 32 for precharging M1 and M1 'to 1/2 voltage and the cell mats 11 and 12, the bit line MO, MO ') and the first and second cell metric which transfers the data read from the cell mat from the local bit line to the global bit line according to the switch signal after the operation. Switch drivers 41 and 42.

Looking at the prior art configured in this way in detail as follows.

The bit line for transmitting data from the cell mat to the sense amplifier is composed of a local bit line (MO, MO ') and a global bit line (M1, M1') as shown in FIG. It consists of (SWB).

In this state, when no data is read or written, the precharge and equalizer signals Precharge & EQ1 (Precharge & EQ2) go high and the switch signal SW goes low.

Thus, the inverted switch signal SWB goes high.

As the precharge and equalizer signals (Precharge & EQ1) (Precharge & EQ2) and the inverted switch signal (SWB) become high, the first and second sense amplifier drivers 31 (32) and the cell mat driver 41 42 are all turned on.

As the transistors of the first and second sense amplifier drivers 31 and 32 are turned on, the global bit lines M1 and M1 'are connected to each other to make the same reference voltage VBLR, and the cell mat As the transistors of the driving units 41 and 42 are turned on, the local bit lines MO and MO 'are connected to each other to make the same reference voltage VBLR.

That is, before the operation, the bit lines are precharged so that the voltage difference does not exist at the same voltage so that the sense amplifiers 21 and 22 do not operate.

When the precharge operation is to be performed while the data signal is read from the cell mat or the data signal is written to the cell mat, the precharge and equalizer signals (Precharge & EQ1) (Precharge & EQ2) The inverted switch signal SWB goes low.

Accordingly, the transistors of the first and second sense amplifier drivers 31 and 32 and the cell mat drivers 41 and 42 are both turned off to turn off the local bit line MO MO ′ and the global bit line M1. (M1 ') is a power supply voltage and a ground voltage, respectively, so that the sense amplifiers 21 and 22 are operable.

At this time, if the word lines WL1 and WL2 of the cell mat 11 and 12 are enabled, the data signals in the cell mat 11 and 12 are loaded on the local bit line MO where the precharge is released. At the same time, the transistors Q11-Q14 are turned on by the switch signal SW.

Accordingly, the data signal loaded on the local bit line M0 is transferred to the global bit line MO MO 'through the transistors Q11 and Q13.

The global bitline then runs across several cell mats and delivers them to the sense amplifier 21 at the end of the array.

Therefore, the sense amplifier 21 amplifies the read data to a predetermined level and outputs it to the peripheral circuit.

Thereafter, the switch signal SW goes low and the inverted switch signal SWB goes high to turn on all transistors of the cell mat driver 41 and 42 to precharge the bit line.

The same circuit as in FIG. 1 is connected and operated.

Eventually, by connecting the capacitor and the local bit line with large resistance, and the capacitor and the global bit line with small resistance, the number of sense amplifiers is reduced and the chip size is reduced.

However, in the prior art as described above, although the global bit line brings the saving of the array area, the sensitivity of the sensing is slightly reduced because the capacitor component of the bit line increases. This reduces the width of the margin during low voltage operation, causing problems in sensing the sensing amplifier for cell data.

Accordingly, in order to solve the above-mentioned problems, the operation area control circuit of the DRAM is provided to separate the precharge levels of the local bit line and the global bit line to control them at different levels, thereby increasing the speed during low voltage operation. Is in.

Another object of the present invention is to provide an operation region control circuit of a DRAM which can simultaneously improve the operation and speed of a low voltage region by adjusting a value of a read output voltage through a switch connecting a local bit line and a global bit line. .

1 is an operation circuit diagram of a conventional DRAM.

2 is an operating area control circuit diagram of the present invention DRAM.

3 is a bit line generation waveform diagram in FIG.

***** Explanation of symbols for the main parts of the drawing *****

101,102: cell mat 103,104: cell mat driving unit

105,106: sense amplifier driver 107,108: sense amplifier

In order to achieve the above object, the present invention provides a pair of local bitlines for reading data from a cell mat, which is composed of cell blocks each storing data, and transferring the data to a pair of global bitlines. A first and second cell mat driver for precharging the local bit line to a reference voltage as a separate switch signal before the operation, and transferring the data signal of the local bit line to the global bit line by the switch, and the pair of global And a first and second sense amplifier driver configured to precharge the bit line to a voltage set higher than the reference voltage before operation.

Hereinafter, with reference to the accompanying drawings in detail as follows.

FIG. 2 is a circuit diagram illustrating an operation area control circuit of the present invention. As shown in FIG. 2, cell mats 101 and 102 made up of cell blocks for storing data and cell mats 101 and 102 are shown. ) Operates a pair of local bit lines MO and MO 'that read data from and transfer the data to a pair of global bit lines M1 and M1', and the pair of local bit lines MO and MO '. The first and second cell matte driving units which precharge to the reference voltage VBLR by a separate switch signal LBL Pre and transfer the data signal of the local bit line to the global bit line by the switch SW ( 103 and 104 and the first and second sense amplifier drivers 105 for precharging the pair of global bit lines M1 and M1 'to a voltage set higher than the reference voltage VBLR before operation. 106 and amplify the data signal transmitted through the global bit lines M1 and M1 'to a predetermined level to peripheral circuits. Up to constitute the sense amplifier 107 (108).

Referring to the operation and effect of the present invention configured as described in detail as follows.

The bit line for transmitting data from the cell mat to the sense amplifier is composed of local bit lines (MO, MO ') and global bit lines (M1, M1'), as shown in FIG. It consists of (SWB).

In this state, when the data is not read or written, the precharge and equalizer signals Precharge & EQ1 (Precharge & EQ2) and the precharge signal LBL Pre are high, and the switch signal SW is low. Becomes

As the precharge and equalizer signals Precharge & EQ1 and Precharge & EQ2 become high, the transistors of the first and second sense amplifier drivers 105 and 106 and the cell mat drivers 103 and 104 are both present. Is turned on.

As the transistors of the first and second sense amplifier drivers 105 and 106 are turned on, the global bit lines M1 and M1 ′ are connected to each other so that the global bit lines of the first sense amplifier driver 105 may be connected to each other. M1 and M1 'are precharged with the same V1 voltage, and the global bit lines of the second sense amplifier driver 106 are precharged with the same V2 voltage.

As the transistors of the cell mat driving units 103 and 104 are turned on, the local bit lines MO and MO 'are connected to each other and precharged to the same reference voltage VBLR.

The voltages V1 and V2 used as the precharge voltage levels of the global bit lines MO and MO 'are set to an appropriate level in consideration of the capacitor components of the global bit line and the local bit line, and the level is set as the reference voltage VBLR. It is set higher, and the levels of the voltages V1 and V2 are set in common or set separately to set the level of the best possible operating characteristics.

As the bit line is precharged before operation, the sense amplifiers 107 and 108 do not operate.

Then, after the operation, i.e., to read the data signal from the cell mat or to write the data signal to the cell mat, the precharge and equalizer signals (Precharge & EQ1) just before the word lines WL1 and WL2 are enabled. (Precharge & EQ2) and the precharge signal (LBL Pre) go low.

Therefore, the transistors of the first and second sense amplifier drivers 105 and 106 and the cell mat driver 103 and 104 are both turned off to release the precharge.

When the word lines WL1 and WL2 are enabled and the data signals from the cell mats 101 and 102 are loaded on the local bit lines MO and MO ', the switch signal SW becomes high at this time. Is enabled.

As the switch signal SW is enabled, the data signal loaded on the local bit lines M0 and MO 'is transferred to the global bit lines M1 and M1' through the transistors Q11 and Q13.

At this time, since the global bit line is precharged to a high level, the level of the local bit line and the data signal loaded on this line is increased by a shared level at the same time.

That is, as shown in FIG. 3, the local bit line is increased by the shared level.

The global bit lines M1 and M1 'have a larger value of the read output voltage ΔV than the voltage of the local bit line under the control of the switch SW.

When the data signal thus raised is transmitted to the global bit line, it is amplified to a predetermined level through the sense amplifiers 107 and 108 and then output to the peripheral circuit.

Thereafter, the switch signal SW goes low and the precharge signal LBL Pre goes high, thereby turning on all transistors of the cell mat driver 103 and 104 to precharge the bit line.

In FIG. 3, (1) is a section for turning off precharge of a local bit line, (2) is an enable section for word line WL, (3) is a section for turning on switch SW, and (4) Is the section for turning on the sense amplifier.

Since the layout size is a global bit line in the present invention, chip size reduction is expected.

As described in detail above, the present invention has the effect of widening the operation in the low voltage region, improving the speed, and reducing the chip size by differentiating and driving the precharge voltages of the global bit line and the local bit line.

Claims (2)

A pair of local bit lines (MO, MO ') that read data from a cell mat consisting of cell blocks each storing data, and transfer the data to a pair of global bit lines M1 and M1'; The pair of local bit lines MO and MO 'are precharged to the reference voltage VBLR by a separate switch signal LBL Pre before the operation, and the data signals of the local bit lines are global bits by the switch SW. Precharges the first and second cell mat driving units to be transferred to the line and the pair of global bit lines M1 and M1 'with voltages V1 and V2 set higher than the reference voltage VBLR before operation. And a first and second sense amplifier driving unit. The operating area control circuit of claim 1, wherein the precharge voltage level of the sense amplifier driver is set to be higher than the precharge voltage level of the cell mat driver.