KR20010037611A - Solder ball having Fe/Ni core - Google Patents
Solder ball having Fe/Ni core Download PDFInfo
- Publication number
- KR20010037611A KR20010037611A KR1019990045240A KR19990045240A KR20010037611A KR 20010037611 A KR20010037611 A KR 20010037611A KR 1019990045240 A KR1019990045240 A KR 1019990045240A KR 19990045240 A KR19990045240 A KR 19990045240A KR 20010037611 A KR20010037611 A KR 20010037611A
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- iron
- solder ball
- nickel core
- semiconductor chip
- core
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
본 발명은 반도체 장치에 사용되는 접속 수단에 관한 것으로서, 더욱 상세하게는 반도체 칩과 외부 실장 수단과의 전기적 연결을 위하여 사용되는 솔더 볼에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to connection means used in semiconductor devices, and more particularly, to solder balls used for electrical connection between semiconductor chips and external mounting means.
반도체 소자의 집적도가 증가하면서 점점 더 많은 수의 입출력 핀이 요구되기 때문에 소자의 크기를 소형화하는 것이 중요하다. 그러나, 소형의 반도체 소자가 많은 입출력 핀을 가지게 되면 반도체 패키지의 리드 피치(lead pitch)가 너무 작아져서 패키지의 리드가 외부의 충격에 약해지고, 전기적인 기생 변수로 인한 칩의 성능 저하도 발생하며, 패키지의 취급에 세심한 주의가 필요하다는 문제점이 생긴다. BGA(Ball Grid Array) 패키지는 PGA(Pin Grid Array) 패키지에서 리드의 길이가 길기 때문에 발생할 수 있는 유도성 성분에 의한 부정적 요소를 배제하면서 입출력핀의 효율성이라는 장점을 취할 수 있는 형태의 패키지로서 많은 수의 리드가 필요한 소자에 적합하다.As the integration of semiconductor devices increases, more and more input and output pins are required, it is important to downsize the device. However, when a small semiconductor device has many input / output pins, the lead pitch of the semiconductor package becomes too small, so that the lead of the package is weak to external shocks, and chip performance is deteriorated due to electrical parasitic variables. The problem arises that the handling of the package requires careful attention. The ball grid array (BGA) package is a type of package that can take advantage of the efficiency of input / output pins while eliminating negative factors due to inductive components that may occur due to the long lead length in the pin grid array (PGA) package. Suitable for devices requiring a large number of leads.
한편, 보다 작고 가벼운 형태의 패키지에 대용량과 다기능을 갖는 반도체소자에 대한 요구가 늘어남에 따라 패키지 크기를 거의 반도체 칩 수준으로 극소화한 CSP(chip scale package)가 개발되었다. CSP는 소자의 크기를 획기적으로 줄여 전자기기의 소형 경량 대용량화 다기능화 등에 큰 역할을 하고 있다. 대부분의 CSP는 기존의 패키지와는 달리 리드프레임을 사용하지 않고 이를 대신하여 폴리이미드 테이프와 접속 단자로서 솔더 볼(solder ball)을 사용하여 패키지의 크기를 최소화하고 있다. 다음은 솔더 볼을 이용하여 반도체 칩이 인쇄회로기판에 직접 실장되는 플립 칩 본딩 기술을 소개하기로 한다.On the other hand, as the demand for semiconductor devices having large capacity and multifunction in smaller and lighter packages increases, a chip scale package (CSP) has been developed that minimizes the package size to almost a semiconductor chip level. CSP is playing a major role in reducing the size of devices and minimizing the size and weight of electronic devices. Unlike conventional packages, most CSPs do not use leadframes. Instead, polyimide tape and solder balls are used as connection terminals to minimize the size of the package. Next, a flip chip bonding technique in which a semiconductor chip is directly mounted on a printed circuit board using solder balls will be introduced.
도 1은 일반적인 플립 칩 본딩 기술에 의해 반도체 칩이 인쇄회로기판에 실장되어 있는 상태를 나타낸 개략도이다.1 is a schematic diagram showing a state in which a semiconductor chip is mounted on a printed circuit board by a general flip chip bonding technique.
도 1을 참조하면, 반도체 칩(21)이 직접 인쇄회로기판(25)에 솔더 볼(30)에 의해 실장되어 있다. 반도체 칩(21)의 각각의 전극패드(22) 위에 솔더 볼(30)이 부착되어 인쇄회로기판(25)과의 접속 수단으로서 사용된다. 여기서, 솔더 볼(30)은 주석/납(Sn/Pb)의 합금으로 이루어지며, 리플로우(reflow) 공정을 통해 반도체 칩(21)에 부착된다.Referring to FIG. 1, a semiconductor chip 21 is directly mounted on a printed circuit board 25 by solder balls 30. A solder ball 30 is attached to each electrode pad 22 of the semiconductor chip 21 to be used as a connection means with the printed circuit board 25. Here, the solder ball 30 is made of an alloy of tin / lead (Sn / Pb) and attached to the semiconductor chip 21 through a reflow process.
도 2a와 도 2b는 종래 기술에 따른 솔더 볼이 반도체 칩에 부착된 상태를 나타낸 개략 단면도로서, 도 2a는 범프(bump) 현상이 나타난 상태를 나타내 단면도이고, 도 2b는 크랙(crack)이 발생된 상태를 나타낸 단면도이다.2A and 2B are schematic cross-sectional views illustrating a solder ball attached to a semiconductor chip according to the prior art, and FIG. 2A is a cross-sectional view illustrating a bump phenomenon and FIG. 2B shows a crack. It is sectional drawing which showed the state.
도 2a를 참조하면, 종래의 솔더 볼(30)은 63Sn/37Pb 합금의 단일체로 구성되는 것이 일반적이다. 이러한 솔더 볼(30)은 반도체 칩(21)에 부착시키는 리플로우 공정(220℃, 1분)에서 열적 스트레스에 의해 솔더 볼(30)의 표면 거칠음(31)이나 범프 현상(32) 등을 발생시킬 수 있으며, 표면 거칠음(31)이나 범프 현상(32)은 인쇄회로기판(25)에 실장시 솔더 볼(30) 내부에 보이드(void)를 유발시켜 품질에 대한 신뢰성을 저하시키는 원인이 된다.Referring to FIG. 2A, a conventional solder ball 30 is generally composed of a single piece of 63Sn / 37Pb alloy. The solder ball 30 generates surface roughness 31, bump phenomenon 32, etc. of the solder ball 30 by thermal stress in a reflow process (220 ° C., 1 minute) attached to the semiconductor chip 21. The surface roughness 31 or the bump phenomenon 32 may cause voids in the solder ball 30 when the PCB 25 is mounted on the printed circuit board 25, thereby causing a decrease in reliability of quality.
도 2b를 참조하면, 종래의 솔더 볼(30)은 리플로우 공정으로 솔더 볼(30)이 반도체 칩(21)에 부착된 상태에서 반도체 완성품을 일정한 온도조건을 가하여 외부 스트레스(stress)의 저항 능력을 평가하는 신뢰성 평가시 가해지는 열적 스트레스에 의해 솔더 볼(30) 자체에 크랙(34) 발생으로 전기적으로 개방되는 불량을 발생시킬 수 있다.Referring to FIG. 2B, the conventional solder ball 30 is capable of resisting external stress by applying a constant temperature condition to a semiconductor finished product in a state in which the solder ball 30 is attached to the semiconductor chip 21 by a reflow process. Due to the thermal stress applied during the reliability evaluation for estimating the reliability, cracks may be generated in the solder ball 30 itself due to cracks 34.
이상 소개한 바와 같이 반도체 칩과 인쇄회로기판을 연결하기 위한 전도체 역할을 하는 종래의 솔더 볼은 주석/납의 합금의 단일체로 구성되기 때문에 강도가 약하고 열적 스트레스에 의한 변형이 심하며, 반도체 제품의 신뢰성 평가시 가해지는 열적 스트레스에 의해 크랙이 발생되어 개방 또는 단락 불량을 유발시킬 수 있는 문제점을 내재하고 있다. 기술의 발달에 따른 솔더 볼의 사용이 더욱 더 증대되고 있는 시점에 있어서 접착력과 강도가 향상된 구조의 솔더 볼의 필요성이 대두되고 있다.As described above, the conventional solder ball, which serves as a conductor for connecting the semiconductor chip and the printed circuit board, is composed of a single alloy of tin / lead alloy, and thus has low strength, severe deformation due to thermal stress, and reliability evaluation of semiconductor products. There is a problem in that cracks are generated by the thermal stress applied, which can cause open or short circuit defects. As the use of solder balls increases with the development of technology, there is a need for solder balls with improved adhesion and strength.
본 발명의 목적은 강도와 접착력이 향상되고 열적 스트레스에 의한 변형이 최소화될 수 있는 구조를 갖는 반도체 장치에 사용되는 접속 수단을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a connection means for use in a semiconductor device having a structure in which strength and adhesion are improved and deformation due to thermal stress can be minimized.
도 1은 일반적인 플립 칩 본딩(flip chip bonding) 기술에 의해 반도체 칩이 인쇄회로기판에 실장되어 있는 상태를 나타낸 개략도,1 is a schematic diagram showing a state in which a semiconductor chip is mounted on a printed circuit board by a general flip chip bonding technique;
도 2a와 도 2b는 종래 기술에 따른 솔더 볼(solder ball)이 반도체 칩에 부착된 상태를 나타낸 개략 단면도로서,2A and 2B are schematic cross-sectional views showing a state in which a solder ball according to the prior art is attached to a semiconductor chip;
도 2a는 범프(bump) 현상이 나타난 상태를 나타내 단면도,2A is a cross-sectional view illustrating a state in which a bump phenomenon occurs;
도 2b는 크랙(crack)이 발생된 상태를 나타낸 단면도,2b is a cross-sectional view showing a state in which a crack is generated;
도 3은 본 발명에 따른 철/니켈 코어(Fe/Ni core) 솔더 볼의 구조를 나타낸 단면도,3 is a cross-sectional view showing a structure of an iron / nickel core (Fe / Ni core) solder ball according to the present invention;
도 4는 본 발명에 따른 철/니켈 코어 솔더 볼이 반도체 칩에 부착된 상태를 나타낸 단면도이다.4 is a cross-sectional view illustrating a state in which an iron / nickel core solder ball according to the present invention is attached to a semiconductor chip.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 철/니켈 코어 솔더 볼 11; 철/니켈 코어10; Iron / nickel core solder ball 11; Iron / nickel core
12; 솔더 코팅층 21; 반도체 칩12; Solder coating layer 21; Semiconductor chip
22; 전극패드 23; 패시베이션막22; Electrode pads 23; Passivation film
24; 폴리이미드막 25; UBM막24; Polyimide membrane 25; UBM film
30; 솔더 볼 31; 표면 거칠음30; Solder ball 31; Surface roughness
32; 범프 현상 34; 크랙(crack)32; Bump phenomenon 34; Crack
이와 같은 목적을 달성하기 위한 본 발명에 따른 철/니켈 코어 솔더 볼은 반도체 칩의 전극패드에 부착되는 접속 수단으로서, 철/니켈 코어(Fe/Ni core)의 외주면에 주석/납의 코팅층이 형성되어 있는 것을 특징으로 한다.Iron / nickel core solder ball according to the present invention for achieving the above object is a connecting means attached to the electrode pad of the semiconductor chip, the coating layer of tin / lead is formed on the outer peripheral surface of the iron / nickel core (Fe / Ni core) It is characterized by being.
이하 첨부 도면을 참조하여 본 발명에 따른 철/니켈 코어 솔더 볼을 보다 상세하게 설명하고자 한다.Hereinafter, an iron / nickel core solder ball according to the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 철/니켈 코어 솔더 볼의 구조를 나타낸 단면도이고, 도 4는 본 발명에 따른 철/니켈 코어 솔더 볼이 반도체 칩에 부착된 상태를 나타낸 단면도이다.3 is a cross-sectional view showing the structure of the iron / nickel core solder ball according to the present invention, Figure 4 is a cross-sectional view showing a state in which the iron / nickel core solder ball according to the invention attached to a semiconductor chip.
도 3과 도 4를 참조하면, 본 발명의 철/니켈 코어 솔더 볼(10)은 기존의 솔더 볼에 비해 외부의 열적 스트레스에 대한 저항력이 우수한 재질인 철/니켈 코어(11)의 외주면에 주석/납 합금의 솔더 코팅층(11)을 형성한 형태로 구성된다. 철/니켈 코어(11)가 열적 스트레스에 대한 저항력이 종래에 비하여 우수하여 크랙의 발생 가능성이 없으며 모양 변형이 발생하지 않는다. 철/니켈 코어(11)의 크기와 주석/납 합금의 솔더 코팅층(12)의 두께는 필요에 따라 적당하게 조절하여 제작하면 된다. 여기서, 솔더 코팅층(12)의 형성에는 용융 도금이나 전기 도금이 사용될 수 있다.3 and 4, the iron / nickel core solder ball 10 of the present invention is a tin on the outer circumferential surface of the iron / nickel core 11, which is a material excellent in resistance to external thermal stress compared to the conventional solder ball The solder coating layer 11 of the lead alloy is formed. The iron / nickel core 11 has better resistance to thermal stress than the conventional one, so there is no possibility of cracking and shape deformation does not occur. The size of the iron / nickel core 11 and the thickness of the solder / coating layer 12 of the tin / lead alloy may be appropriately adjusted and manufactured as necessary. Here, hot dip plating or electroplating may be used to form the solder coating layer 12.
철/니켈 코어 솔더 볼(10)의 부착 과정을 설명하기로 한다. 반도체 칩(21)에는 집적회로를 보호하기 위하여 패시베이션막(23)이 형성되어 있고, 그 상부에 다시 폴리이미드막(24)이 형성되어 있다. 그리고, 전극패드(22)와 접합되도록 하여 형성된 UBM(Under Bumped Metal)막(25)이 형성되어 있다. 반도체 칩(21)의 전극패드(22)와 접합된 UBM막(25)에 철/니켈 코어의 외주면에 솔더 코팅층(12)이 형성된 철/니켈 코어 솔더 볼(10)을 올려놓은 상태에서 리플로우(reflow)를 실시하면 철/니켈 코어(11)의 외주면에 형성된 솔더 코팅층(12)이 용융되어 UBM막(25)과 접합되며, 용융된 솔더 코팅층(12)이 경화되면 철/니켈 코어 솔더 볼(10)과 전극패드(22)가 전기적으로 도통되는 상태가 된다. 이때, 철/니켈 코어(11)가 솔더 코팅층(12)의 내부에 위치하기 때문에 강도가 강화되어 접합력을 향상시킬 수 있으며, 더욱이 철/니켈 코어(11)와 솔더 코팅층(12)간에도 미세한 결합이 이루어져 강도가 향상된다.The attaching process of the iron / nickel core solder ball 10 will be described. The passivation film 23 is formed in the semiconductor chip 21 to protect the integrated circuit, and the polyimide film 24 is formed on the semiconductor chip 21 again. An UBM (Under Bumped Metal) film 25 formed to be bonded to the electrode pad 22 is formed. Reflow with the iron / nickel core solder ball 10 having the solder coating layer 12 formed on the outer circumferential surface of the iron / nickel core on the UBM film 25 bonded to the electrode pad 22 of the semiconductor chip 21. When reflow is performed, the solder coating layer 12 formed on the outer circumferential surface of the iron / nickel core 11 is melted and bonded to the UBM film 25. When the molten solder coating layer 12 is cured, the iron / nickel core solder ball is hardened. 10 and the electrode pad 22 are in an electrically conductive state. In this case, since the iron / nickel core 11 is located inside the solder coating layer 12, the strength may be enhanced to improve the bonding strength, and further, fine coupling may be performed between the iron / nickel core 11 and the solder coating layer 12. The strength is improved.
이상과 같은 본 발명에 의한 철/니켈 코어 솔더 볼에 따르면 강도와 접착력이 향상되고 열적 스트레스에 의한 변형을 최소화할 수 있어 크랙의 발생이나 범프 현상 및 표면 거칠음 등의 불량 발생을 방지하여 반도체 칩과 인쇄회로기판과의 접합에 대한 신뢰성을 향상시킬 수 있다.According to the iron / nickel core solder ball according to the present invention as described above, the strength and adhesion can be improved, and deformation due to thermal stress can be minimized, thereby preventing the occurrence of cracks, defects such as bumps, surface roughness, and the like. It is possible to improve the reliability of the bonding with the printed circuit board.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990045240A KR20010037611A (en) | 1999-10-19 | 1999-10-19 | Solder ball having Fe/Ni core |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990045240A KR20010037611A (en) | 1999-10-19 | 1999-10-19 | Solder ball having Fe/Ni core |
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| Publication Number | Publication Date |
|---|---|
| KR20010037611A true KR20010037611A (en) | 2001-05-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990045240A KR20010037611A (en) | 1999-10-19 | 1999-10-19 | Solder ball having Fe/Ni core |
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| KR (1) | KR20010037611A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101284363B1 (en) * | 2013-01-03 | 2013-07-08 | 덕산하이메탈(주) | Metal core solder ball and heat dissipation structure of semiconductor device using the same |
-
1999
- 1999-10-19 KR KR1019990045240A patent/KR20010037611A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101284363B1 (en) * | 2013-01-03 | 2013-07-08 | 덕산하이메탈(주) | Metal core solder ball and heat dissipation structure of semiconductor device using the same |
| WO2014106985A1 (en) * | 2013-01-03 | 2014-07-10 | Duksan Hi-Metal Co., Ltd. | Metal core solder ball and heat dissipation structure for semiconductor device using the same |
| TWI578418B (en) * | 2013-01-03 | 2017-04-11 | 德山金屬有限公司 | Metal core solder ball and heat dissipation structure of semiconductor device using the same |
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