KR20010028167A - Method of fabricating trench gate power MOSFET using sidewall spacer - Google Patents

Abstract

PURPOSE: A method for manufacturing a trench gate power device is provided to reduce the number of etching masks, by forming a source region after an N- well or P- well is formed by using a trench gate mask and a sidewall layer is formed to manufacture a trench gate. CONSTITUTION: After N- epi layer(2) is grown and an oxide layer is formed on an N+ silicon substrate, a portion for a trench gate is defined and etched to form a P- well(5). A layer for forming a sidewall layer and the trench gate is formed. After a portion of the sidewall layer is defined, the layer for the sidewall layer is etched to form the sidewall layer. The N- epi layer is etched by a depth deeper than that of the P- well to form the trench structure. After a gate oxide layer(9) is grown, a polycrystalline silicon thin film doped with impurities is deposited to fill a trench. The polycrystalline silicon thin film is anisotropically etched to form a polycrystalline gate structure(10). After the sidewall layer is removed, N+ impurity ions are implanted into the region where the sidewall layer is eliminated, to form a source region(11). The oxide layers(3,4) are etched and a field oxide layer(12) are grown. A portion where a source electrode(13) contacts a gate electrode is formed. After a metal layer is deposited to form the source electrode and the gate electrode, a drain electrode(14) is formed on a back side of the substrate.

Description

Method of fabricating trench gate power device using sidewall film {Method of fabricating trench gate power MOSFET using sidewall spacer}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low voltage high current power device used in a lithium ion secondary battery protection circuit, a DC-DC converter, a motor, and the like. In particular, the manufacturing process is simplified by using a sidewall film, and a highly integrated trench gate having low ON resistance characteristics. It relates to a power device manufacturing method.

In general, a power device using MOS (Metal Oxide Semiconductor) technology has a vertical double-diffused metal oxide semiconductor (VDMOS) having a vertical channel structure in which source-gate-drains are disposed vertically and a horizontally arranged source-gate-drain. LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) having a channel structure is classified. VDMOS can flow more current than LDMOS, so it is used in large current power devices. VDMOS can be divided into planar gate type and trench gate type. Trench gate type power devices can lower the on-resistance value, which is a major variable of power devices, by integrating more devices per unit area than planar gate type power devices, and have the advantage of allowing a large current to flow at a low driving voltage. For this reason, it is currently switching from planar gate type to trench gate type power devices.

Looking at the conventional conventional trench gate power device manufacturing method as shown in FIG.

That is, as shown in FIG. 1A, the oxide film 22 is first grown using the N− epilayer 21 / N + silicon substrate 20, and then a region in which the P-well is to be formed is defined using a P-well mask.

After the oxide film 22 in the region where the P-well is to be formed is etched, a 400 Å thick oxide film 23 is grown, implanted with impurities, and then heat treated to form the P-well 24.

Subsequently, impurities are ion-implanted using a source mask to form an N + source region 25 as shown in FIG. 1B, and then an oxide layer 26 is deposited. The oxide film 26 is etched after defining the portion where the trench gate is to be formed using the trench gate mask. Using the etched oxide film, a trench is formed deeper than the P-well depth, and then the gate oxide 27 is grown. Depositing a doped polycrystalline silicon thin film on the gate oxide film 27 and etching the polycrystalline silicon thin film anisotropically using a gate electrode mask to form the trench gate electrode 28, and then removing defects generated during the etching of the polycrystalline silicon thin film In order to grow a thin protective oxide film.

After depositing the field oxide layer 29 as shown in FIG. 1C, the gate and source electrode junction portions are defined using a junction mask, and the field oxide layer 29 is etched to open the source electrode junction portion. After depositing the metal thin film, a gate electrode and a source electrode 30 are formed using an electrode mask, and then a drain electrode 31 is formed on the back of the substrate.

As described above, a total of six masks (P-well masks, source masks, trench gate masks, gate electrode masks, junction masks, and electrode masks) may be used to manufacture the trench gate power devices according to the conventional trench gate power device manufacturing method. Is needed. If a P + impurity is ion implanted into the source region, one additional mask is required.

By the way, when the number of masks used is large, the manufacturing process is complicated and the productivity is low.

In addition, the use of a large number of masks increases the alignment error of the device, and thus there is a problem that high integration is difficult and the yield of the device is lowered.

Summary of the Invention An object of the present invention for solving the above-mentioned problems is to simplify the manufacturing process of the power device and to reduce the alignment error of the device by using a small number of masks, thereby improving the degree of integration, thereby improving on-resistance, which is a key variable of the power device It is an object of the present invention to provide a method for manufacturing a trench trench power device that is lowered.

1 is a step-by-step manufacturing process cross-sectional view of an N-channel trench gate power device by a conventional method

2 is a plan view of an N-channel trench gate power device according to an embodiment of the present invention;

3 is a cross-sectional view of a step-by-step manufacturing process of the N-channel trench gate power device according to an embodiment of the present invention

4 is a cross-sectional view of a part of a manufacturing process of an N-channel trench gate power device according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a part of a manufacturing process of an N-channel trench gate power device according to still another embodiment of the present invention; FIG.

6 is a cross-sectional view of an N-channel trench gate power device according to another embodiment of the present invention.

7 and 8 are cross-sectional views of a P-channel trench gate power device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawing

1: N + silicon substrate 2: N- epi layer

3: oxide film 4: oxide film

5: P-well region 6: silicon nitride film

7: oxide film 8: trench region

9 gate oxide film 10 trench gate electrode

11: N + source region 12: field oxide film

13 source electrode 14 drain electrode

1a: P + silicon substrate 2a: P- epi layer

2b: thin N- epi layer 2c: thin P- epi layer

3a: inclined oxide film 5a: N-well region

6a: silicon nitride film 11a: P + source region

20: N + silicon substrate 21: N- epi layer

22: oxide film 23: oxide film

24: P-well region 25: N + source region

26 oxide film 27 gate oxide film

28 trench gate electrode 29 field oxide film

30 source electrode 31 drain electrode

In the method of manufacturing a trench gate power device of the present invention for achieving the above object, a P-well (or N-well) is formed by growing an N- epi layer (or P- epi layer) on an N + (or P +) silicon substrate. A trench gate power device comprising a process of forming a trench structure, a process of forming a trench gate, a process of forming an N + (or P +) source region, and a process of forming a gate, source, and drain electrode. In the manufacturing method, a P-well (or N-well region) is first formed using a trench gate mask without using a P-well (or N-well) mask and a source mask, and then a trench structure and a trench gate are formed. It is characteristic that the manufacturing process is simplified by reducing the number of masks used by sequentially forming and forming source regions.

Another feature of the present invention is to form a P-well region (or N-well region) and an N + source region (or P + region) around the trench gate without using a mask, so that the lateral junction depth is automatically aligned, reducing alignment errors and high integration. This is to lower the on resistance, which is the main variable of the power device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

FIG. 2 is a plan view of an N-channel trench gate power device according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating a process of manufacturing the trench gate power device taken from the dotted line A of FIG. 2.

As shown in FIG. 3, the method of manufacturing the N-channel trench gate power device of the present embodiment is largely used to grow a N- epitaxial layer and form a P-well on an N + silicon substrate, and to form a sidewall film to be used as a mask. A second step of forming a necessary film, a third step of forming a trench structure by etching the film formed in the second step, using the mask as a mask, a fourth step of forming a trench gate, and removing the sidewall film Next, a fifth step of forming a source region and a sixth step of forming a gate, a source, and a drain electrode are performed.

A feature of the present embodiment is to form a trench gate before forming the source region, and to use a sidewall film made of a silicon nitride film and an oxide film when forming the trench structure to form the trench gate.

Each process is demonstrated in more detail.

In the first step, as shown in FIG. 3A, the N− epilayer 2 is grown on the N + silicon substrate 1 and the P-well 5 is formed.

To this end, first, an N- epitaxial layer 2 having a resistivity value of 0.5 to 1 µm and a thickness of 4 to 8 µm is grown on the N + silicon substrate 1 having a resistivity value of less than 0.004 µm.

Then, an oxide film 3 having a thickness of 4000 to 5000 kPa is grown in a thermoelectric furnace at 900 to 1100 ° C, and a photosensitive film is applied thereon. After the trench gate mask is used to define the portion where the trench gate is to be formed, the oxide film 3 is anisotropically etched by the plasma ion etching method and the photoresist film is removed.

An oxide film 4 having a thickness of 400 kPa is grown on the portion where the trench gate is to be formed. Thereafter, ion implantation was performed with BF ₂ at 160 KeV and 1 to 3E13 / cm ² , followed by heat treatment at 1000 to 1150 ° C. to form a P-well 5 having a depth of 1 to 2 μm in the N-epitaxial layer 2. do.

In the second process, as shown in FIG. 3B, the silicon nitride film 6 having a thickness of 1000 to 2000 GPa and the TEOS or LTO (Low) having a thickness of 2000 to 3000 GPa are formed on the etched oxide film 3 and the oxide film 4 having a thickness of 4000 to 5000 GPa. Temperature Oxide) The oxide film 7 is sequentially deposited.

In the third process, as shown in FIG. 3C, anisotropic etching is performed by plasma ion etching to form a sidewall film by leaving the TEOS or LTO oxide film 7 and the silicon nitride film 6 on the sidewall of the etched oxide film 3.

Using the formed sidewall TEOS or LTO oxide film 7 and the silicon nitride film 6 as a mask, the trench structure 8 is etched by etching the N-epitaxial layer 2 deeper than the depth of the P-well 5 by plasma ion etching. Form. Then, in order to remove the defects in the trench walls, a sacrificial oxide film having a thickness of 500 to 1000 에서 is grown and removed at 850 to 1100 ° C.

In the fourth step, as shown in FIG. 3D, the gate oxide film 9 having a thickness of 300 to 500 kW is grown, and then a polycrystalline silicon thin film doped with impurity P is deposited to fill the trench. After defining the portion where the gate electrode is to be formed using the gate electrode mask, the trench gate electrode 10 is formed by anisotropically etching the polycrystalline silicon thin film by plasma ion etching. Then, in order to remove defects generated during etching of the polycrystalline silicon thin film, an oxide film having a thickness of 2000 to 3000 Å is grown.

In the fifth process, as shown in FIG. 3E, the TEOS or LTO oxide film 7 and the silicon nitride film 6 forming the sidewall film are removed, and ion-implanted at 60 to 80 KeV and 3 to 5E15 / cm ² at P or As in place. The source region 11 is formed.

3F is a cross-sectional view illustrating a process of finally forming an electrode.

A protective oxide film with a thickness of 300 to 1000 GPa is grown, and then a field oxide film 12 with a thickness of 7000 to 8000 GPa is grown. After the source and gate electrode contact portions are formed using the electrode contact mask, a metal film is deposited, and then the source electrode 13 and the gate electrode are formed using the electrode mask, and the drain electrode 14 is formed on the back side of the substrate. . This produces a highly integrated N-channel trench gate power device.

Example 2

4 illustrates a method of manufacturing a trench gate power device according to another embodiment of the present invention, in which a sidewall film is formed by etching a film formed in a second process and a second process of forming a film required for forming a sidewall film to be used as a mask. Only the cross section of the 3rd process of forming a trench structure using a mask is shown. All remaining steps are the same as in Example 1.

A feature of this embodiment is to use a silicon nitride film as the sidewall film to be used as a mask when forming the trench structure.

It demonstrates in detail centering on 2nd process and 3rd process different from Example 1. FIG.

In the first step, the trench gate is formed after sequentially growing the N− epi layer 2 and the oxide film 3 on the N + silicon substrate 1 as in FIG. Etch the part to be Next, the oxide film 4 is grown in the etched place, and the P-well 5 is formed using the remaining etched oxide film 3 as a mask.

Next, in the second process, a silicon nitride film 6a having a thickness of 3000 to 5000 kPa is deposited on the oxide film 3 having a thickness of 4000 to 5000 kPa remaining after etching as shown in FIG. 4A.

That is, unlike the deposition of the silicon nitride film 6 having a thickness of 1000 to 2000 mm 3 and the TEOS or LTO oxide film 7 having a thickness of 2000 to 3000 mm 3 on the oxide film 3 having a thickness of 4000 to 5000 mm 3 etched in Example 1, In this embodiment, the silicon nitride film 6a is deposited to the extent that the thickness of the silicon nitride film 6 and the TEOS or LTO oxide film 7 in Example 1 are combined.

In the third process, as shown in FIG. 4B, an anisotropic etching is performed by plasma ion etching to form a sidewall film by leaving the silicon nitride film 6a on the sidewall of the oxide film 3 remaining after etching.

Using the formed sidewall silicon nitride film 6a as a mask, the trench structure 8 is formed by etching the N- epi layer 2 deeper than the depth of the P-well 5 by plasma ion etching. Then, in order to remove the defects in the trench walls, a sacrificial oxide film having a thickness of 500 to 1000 에서 is grown and removed at 850 to 1100 ° C.

Thereafter, a fourth process of forming a trench gate, a fifth process of removing a sidewall film and then a source region, and a sixth process of forming a source and a drain electrode are performed in the same manner as in Example 1, thereby performing a highly integrated N-channel trench gate. Manufacture a power device.

Example 3

FIG. 5 illustrates a method of manufacturing a trench gate power device in accordance with still another embodiment of the present invention. A cross-sectional view after performing a second step of forming a film required for formation and a third step of forming a trench structure by etching the film formed in the second step and using this as a mask is shown. The rest of the process is the same as in Example 1.

A feature of this embodiment is that the oxide film to be used as a mask is etched inclined at a predetermined angle when forming the P-well in the first step.

The first to third processes of this embodiment will be described in detail.

In the first step, first, an N- epitaxial layer 2 having a specific resistance of 0.5 to 1 µm and a thickness of 4 to 8 µm is grown on the N + silicon substrate 1 having a specific resistance of less than 0.004 µm.

Next, an oxide film 3 having a thickness of 4000 to 5000 kPa is grown in a thermoelectric furnace at 900 to 1100 ° C., a photoresist is applied thereon, and a portion of the trench gate is defined using a trench gate mask.

Next, the oxide film 3 is anisotropically etched at an angle of 45 to 85 ° by a plasma ion etching method and the photoresist film is removed.

An oxide film 4 having a thickness of 400 kPa is grown on the portion where the trench gate is to be formed. Thereafter, ion implantation was performed with BF ₂ at 160 KeV and 1 to 3E13 / cm ² , followed by heat treatment at 1000 to 1150 ° C. to form a P-well 5 having a depth of 1 to 2 μm in the N-epitaxial layer 2. do.

In the second step, a silicon nitride film 6a having a thickness of 3000 to 5000 kPa is deposited on the obliquely etched oxide film 3.

Subsequently, in the third process, the silicon oxide film 6a is anisotropically etched by plasma ion etching to leave the silicon nitride film 6a on the inclined sidewall to form the sidewall film. Using the formed sidewall silicon nitride film 6a as a mask, the trench structure 8 is formed by etching the N- epi layer 2 deeper than the depth of the P-well 5 by plasma ion etching.

Next, the fourth process of forming the trench gate, the fifth process of removing the sidewall layer and then the source region, and the sixth process of forming the gate, source and drain electrodes were performed in the same manner as in Example 1 to obtain a highly integrated N-channel. A trench gate power device is manufactured.

Example 4

6 is a cross-sectional view of an N-channel trench gate power device according to another embodiment of the present invention.

In the present embodiment, the trench gate power device is manufactured in the same process order as any one of the above-described embodiments 1 to 3 showing the method of manufacturing the N-channel trench gate power device.

However, in the first step, instead of the N- epi layer (2) / N + silicon substrate (1), a silicon substrate in which a thin N- epi layer (2b) having a thickness of 2-3 m is grown on the N + silicon substrate (1) is used. do.

Further, when the trench structure 8 is formed in the third step, the trench structure 8 is etched to the N + silicon substrate 1 deeper than the thin N- epi layer 2b.

When the thin N- epi layer 2b having a thickness of 2 to 3 μm is used as in this embodiment, the breakdown voltage of the trench gate power device is reduced, but the resistance of the drift region can be reduced, thereby reducing the on-resistance, which is a main variable of the power device. Can be lowered.

Example 5

7 is a cross-sectional view of a P-channel trench gate power device according to another embodiment of the present invention.

In the present embodiment, the trench gate power device is manufactured in the same process order as any one of the above-described embodiments 1 to 3 showing the method of manufacturing the N-channel trench gate power device.

However, in the first step, P- epi layer 2a / P + silicon substrate 1a is used instead of N- epi layer 2 / N + silicon substrate 1.

In addition, as illustrated in FIG. 7, P ⁺ or As ⁺ ions are implanted to form the N-well 5a, and then BF ₂ ions are implanted to form the P + source region 11a.

Example 6

8 is a cross-sectional view of a P-channel trench gate power device according to another embodiment of the present invention.

In this embodiment, the trench gate power device is manufactured in the same process sequence as in the fifth embodiment.

However, in the first step, instead of the P- epi layer 2a / P + silicon substrate 1a, a silicon substrate with a thin P- epi layer 2c having a thickness of 2-3 m on the P + silicon substrate 1a is used. .

Further, when the trench structure 8 is formed in the third step, the trench structure 8 is etched to the P + silicon substrate 1a deeper than the thin P− epi layer 2c.

As described above, the present invention uses the trench gate mask to form an N-well (or P-well), and then forms a sidewall film to form a trench gate, and then forms a source region (four sheets). By reducing trench gates, gate electrodes, junctions and electrode masks, and simplifying the manufacturing process, productivity can be improved and manufacturing costs can be lowered.

In addition, by using a small number of masks, the alignment error of the device is reduced, resulting in high integration, thereby reducing the on-resistance, which is a main variable of the power device.

The technical spirit of the present invention has been described above with reference to the accompanying drawings, but this is by way of example only and not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (8)

After growing the N- epi layer 2 on the N + silicon substrate 1 and growing the oxide film 3, the trench gate mask is used to define the portion where the trench gate is to be formed, and then the portion where the trench gate is to be formed is etched. A first step of forming a P-well 5 using the remaining oxide film 3 as a mask; A second step of growing a film necessary for forming a sidewall film to be used as a mask when forming a trench structure and a trench gate; After defining the portion where the sidewall film is to be formed, the sidewall film is formed by etching the film grown in the second process, and the N-epitaxial layer 2 is etched deeper than the depth of the P-well 5 using the mask to form the trench structure (8). Forming a third process; A fourth step of growing the gate oxide film 9, depositing a polycrystalline silicon thin film doped with impurities to fill the trench, and then etching the polycrystalline silicon thin film anisotropically to form the polycrystalline silicon gate electrode 10; A fifth step of removing the sidewall film and then ion implanting impurity N + into the source to form the source region 11; After etching the oxide films 3 and 4, the field oxide film 12 is grown, the source and gate electrode contact portions are formed, and then a metal film is deposited to form the source electrode 13 and the gate electrode, and then the back of the substrate. And a sixth step of forming a drain electrode (14) in the trench. After growing the P- epi layer 2a on the P + silicon substrate 1a and growing the oxide film 3, the trench gate mask is used to define the portion where the trench gate is to be formed, and then the portion where the trench gate is to be formed is etched. A first step of forming an N-well 5a using the remaining oxide film 3 as a mask; A second step of growing a film necessary for forming a sidewall film to be used as a mask when forming a trench structure and a trench gate; After defining the portion where the sidewall film is to be formed, the sidewall film is formed by etching the film grown in the second process, and using the mask as a mask, the P-epi layer 2a is etched deeper than the depth of the N-well 5a to form a trench structure (8). Forming a third process; A fourth step of growing the gate oxide film 9, depositing a polycrystalline silicon thin film doped with impurities to fill the trench, and then etching the polycrystalline silicon thin film anisotropically to form the polycrystalline silicon gate electrode 10; A fifth step of removing the sidewall film and then ion implanting impurity P + in place to form the source region 11a; After etching the oxide films 3 and 4, the field oxide film 12 is grown, the source and gate electrode contact portions are formed, and then a metal film is deposited to form the source electrode 13 and the gate electrode, and then the back of the substrate. And a sixth step of forming a drain electrode (14) in the trench. The method according to claim 1 or 2, Fabrication of a trench gate power device, characterized in that the silicon nitride film 6 and the oxide film 7 are sequentially deposited by forming a sidewall film to be used as a mask when forming a trench structure and a trench gate. Way. The method of claim 3, And the oxide film (7) is a TEOS or LTO oxide film. The method according to claim 1 or 2, The trench structure grown in the second process and the sidewall film to be used as a mask when forming the trench gate are silicon nitride films (6a). The method according to claim 1 or 2, A method for manufacturing a trench gate power device, characterized in that the oxide film (3) to be used as a mask is etched at an angle at a predetermined angle when the wells (5) (5a) are formed in the first step. The method of claim 6, A method of manufacturing a trench gate power device, characterized in that the etching angle of the oxide film (3) is 45 to 85 degrees. The method according to claim 1 or 2, In the first step, a thin N- epi layer 2b or a thin P- epi layer 2c is grown on the silicon substrate 1, 1a with a thickness of 2 to 3 탆, In the third process, the trench structure (8) is formed by etching deeper than the thin epitaxial layer (2b) (2c) to the silicon substrate (1) (1a).