KR20010025799A - Random access memory device using prefetch method - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to minimize load and the number of a data line as preventing each of a plurality of memory cell array blocks from sharing an inner data line with different memory cell array blocks. CONSTITUTION: The memory device includes N memory cell array blocks(BLOCK1,BLOCK2,BLOCK3,BLOCK4), MxN sense amps, M data outputting portions(11-18), MxK data lines for reading, M data inputting portions, MxK write drivers and MxK data lines for writing. The sense amps one by one amplify MxK data which is simultaneously read from the N memory cell array blocks and then output. The M data outputting portions temporarily latch MxK output data of the sense amps transmitted by K output data and then sequentially output by one at one time through K times. The MxK data lines connect the sense amps and the data outputting portions with K:1 and transmit MxK output data of the sense amps to the data output portions by K output data. The data inputting portions latch a data, which are sequentially inputted by one at one time through K times, simultaneously to be written to the N memory cell array blocks and then simultaneously output. The write drivers, to which MxK output data of the data inputting portion are transmitted by one, simultaneously write to the memory cell array blocks. The data lines for writing connect the M data inputting portions and the MxK write drivers with 1:K and transmit MxK output data of the data inputting portions to the write drivers by one.

Description

Semiconductor access memory device using prefetch method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device using a prefetch method.

In accordance with the high performance of the microprocessor, the speed of the semiconductor memory device (cache SRAM) has been required, and in order to solve this problem, in the case of a write operation, after receiving some data to be written in advance, the memory cell array is written in parallel and a read operation is performed. BACKGROUND OF THE INVENTION [0002] A semiconductor memory device using a prefetch method that reads some data from a memory cell array in advance and outputs it sequentially has been developed.

In addition, with the advent of semiconductor memory devices having wide I / O buses such as x64, x72, x128, x144, and the like, the I / O bus structure of the semiconductor memory device to which the prefetch method is applied is complicated. That is, the number of data lines required internally in a semiconductor memory device employing the prefetch method increases the number of I / O buses because K × P corresponds to the product of the prefetch number K and the number of I / O buses P. The more the number of internal data lines increases.

As a result, the semiconductor memory device using the prefetch method according to the prior art increases the number of internal data lines by a prefetch number of K times compared to the semiconductor memory device without the prefetch method. there was.

In addition, in the semiconductor memory device using the prefetch method according to the prior art, since a plurality of memory cell array blocks share internal data lines, there is a problem in that a sensing power is large because a load of the data line is large.

Accordingly, the present invention provides a semiconductor memory device using a prefetching method in which a load of a data line is minimized and the number of data lines is minimized by not allowing each of the plurality of memory cell array blocks to share internal data lines with other memory cell array blocks. The purpose is to provide.

In order to achieve the above object, the semiconductor memory device using the prefetch method according to the present invention amplifies N memory cell array blocks and M × K data read simultaneously from the N memory cell array blocks one by one. M × K sense amplifiers to output and M × K output data of the sense amplifiers are received and temporarily latched by K, and M data output units sequentially output one time at a time K times. And M × K pieces of M × K output data of the sense amplification parts, which are transmitted K-by-K to the data output parts by connecting the M × K sense amplification parts and the M data output parts in a K: 1 correspondence. The data lines for read and the data to be simultaneously written to the N memory cell array blocks are sequentially input and temporarily latched one K time at a time. M data input parts outputting at the time, M × K write drivers receiving M × K output data of the data input parts one by one, and writing the same to the N memory cell array blocks simultaneously; M × K write data lines for connecting the M × K write drivers to the write drivers by passing the M × K output data to the write drivers one by one. It is characterized by.

Each of the M data output units latches K data received through K read data lines of the M × K read data lines one by one and sequentially outputs the K data sequentially at different times. And a data output buffer for buffering and outputting the output data of the K read switch units, wherein each of the M data input units has K data to be simultaneously written to the memory cell array block. The data input buffer sequentially buffering and outputting K times one at a time, and the output data of the data input buffer are received and latched one by one, and then K light data of the M × K light data lines is latched. It is preferable that the switch is composed of K light switches which simultaneously output the lines.

1A and 1B are a partial block diagram of a semiconductor memory device to which a prefetch method according to an example of the prior art is applied;

2A and 2B are partial block diagrams of a semiconductor memory device to which the prefetch method is applied according to an embodiment of the present invention.

First, a description will be given of a semiconductor memory device to which the prefetch method according to an example of the related art compared with an embodiment of the present invention is applied.

1A and 1B are partial block diagrams of a semiconductor memory device to which a prefetching scheme according to the prior art is applied. In FIG. 1A, components corresponding to read paths are illustrated in FIG. 1B, respectively. Is shown. The semiconductor memory device illustrated in FIGS. 1A and 1B is a semiconductor memory device having eight I / O buses and two prefetches.

As shown in FIGS. 1A and 1B, a semiconductor memory device employing a prefetch method according to an example of the related art includes four memory cell array blocks BLOCK1 to BLOCK4 and 64 Y-pass gates Y1 to Y64. ), 64 sense amplifiers SA1 to SA64, 16 read data lines MDL1 'to MDL16', 16 read multiplexers RM1 to RM16, and 8 data output buffers. (DOB1 to DOB8), eight data input buffers (DIB1 to DIB8), 16 write multiplexers (WM1 to WM16), 16 write data lines (DIN1 'to DIN16'), 64 Four write drivers WD1 to WD64.

The four memory cell array blocks BLOCK1 to BLOCK4 are composed of a plurality of memory cells connected between a plurality of orthogonal word lines and a plurality of bit line pairs to store data.

The 64 Y-pass gates Y1 to Y64 are connected to the four memory cell array blocks BLOCK1 to BLOCK4 in a 1:16 correspondence, and are read from one memory cell array block in response to an external address. 16 data may be selectively transferred to the corresponding sense amplifiers, or output data of the corresponding write drivers may be selectively transferred to the memory cell array blocks BLOCK1 to BLOCK4.

The 64 sense amplifiers SA1 to SA64 are connected in one-to-one correspondence to the 64 Y-pass gates Y1 to Y64 so that only 16 are selectively driven during a read operation. In this case, the sixteen sense amplifiers driven are amplified and outputted one by one from sixteen data read simultaneously from one memory cell array block.

The 16 read data lines MDL1 to MDL16 are arranged in a horizontal direction as shown in FIG. 1A, and 16 sense amplifiers corresponding to one memory cell array block are connected in a one-to-one correspondence. Sixteen lead multiplexers RM1 to RM16 are connected in a one-to-one correspondence. The 16 read data lines MDL1 to MDL16 transfer output data of 16 sense amplifiers that are selectively driven to the 16 read multiplexers RM1 to RM16.

The 16 read multiplexers RM1 to RM16 temporarily latch 16 data transmitted through the 16 read data lines MDL1 to MDL16 and then 8 read multiplexers RM1, RM3, and RM5. , RM7, RM9, RM11, RM13, and RM15 and eight lead multiplexers RM2, RM4, RM6, RM8, RM10, RM12, RM14, and RM16 turn on and output the latched data.

The eight data output buffers DOB1 to DOB8 buffer the output data of the read multiplexers RM1 to RM16 and transfer them to eight input / output pads (not shown).

The eight data input buffers DIB1 to DIB8 output 16 data input twice in eight through eight input / output pads in the order of input.

The sixteen write multiplexers WM1 to WM16 temporarily latch data input one by one from the data input buffers DIB1 to DIB8 and output them simultaneously.

The sixteen light data lines DIN1 'to DIN16' are arranged in a horizontal direction as shown in FIG. 1A, and the sixteen light multiplexers WM1 to WM16 are connected in a one-to-one correspondence. Sixteen write drivers corresponding to one memory cell array block are connected in a one-to-one correspondence. The sixteen write data lines DIN1 'to DIN16' transfer output data of the sixteen write multiplexers WM1 to WM16 to one of sixteen write drivers selectively driven.

The 64 write drivers WD1 to WD64 are connected to the 64 Y-pass gates Y1 to Y64 in a one-to-one correspondence so that only 16 are selectively driven during the write operation. At this time, the 16 write drivers driven transmit 1 write data received through the 16 write data lines DIN1 'to DIN16' one by one memory cell through the 16 Y-pass gates Y1 to Y16. Write to the array block at the same time.

The operation of the semiconductor memory device to which the prefetch method according to the example of the related art configured as described above will be described as follows.

First, in the read operation, 16 data simultaneously read from one memory cell array block in response to an external address are transferred to corresponding sense amplifiers through 16 Y-pass gates of 64 Y-pass gates Y1 to Y64. The sixteen sense amplifiers that receive the read data and amplify the corresponding data output one by one to the sixteen read data lines MDL1 'to MDL16'.

Thereafter, the 16 read data are transferred to the 16 read multiplexers RM1 to RM16 through the read data lines MDL1 'to MDL16', and the 16 read multiplexers RM1 to RM16 are connected to each other. The received data is latched one by one, and eight of the read multiplexers RM1, RM3, RM5, RM7, RM9, RM11, RM13, and RM15 are first turned on to latch the data that has been latched. One to DOB1 to DOB8, and then the eight lead multiplexers RM1, RM3, RM5, RM7, RM9, RM11, RM13, and RM15 are turned off and the remaining eight multiplexers RM2, RM4, RM6, RM8, RM10, RM12, RM14, and RM16 are turned on to transfer the latched data to the eight data output buffers DOB1 to DOB8, and the data output buffers DOB1 to DOB8 are read multiplexers. 8 data and read multi data from RM1, RM3, RM5, RM7, RM9, RM11, RM13, RM15) Eight data received from the Lexus (RM2, RM4, RM6, RM8, RM10, RM12, RM14, RM16) sequentially conveys the eight IO pad twice.

Next, during the write operation, the eight data input buffers DIB1 to DIB8 receive eight data input through the eight input / output pads and eight write multiplexers WM1, WM3, WM5, WM7, WM9, WM11, WM13, WM15), and then the eight data input through the eight input / output pads are transferred to the remaining eight write multiplexers (WM2, WM4, WM6, WM8, WM10, WM12, WM14, and WM16). The sixteen write multiplexers WM1 to WM16 latch the data received from the eight data input buffers DIB1 to DIB8 one by one, and simultaneously to the sixteen write data lines DIN1 'to DIN16'. Output Thereafter, the 16 write drivers selectively driven among the 64 write drivers WD1 to WD64 are connected to the 16 data received through the 16 write data lines DIN1 'to DIN16'. Write to one memory cell array block simultaneously through Y-pass gates.

However, in the semiconductor memory device applying the prefetch method according to the related art constructed and operated as described above, the number of read data lines and write data lines is increased by K times as compared to the semiconductor memory device without the prefetch method. As a result, the chip size is increased, and the memory cell array blocks share the read data lines and the write data lines.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention solved the above problems will be described in detail.

2A and 2B are partial block diagrams of a semiconductor memory device to which the prefetch method is applied according to an embodiment of the present invention. In FIG. 2A, components corresponding to the read paths are illustrated in FIG. 2B. Are respectively shown. The semiconductor memory device shown in FIGS. 2A and 2B is a semiconductor memory device having 8 I / O buses and 2 prefetches.

In the semiconductor memory device using the prefetch method according to an embodiment of the present invention, four memory cell array blocks BLOCK1 to BLOCK4 and 16 Y-pass gates Y1 are illustrated in FIGS. 2A and 2B. To Y16, 16 sense amplifiers SA1 to SA16, 8 data outputs 11 to 18, 16 read data lines MDL1 to MDL16, and 8 data inputs 21 28, 16 write drivers WD1 to WD16, and 16 write data lines DIN1 to DIN16.

The four memory cell array blocks BLOCK1 to BLOCK4 are composed of a plurality of memory cells connected between a plurality of orthogonal word lines and a plurality of bit line pairs to store data. In addition, all four memory cell array blocks BLOCK1 to BLOCK4 are always selected and activated regardless of the external block address.

The sixteen Y-pass gates Y1 to Y16 are connected to four memory cell array blocks BLOCK1 to BLOCK4 in a 1: 4 correspondence, and are simultaneously activated in response to an external address. 16 pieces of data read from the blocks BLOCK1 to BLOCK4 are input and transferred to the 16 sense amplifiers SA1 to SA16 one by one, or the output data of the 16 write drivers WD1 to WD16 is output to 4 memory cell array blocks. To BLOCK1 to BLOCK4. In the read operation, four pieces of data are read per memory cell array block.

The sixteen sense amplifiers SA1 to SA16 are connected in one-to-one correspondence to the sixteen Y-pass gates Y1 to Y16 to amplify the read data transferred through the Y-pass gates Y1 to Y16 one by one. Output

The eight data output units 11 to 18 receive and temporarily latch two pieces of 16 output data of the sense amplifiers SA1 to SA16 and output them sequentially two times at a time. Each consists of two read multiplexers RM and one data output buffer DOB. For example, the two read multiplexers RM1 and RM2 included in the data output unit 11 latch two pieces of data transmitted through the two read data lines MDL1 and MDL2 one by one. The data is sequentially output at different times, and the data output buffer DOB1 buffers the output data of the two read multiplexers RM1 and RM2 to the input / output pad (not shown), and the remaining data output units. The read multiplexers (12-18) and the data output buffer also play the same role.

The 16 read data lines MDL1 to MDL16 connect the 16 sense amplifiers SA1 to SA16 and the eight data output parts 11 to 18 in a 2: 1 correspondence as shown in FIG. 2A. 16 output data of the sense amplifiers SA1 to SA16 are transmitted to the data output units 11 to 18, respectively. More specifically, the 16 read data lines MDL1 to MDL16 are connected in a one-to-one correspondence with the 16 read multiplexers RM1 to RM16 provided in the data output units 11 to 18 and 16 sense amplifiers. The output data of SA1 to SA16 are transferred to the 16 read multiplexers RM1 to RM16 one by one. Here, the lead data lines MDL1 to MDL16 shown in FIG. 2A are compared with the lead data lines MDL1 'to MDL16' shown in FIG. 1A. MDL16 'is disposed in the horizontal direction in the drawing and is shared by four memory cell array blocks BLOCK1 to BLOCK4, while the read data lines MDL1 to MDL16 of the present invention are 4 per memory cell array block. Read data lines are dedicated and are not shared by other memory cell array blocks. As a result, the load data lines MDL1 to MDL16 of the present invention are significantly reduced in load compared to the read data lines MDL1 'to MDL16' of the prior art, thereby reducing sensing power. In addition, horizontal read data lines shared between each memory cell array block may be removed.

The eight data input units 21 to 28 sequentially receive and temporarily latch data to be written to four memory cell array blocks BLOCK1 to BLOCK4 two times, one at a time. In this case, one data input buffer DIB and two write multiplexers WM are included. For example, the data input buffer DIB1 included in the data input unit 21 sequentially buffers two data to be simultaneously written to the memory cell array block BLOCK1, one at a time through the input / output pad, twice. And the two light multiplexers WM1 and WM2 receive and latch the output data of the data input buffer DIB1 one by one and simultaneously output them to the two light data lines DIN1 and DIN2. The data input buffers of the remaining data input units 22 to 28 and the multiplexers for writing also play the same role.

The sixteen write drivers WD1 to WD16 receive sixteen output data of the data input units 21 to 28 one by one and four memory cell array blocks through the sixteen Y-pass gates Y1 to Y16. Writes simultaneously to (BLOCK1 to BLOCK4).

As shown in FIG. 2B, the sixteen write data lines DIN1 to DIN16 connect eight data input units 21 to 28 and sixteen write drivers WD1 to WD16 in a 1: 2 correspondence. The sixteen output data of the data input units 21 to 28 are transferred to the write drivers WD1 to WD16 one by one. More specifically, the sixteen write data lines DIN1 to DIN16 connect the sixteen write multiplexers WM1 to WM16 and the sixteen write drivers WD1 to WD16 in a one-to-one correspondence to each other. The 16 output data of (WM1 to WM16) are transferred to the write drivers WD1 to WD16 one by one. Here, when the light data lines DIN1 to DIN16 shown in FIG. 2B are compared with the light data lines DIN1 'to DIN16' shown in FIG. 1B, the light data lines DIN1 'to the prior art are shown. DIN16 ') is arranged in the horizontal direction in the drawing and is shared by four memory cell array blocks BLOCK1 to BLOCK4, whereas the write data lines DIN1 to DIN16 of the present invention have 4 per memory cell array block. Read data lines are dedicated and are not shared by other memory cell array blocks. As a result, the load data lines DIN1 to DIN16 of the present invention are significantly reduced in load compared to the conventional light data lines DIN1 'to DIN16', thereby reducing bus driving power. In addition, horizontal write data lines shared between each memory cell array block may be removed.

Referring to the operation of the semiconductor memory device to which the prefetch method according to an embodiment of the present invention configured as described above is as follows.

First, in the read operation, 16 data simultaneously read in four per memory cell array block in response to an external address are transferred to 16 sense amplifiers SA1 to SA16 through 16 Y-pass gates Y1 to Y16. The sixteen sense amplifiers SA1 to SA16 respectively amplify corresponding data and output the amplified data to the sixteen read data lines MDL1 to MDL16.

Thereafter, the 16 read data are transferred to the 16 read multiplexers RM1 to RM16 one by one through the read data lines MDL1 to MDL16, and the 16 read multiplexers RM1 to RM16 are received. Each of the data is latched, and the eight read multiplexers RM1, RM3, RM5, RM7, RM9, RM11, RM13, and RM15 are first turned on to latch the data that has been latched. One to the DOB8), and then the eight lead multiplexers RM1, RM3, RM5, RM7, RM9, RM11, RM13 and RM15 are turned off and the remaining eight multiplexers RM2, RM4, RM6, The RM8, RM10, RM12, RM14, and RM16 are turned on to transfer the latched data to one of the eight data output buffers DOB1 to DOB8, and the data output buffers DOB1 to DOB8 are read multiplexers RM1. 8 data and leads from RM3, RM5, RM7, RM9, RM11, RM13, and RM15) Eight data transmitted from the Lexus tipeul (RM2, RM4, RM6, RM8, RM10, RM12, RM14, RM16) and transmitted to the eight input-output pad twice in sequence.

Next, during the write operation, the eight data input buffers DIB1 to DIB8 receive eight data input through the eight input / output pads and eight write multiplexers WM1, WM3, WM5, WM7, WM9, WM11, WM13, WM15), and then the eight data input through the eight input / output pads are transferred to the remaining eight write multiplexers (WM2, WM4, WM6, WM8, WM10, WM12, WM14, and WM16). The sixteen write multiplexers WM1 to WM16 latch data received from the data input buffers DIB1 to DIB8 one by one and simultaneously output the data to the sixteen write data lines DIN1 to DIN16. Thereafter, the 16 write drivers WD1 to WD16 transmit 16 data received one by one through the 16 write data lines DIN1 to DIN16 through 16 Y-pass gates Y1 to Y16. Writes to two memory cell array blocks BLOCK1 to BLOCK4 simultaneously.

As described above, in the semiconductor memory device to which the prefetching method of the present invention is applied, the chip size is reduced because the number of internal data lines is greatly reduced as compared with the prior art, and the data is reduced because the plurality of memory cell array blocks do not share the data lines. As the load on the line is reduced, the sensing power is reduced.

Claims (3)

N memory cell array blocks, M × K sense amplifiers for amplifying and outputting M × K data simultaneously read from the N memory cell array blocks one by one; M data output units for receiving M × K output data of the sense amplification units and temporarily latching them, and outputting them sequentially K times one at a time; M × K read leads for connecting the M × K sense amplifiers and the M data outputs in a K: 1 correspondence to deliver M × K output data of the sense amplifiers to each of the data outputs. Data lines, M data input units for sequentially receiving and temporarily latching data to be simultaneously written to the N memory cell array blocks one at a time K times, and simultaneously outputting the data; M × K write drivers which receive M × K output data of the data input units one by one and simultaneously write to the N memory cell array blocks; M × K write data lines connecting the M data input units and the M × K write drivers in a 1: K correspondence to transfer M × K output data of the data input units to the write drivers one by one. A semiconductor memory device employing a prefetch method, characterized in that it comprises a. The method of claim 1, Each of the M data output units K lead switch units for latching the K data received through the K read data lines of the M × K read data lines one by one and sequentially outputting them at different times; And a data output buffer for buffering and outputting the output data of the K read switch units, Each of the M data input units A data input buffer for sequentially buffering and outputting K data to be written to the memory cell array block one at a time K times; The output data of the data input buffer one by one, and latches the output of the K X of the light data line of the write data to the K light data line of the light switch comprises: A semiconductor memory device employing a patch method. The method of claim 1, And (M × K) / N sense amplifiers per memory cell array block corresponding to each other.