KR20010019812A - Method for reducing prostitute capacitance - Google Patents
Method for reducing prostitute capacitance Download PDFInfo
- Publication number
- KR20010019812A KR20010019812A KR1019990036439A KR19990036439A KR20010019812A KR 20010019812 A KR20010019812 A KR 20010019812A KR 1019990036439 A KR1019990036439 A KR 1019990036439A KR 19990036439 A KR19990036439 A KR 19990036439A KR 20010019812 A KR20010019812 A KR 20010019812A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- sacrificial layer
- wiring
- parasitic capacitance
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02269—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by thermal evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
Abstract
Description
본 발명은 반도체 장치의 기생 용량을 감소시키는 방법에 관한 것으로서, 더욱 상세하게는, 다마신(damascene) 공정이 적용되는 반도체 장치의 기생 용량을 감소시키는 방법에 관한 것이다.The present invention relates to a method for reducing the parasitic capacitance of a semiconductor device, and more particularly, to a method for reducing the parasitic capacity of a semiconductor device to which a damascene process is applied.
주지하다시피, 반도체 장치가 고집적화 되어감에 따라서 배선 간격이 좁아지면서 배선 사이의 기생 용량이 증가되었는데, 그와 같이 증가된 기생 용량은 소자의 속도 저하 및 크로스토크(cross talk) 등을 유발하는 원인이 되고 있다.As is well known, as semiconductor devices become more integrated, parasitic capacitances between wirings have increased as the wiring spacing narrows. Such increased parasitic capacitances cause the device to slow down and cause cross talk. It is becoming.
따라서, 종래에는 그와 같은 기생 용량을 감소시키기 위한 많은 방법들이 제안되었는 바, 현행 반도체 제조시 배선간 절연을 위해서 사용되는 절연물, 예를 들어, SiO2와 같은 저유전율을 갖는 재료로 대체하는 방법이 제안되었었다.Therefore, many methods for reducing such parasitic capacitance have been proposed in the related art. In the current semiconductor manufacturing, a method of replacing an insulating material used for inter-wire insulation, for example, a material having a low dielectric constant such as SiO 2 , is used. This had been proposed.
즉, 용량(capacitance)은 유전율(k)에 비례하므로, 종래의 SiO2(k=4.1)에 비해서 유전율이 낮은 절연 재료, 예를 들어, FSG(silicon oxyfluoride, SixOFy, k=3.4∼4.1), HSQ(hydrogen silsesquioxane, k=2.9) 등과 같은 절연재료를 사용해서 배선간 절연막을 형성하는 방법이 제안되었었다.That is, since the capacitance is proportional to the dielectric constant k, an insulating material having a lower dielectric constant than conventional SiO 2 (k = 4.1), for example, FSG (silicon oxyfluoride, Si x OF y , k = 3.4 to 4.1), a method of forming an insulating film between wirings using an insulating material such as HSQ (hydrogen silsesquioxane, k = 2.9) has been proposed.
한편, 유전율은 공백 상태(vacuum, air)에서 가장 낮은 유전율(k=1)을 갖는 다는 점에 착안해서, 배선간 절연막에 에어갭(air gap)을 형성하는 방법도 제안되어 졌다.On the other hand, taking into consideration that the dielectric constant has the lowest dielectric constant (k = 1) in the void (vacuum, air), a method of forming an air gap in the insulating film between wires has also been proposed.
도 1을 참조해서, 그와 같이 에어갭을 형성하는 과정에 대해서 설명하면 다음과 같다.Referring to FIG. 1, a process of forming an air gap as described above is as follows.
먼저, 도 1a를 참조하면, 기저층(10)의 상부에 도전성 재료를 적층해서 배선용 도전층(20)을 형성한다. 이때, 기저층(10)은 배선과 배선사이를 절연하기 위한 층간 절연막이 될 수도 있고, 반도체 기판상에 형성된 산화막일 수도 있을 것이다.First, referring to FIG. 1A, a conductive material is laminated on the base layer 10 to form a wiring conductive layer 20. In this case, the base layer 10 may be an interlayer insulating film for insulating the wiring and the wiring, or may be an oxide film formed on the semiconductor substrate.
그 다음, 도 1b를 참조하면, 기저층(10)의 상부에 형성된 배선용 도전층(20)을 통상적인 포토리쏘그래피(photolitho) 기법에 의해서 원하는 형상으로 패터닝(patterning)해서 배선(20a)을 형성한다.Next, referring to FIG. 1B, the wiring 20a is formed by patterning the wiring conductive layer 20 formed on the base layer 10 to a desired shape by a conventional photolitho technique. .
이어서, PECVD(plasma enhanced chemical vapor deposition)등으로 절연재료를 적층한다. 이때, 도 2a에 도시된 바와 같이 배선(20a)의 외측 모서리(a)는 외부에 270°로 노출되어 있고, 배선(20a)의 측벽(b)은 180°로 노출되어 있으며, 배선(20a)의 내측 모서리(c)는 90°로 노출되어 있으므로, 절연재료가 적층되는 순서는 외측 모서리(a)〉측벽(b)〉내측 모서리(c) 순이 될 것이다. 따라서, 도 2b에 도시된 바와 같이 배선(20a)의 상측이 하측보다 점점 두껍게 형성됨으로써, 상측과 하측의 적층 두께 차이는 점점 심화되고, 상측이 완전히 덮힌 다음에는 하측으로 절연 재료가 도달하지 못하므로 에어갭(air gap)이 형성된다.Subsequently, an insulating material is deposited by plasma enhanced chemical vapor deposition (PECVD). At this time, as shown in FIG. 2A, the outer edge a of the wiring 20a is exposed to the outside at 270 °, the sidewall b of the wiring 20a is exposed to 180 °, and the wiring 20a is exposed. Since the inner edge c of the surface is exposed at 90 °, the order in which the insulating materials are stacked will be in the order of outer edge (a)> side wall (b)> inner edge (c). Therefore, as shown in FIG. 2B, the upper side of the wiring 20a is formed thicker than the lower side, so that the difference in stack thickness between the upper side and the lower side becomes deeper, and after the upper side is completely covered, the insulating material does not reach the lower side. An air gap is formed.
그 다음, 후속하는 공정을 위해서 그와 같이 형성된 절연 재료의 표면을 CMP(chemical mechanical polishing) 등으로 평탄화 한다.Then, the surface of the insulating material thus formed is planarized by chemical mechanical polishing (CMP) or the like for subsequent processing.
한편, 종래의 일반적인 반도체 장치에서는 알루미늄(Al)이 배선의 재료로 주로 사용되어졌으나, 고집적화에 따라서 선폭이 점차 감소되어가는 추세에 따라, 전기적 물질 이동(Electromigration)이나 스트레스 마이그레이션(stressmigration) 등으로 인해 단선이 유발될 가능성이 있는 알루미늄(Al) 대신, 구리(Cu)를 배선 재료로 선택하는 기술들이 개발되어 지고 있다.Meanwhile, in the conventional general semiconductor device, aluminum (Al) is mainly used as a wiring material, but as the line width gradually decreases due to high integration, due to electrical material transfer or stress migration, etc. Instead of aluminum (Al), which may cause disconnection, techniques have been developed to select copper (Cu) as the wiring material.
그와 같이 구리를 배선으로 사용하는 경우에는, 구리를 패터닝하기가 어려워 다마신 공정이 이용되는 바, 도 3을 참조해서 개략적으로 설명하면 다음과 같다.When copper is used as the wiring as described above, a damascene process is used because it is difficult to pattern copper, which will be described below with reference to FIG. 3.
먼저, 도 3a에 도시된 바와 같이 기저층(110)의 상부에 금속간 절연막으로 사용될 절연재료 적층해서 절연층(120)을 형성한 다음, 그 절연재료를 일반적인 포토리쏘그래피 기법으로 패터닝해서, 배선이 형성될 영역의 절연층(120)을 제거한다.First, as shown in FIG. 3A, an insulating material 120 is formed by stacking an insulating material to be used as an intermetallic insulating film on the base layer 110, and then patterning the insulating material by a general photolithography technique to form a wiring. The insulating layer 120 of the region to be formed is removed.
그 다음, 도 3에 도시된 바와 같이 패터닝된 절연층(120)의 상부에 구리를 적층해서 배선용 금속층(130)을 형성한 후, CMP 공정 등으로 절연층(120)의 상부에 형성된 배선용 금속층(130)을 제거함으로써, 배선(130a)을 형성한다.Next, as shown in FIG. 3, copper is laminated on the patterned insulating layer 120 to form the wiring metal layer 130, and then the wiring metal layer formed on the insulating layer 120 by a CMP process or the like ( By removing 130, the wiring 130a is formed.
이후, 절연층(120) 및 배선(130a)의 상부에 절연 재료를 적층해서(140)해서 층간 절연막 또는 표면 보호막등으로 작용하게 될 절연막(140)을 형성한다.Thereafter, an insulating material is stacked 140 on the insulating layer 120 and the wiring 130a to form an insulating film 140 that will act as an interlayer insulating film or a surface protective film.
그러나, 상술한 바와 같이 다마신 공정을 사용하게 되는 경우, 평탄한 기저층(110)상에 절연막(120)이 형성되므로, 상술한 에어갭 형성 과정과 같이 에어갭을 형성할 수 없게 된다.However, when the damascene process is used as described above, since the insulating layer 120 is formed on the flat base layer 110, the air gap cannot be formed as in the above-described air gap formation process.
따라서, 다마신 공정에 의해서 배선을 형성하게 되는 경우에는, 에어갭에 의해서 기생 용량을 감소시키는 방법을 적용할 수 없게 된다.Therefore, when the wiring is formed by the damascene process, the method of reducing the parasitic capacitance due to the air gap cannot be applied.
본 발명은 상술한 문제점을 해소하기 위해서 안출된 것으로서, 다마신 공정에 의해서 금속 배선을 형성하는 경우에도 에어갭에 의해서 기생 용량을 감소시킬 수 있는 반도체 장치의 기생 용량 감소 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for reducing parasitic capacitance of a semiconductor device, which can reduce parasitic capacitance due to an air gap even when a metal wiring is formed by a damascene process. There is this.
상술한 목적을 달성하기 위해서, 본 발명에서는, 반도체 장치의 기생 용량을 감소시키는 방법에 있어서, 특정층의 상부에 절연재료를 적층해서 희생층을 형성하는 단계, 상기 희생층을 패터닝해서 금속 배선이 형성될 부분을 제거하는 단계; 상기 패터닝된 희생층의 상부에 도전성 재료를 적층해서 배선용 도전층을 형성하는 단계; 상기 희생층의 상부에 형성된 배선용 도전층을 제거해서 각각 전기적으로 분리된 배선을 형성하는 단계; 상기 배선 사이에 남아있는 잔여 희생층을 제거하는 단계; 상기 배선의 상부에 절연재료를 적층해서 상기 배선 사이에 에어갭이 형성되어 있는 절연층을 형성하는 단계를 포함하는 반도체 장치의 기생 용량 감소 방법을 제공한다.In order to achieve the above object, in the present invention, in the method for reducing the parasitic capacitance of a semiconductor device, forming a sacrificial layer by laminating an insulating material on top of a specific layer, patterning the sacrificial layer to form a metal wiring Removing the portion to be formed; Forming a conductive layer for wiring by stacking a conductive material on the patterned sacrificial layer; Removing wiring conductive layers formed on the sacrificial layer to form wirings that are electrically separated from each other; Removing the remaining sacrificial layer remaining between the wires; A method for reducing parasitic capacitance of a semiconductor device, the method comprising: forming an insulating layer having an air gap formed between the wirings by stacking an insulating material on the wirings.
도 1은 종래의 에어갭 형성 과정을 도시한 순차 단면도,1 is a sequential cross-sectional view showing a conventional air gap forming process,
도 2는 종래의 에어갭이 형성되는 원리를 설명하기 위한 예시도,Figure 2 is an exemplary view for explaining the principle that the conventional air gap is formed,
도 3은 종래의 다마신 공정을 도시한 순차 단면도,Figure 3 is a sequential cross-sectional view showing a conventional damascene process,
도 4는 본 발명의 바람직한 실시예에 따라서 에어갭을 형성하는 과정을 도시한 순차 단면도.4 is a sequential cross-sectional view illustrating a process of forming an air gap according to a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10, 110, 210 : 기저층 20, 130, 230 : 배선용 도전층10, 110, 210: base layer 20, 130, 230: wiring conductive layer
20a, 130a, 230a : 배선 30, 120, 140, 240 : 절연층20a, 130a, 230a: wiring 30, 120, 140, 240: insulating layer
220 : 희생층220: sacrificial layer
이하, 첨부된 도 4를 참조해서, 본 발명의 바람직한 일 실시예에 따른 반도체 장치의 기생 용량 감소 방법에 대해서 설명하면 다음과 같다. 이때, 도 4는 본 발명의 바람직한 실시예에 따라서 에어갭을 형성하는 과정을 도시한 순차 단면도이다.Hereinafter, a parasitic capacitance reducing method of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying FIG. 4. 4 is a sequential cross-sectional view illustrating a process of forming an air gap according to a preferred embodiment of the present invention.
먼저, 도 4a를 참조하면, 기저층(210)의 상부에 식각이 용이한 재료, 예를 들어, PSG(phospho-silicate glass)를 PECVD 등에 의해서 침적함으로써, 희생층(220)을 형성한다. 이때, 희생층(220)의 침적 두께는 형성하고자 하는 배선의 두께와 동일한 두께로 형성하는 것이 바람직할 것이다. 또한, 기저층(210)은 반도체 장치의 배선이 될 수도 있고, 구동 소자 등이 형성되어 있는 반도체 기판일 수도 있을 것이다.First, referring to FIG. 4A, a sacrificial layer 220 is formed by depositing a material, for example, phosphor-silicate glass (PSG), which is easily etched on the base layer 210 by PECVD. In this case, the deposition thickness of the sacrificial layer 220 may be formed to have the same thickness as the thickness of the wiring to be formed. In addition, the base layer 210 may be a wiring of a semiconductor device, or may be a semiconductor substrate on which a driving element or the like is formed.
도 4b를 참조하면, 통상적인 미세패턴 형성 공정에 의해서 희생층(220)을 패터닝해서, 배선을 형성하고자 하는 영역의 희생층(220)을 제거한다. 이때, 본 실시예에서는, 식각 구배에 의해서 희생층(220)의 상부에서부터 하부까지 점차적으로 제거되는 부분이 감소되도록 제거한다. 이와 같이 희생층(220)의 상부를 하부보다 많이 제거하는 것은, 에어갭을 보다 용이하게 형성하기위한 것으로서, 이에 대한 설명은 후술하는 해당 공정에서 설명하기로 한다.Referring to FIG. 4B, the sacrificial layer 220 is patterned by a conventional micropattern forming process to remove the sacrificial layer 220 in a region where wiring is to be formed. At this time, in the present embodiment, the portion that is gradually removed from the top to the bottom of the sacrificial layer 220 by the etching gradient is removed to be reduced. As described above, the upper portion of the sacrificial layer 220 is removed to form an air gap more easily. The description thereof will be described in a corresponding process to be described later.
도 4c를 참조하면, 상술한 바와 같이, 희생층(220)의 패터닝으로 노출된 기저층(210)의 상부 및 희생층(220)의 상부에 구리(Cu), 알루미늄(Al), 실리사이드(silicide) 또는 폴리실리콘(poly silicon) 등과 같은 도전성 재료를 화학적 또는 물리적 기상 침적법으로 적층함으로써, 배선용 도전층(230)을 형성한다. 이때, 배선용 도전층(230a)을 희생층(220)보다 두껍게 형성하여, 희생층(220) 사이에 완전히 매립될 수 있도록 형성해야 될 것이다.Referring to FIG. 4C, as described above, copper (Cu), aluminum (Al), and silicide on the upper portion of the base layer 210 and the upper portion of the sacrificial layer 220 exposed by the patterning of the sacrificial layer 220. Alternatively, the conductive layer 230 for the wiring is formed by laminating a conductive material such as poly silicon or the like by chemical or physical vapor deposition. In this case, the wiring conductive layer 230a may be formed thicker than the sacrificial layer 220 to be completely embedded between the sacrificial layers 220.
도 4d를 참조하면, 화학적 기계 연마법(CMP) 또는 식각 가스 등을 이용한 에치백(etch back) 공정에 의해서, 희생층(220)의 상부에 형성된 배선용 도전층(230)을 제거함으로써, 배선용 도전층(230)을 배선(230a)으로 형성한다. 이때, 배선(230a)은 희생층(220)에 의해서 상호간에 전기적으로 분리될 것이다.Referring to FIG. 4D, a wiring conductive layer is formed by removing the wiring conductive layer 230 formed on the sacrificial layer 220 by an etch back process using chemical mechanical polishing (CMP) or an etching gas. The layer 230 is formed of the wiring 230a. At this time, the wiring 230a will be electrically separated from each other by the sacrificial layer 220.
도 4e를 참조하면, 통상적인 건식 또는 습식 식각 기법에 의해서, 배선(230a) 사이에 잔류하는 희생층(220)을 제거한다. 이때, 희생층(220)의 제거로 남게되는 배선(230a) 각각의 패턴은, 하측에서 상측으로 갈수록 보다 넓게 형성되어 있을 것이다. 즉, 각 패턴은 외측 모서리(a)는 270°이상의 각으로 형성되고, 측벽(b)은 180°의 각으로 형성되며, 패턴 내측의 모서리(c)는 90°이하로 형성될 것이다. 따라서, 금속 패턴 내측의 희생층(220)까지 제거할 필요가 있을 경우에는 습식 식각이 보다 바람직할 수도 있을 것이다.Referring to FIG. 4E, the sacrificial layer 220 remaining between the wirings 230a is removed by a conventional dry or wet etching technique. At this time, the pattern of each of the wirings 230a remaining after the removal of the sacrificial layer 220 may be formed wider from the lower side to the upper side. That is, each pattern of the outer edge (a) is formed at an angle of 270 ° or more, the side wall (b) is formed at an angle of 180 °, the inner edge (c) of the pattern will be formed below 90 °. Therefore, when it is necessary to remove the sacrificial layer 220 inside the metal pattern, wet etching may be more preferable.
도 4f를 참조하면, 희생층(220)의 제거로 노출된 기저층(210)의 상부 및 배선(230)의 상부에 절연 재료를 적층해서 절연층(240)을 형성한다. 이때, 도 2를 참조해서 상술한 방법에서와 같이 배선(230a) 사이의 절연층(240)에는 에어갭이 형성될 것이다.Referring to FIG. 4F, an insulating material 240 is formed by stacking an insulating material on the upper portion of the base layer 210 and the wiring 230 exposed by the removal of the sacrificial layer 220. In this case, as in the method described above with reference to FIG. 2, an air gap will be formed in the insulating layer 240 between the wirings 230a.
즉, 배선(230a)의 각 패턴은 외측 모서리(a)는 270°이상의 각으로 형성되고, 측벽(b)은 180°의 각으로 형성되며, 패턴 내측의 모서리(c)는 90°이하로 형성되어 있으므로, 침적되는 절연재료에 보다 많이 노출되어 있는 순서, 즉, 외측 모서리(a)〉측벽(b)〉내측 모서리(c) 순서에 의해서 적층이 빠르게 이루어질 것이다.That is, each pattern of the wiring 230a has an outer edge a formed at an angle of 270 ° or more, the side wall b is formed at an angle of 180 °, and an edge c inside the pattern is formed at 90 ° or less. As a result, the lamination will be quicker in the order of being more exposed to the insulating material to be deposited, that is, in the order of the outer edge (a)> side wall (b)> inner edge (c).
따라서, 상측이 하측보다 점점 두껍게 형성됨으로써, 상측과 하측의 적층 두께 차이는 점점 심화되고, 상측이 완전히 덮힌 다음에는 하측으로 절연 재료가 도달하지 못하므로 에어갭(air gap)이 형성되는데, 도 2도를 참조해서 설명한 방법에 비해서, 본 실시예에서는 외측 모서리(a)가 보다 많이 노출되어 있고, 내측 모서리(b)가 보다 덜 노출어 있으므로, 도 2를 참조한 설명에서보다 상측이 보다 빠르게 매립될 것이고, 결과적으로 보다 큰 에어갭이 용이하게 형성될 것이다.Therefore, as the upper side is formed thicker than the lower side, the difference in stack thickness between the upper side and the lower side becomes deeper, and after the upper side is completely covered, since the insulating material does not reach the lower side, an air gap is formed. Compared to the method described with reference to the drawings, in this embodiment, the outer edge a is more exposed and the inner edge b is less exposed, so that the upper side is buried faster than in the description with reference to FIG. As a result, larger air gaps will be readily formed.
한편, 그와 같이 에어갭이 형성된 절연층(240)을 형성하는 과정에서, 절연 재료로서는, 배선 사이의 기생 용량을 보다 감소 시킬 수 있도록, USG, PSG, BSG, BPSG, FSG, 폴리머(polymer) 또는 SOG 등과 같이 유전율이 낮은(예를 들어, 유전율이 4이하로 낮은) 절연재료를 사용하는 것이 보다 바람직할 것이고, 절연층(240)을 형성하는 기법으로는, 화학 기상 침적법(CVD), 스퍼터링(sputtering), 회전 도포법(spin coating) 또는 증발법(evaporation)중 어느 하나를 이용할 수 있을 것이다.Meanwhile, in the process of forming the insulating layer 240 in which the air gap is formed, USG, PSG, BSG, BPSG, FSG, and polymer are used as the insulating material so that the parasitic capacitance between the wirings can be further reduced. Alternatively, it is more preferable to use an insulating material having a low dielectric constant (for example, low dielectric constant of 4 or less) such as SOG, and the like. As a technique for forming the insulating layer 240, chemical vapor deposition (CVD), Sputtering, spin coating or evaporation may be used.
도 4g를 참조하면, CMP나 식각제를 이용한 에치백(etch back) 공정에 의해서, 절연층(240)의 상부를 평탄화한다. 이때, 그와 같은 평탄화 과정은 후속하는 공정을 용이하게 하기 위한 것으로서, 이 과정이 생략되어도 본 발명은 용이하게 이루어진다.Referring to FIG. 4G, the upper portion of the insulating layer 240 is planarized by an etch back process using CMP or an etchant. At this time, such a planarization process is intended to facilitate the subsequent process, even if this process is omitted, the present invention is easily made.
상술한 실시예에서는, 에어갭을 보다 용이하게 형성하도록 희생층(220)의 모향을 한정하도록 설명했으나, 본원 발명의 핵심 기술 사상은, "종래에 배선 사이에 저유전율을 갖는 재료 등으로 형성되던 절연층 대신에 후속하는 공정에서 제거하기 용이한 식각제를 사용해서 희생층을 형성한 후, 배선을 형성하고 난 다음에는, 그 희생층을 제거한 후, 다시 저유전율 재료로 절연층을 형성함으로써, 배선 사이의 절연층에 에어갭을 형성"하는데 있는 바, 이를 중심으로 본원 발명이 이해되어야 할 것이다.In the above-described embodiment, it has been described to limit the mother home of the sacrificial layer 220 to form the air gap more easily, the core technical idea of the present invention, "formerly formed of a material having a low dielectric constant between the wiring and the like By forming a sacrificial layer using an etchant which is easy to remove in a subsequent step instead of an insulating layer, and then forming a wiring, the sacrificial layer is removed, and then an insulating layer is formed of a low dielectric constant material again. To form an air gap in the insulating layer between the wirings ", and the present invention should be understood based on this.
상술한 본 발명에 따르면, 다마신 공정의 채용으로 인해서 기생 용량 방지용 에어갭의 형성이 불가능한 반도체 장치에서도, 배선 사이에 에어갭을 형성하여 기생 용량을 방지할 수 있게 됨으로써, 소자의 속도 향상이나 크로스토크(cross talk)를 방지할 수 있는 등의 효과를 얻을 수 있다.According to the present invention described above, even in a semiconductor device in which it is impossible to form an air gap for preventing parasitic capacitance due to the adoption of a damascene process, an air gap can be formed between wirings to prevent parasitic capacitance, thereby improving device speed and cross The effect of preventing cross talk and the like can be obtained.
Claims (6)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990036439A KR100307490B1 (en) | 1999-08-31 | 1999-08-31 | Method for reducing prostitute capacitance |
| TW89117833A TW495913B (en) | 1999-08-31 | 2000-08-31 | An interconnect structure of a semiconductor device with an air gap and method of manufacturing the same |
| JP2000262554A JP3813424B2 (en) | 1999-08-31 | 2000-08-31 | Manufacturing method of wiring structure of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990036439A KR100307490B1 (en) | 1999-08-31 | 1999-08-31 | Method for reducing prostitute capacitance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010019812A true KR20010019812A (en) | 2001-03-15 |
| KR100307490B1 KR100307490B1 (en) | 2001-11-01 |
Family
ID=19609315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990036439A KR100307490B1 (en) | 1999-08-31 | 1999-08-31 | Method for reducing prostitute capacitance |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3813424B2 (en) |
| KR (1) | KR100307490B1 (en) |
| TW (1) | TW495913B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100712517B1 (en) * | 2005-07-14 | 2007-04-30 | 삼성전자주식회사 | Interposer of semiconductor device having air gap structure |
| KR100867631B1 (en) * | 2007-02-01 | 2008-11-10 | 삼성전자주식회사 | Semiconductor device and Method of manufacturing the same |
| KR100909855B1 (en) * | 2002-07-15 | 2009-07-28 | 크로스텍 캐피탈, 엘엘씨 | Image sensor and its manufacturing method that can prevent crosstalk |
| KR101038388B1 (en) * | 2009-01-29 | 2011-06-02 | 주식회사 하이닉스반도체 | Manufacturing method of metal line for semiconductor device |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7297471B1 (en) | 2003-04-15 | 2007-11-20 | Idc, Llc | Method for manufacturing an array of interferometric modulators |
| US7265045B2 (en) | 2002-10-24 | 2007-09-04 | Megica Corporation | Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging |
| JP4052950B2 (en) | 2003-01-17 | 2008-02-27 | Ｎｅｃエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| TW570896B (en) | 2003-05-26 | 2004-01-11 | Prime View Int Co Ltd | A method for fabricating an interference display cell |
| TW593126B (en) | 2003-09-30 | 2004-06-21 | Prime View Int Co Ltd | A structure of a micro electro mechanical system and manufacturing the same |
| KR101255691B1 (en) | 2004-07-29 | 2013-04-17 | 퀄컴 엠이엠에스 테크놀로지스, 인크. | System and method for micro-electromechanical operating of an interferometric modulator |
| TW200628877A (en) * | 2005-02-04 | 2006-08-16 | Prime View Int Co Ltd | Method of manufacturing optical interference type color display |
| JP4956919B2 (en) | 2005-06-08 | 2012-06-20 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| KR20080040715A (en) | 2005-07-22 | 2008-05-08 | 콸콤 인코포레이티드 | Support structure for mems device and methods therefor |
| KR101423321B1 (en) | 2005-07-22 | 2014-07-30 | 퀄컴 엠이엠에스 테크놀로지스, 인크. | Electomechanical devices having support structures and methods of fabricating the same |
| EP2495212A3 (en) | 2005-07-22 | 2012-10-31 | QUALCOMM MEMS Technologies, Inc. | Mems devices having support structures and methods of fabricating the same |
| JP4731262B2 (en) | 2005-09-22 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device |
| US7795061B2 (en) | 2005-12-29 | 2010-09-14 | Qualcomm Mems Technologies, Inc. | Method of creating MEMS device cavities by a non-etching process |
| US7382515B2 (en) | 2006-01-18 | 2008-06-03 | Qualcomm Mems Technologies, Inc. | Silicon-rich silicon nitrides as etch stops in MEMS manufacture |
| US7763546B2 (en) | 2006-08-02 | 2010-07-27 | Qualcomm Mems Technologies, Inc. | Methods for reducing surface charges during the manufacture of microelectromechanical systems devices |
| KR100829603B1 (en) * | 2006-11-23 | 2008-05-14 | 삼성전자주식회사 | Method of manufacturing a semiconductor device having an air-gap |
| US7733552B2 (en) | 2007-03-21 | 2010-06-08 | Qualcomm Mems Technologies, Inc | MEMS cavity-coating layers and methods |
| US7719752B2 (en) | 2007-05-11 | 2010-05-18 | Qualcomm Mems Technologies, Inc. | MEMS structures, methods of fabricating MEMS components on separate substrates and assembly of same |
| US8068268B2 (en) | 2007-07-03 | 2011-11-29 | Qualcomm Mems Technologies, Inc. | MEMS devices having improved uniformity and methods for making them |
| JP5342811B2 (en) * | 2008-06-09 | 2013-11-13 | 東京エレクトロン株式会社 | Manufacturing method of semiconductor device |
| US7864403B2 (en) | 2009-03-27 | 2011-01-04 | Qualcomm Mems Technologies, Inc. | Post-release adjustment of interferometric modulator reflectivity |
| JP5537137B2 (en) * | 2009-12-10 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US8659816B2 (en) | 2011-04-25 | 2014-02-25 | Qualcomm Mems Technologies, Inc. | Mechanical layer and methods of making the same |
| JP6295802B2 (en) | 2014-04-18 | 2018-03-20 | ソニー株式会社 | FIELD EFFECT TRANSISTOR FOR HIGH FREQUENCY DEVICE, ITS MANUFACTURING METHOD, AND HIGH FREQUENCY DEVICE |
| WO2015182581A1 (en) | 2014-05-29 | 2015-12-03 | アーゼット・エレクトロニック・マテリアルズ（ルクセンブルグ） ソシエテ・ア・レスポンサビリテ・リミテ | Void forming composition, semiconductor device provided with voids formed using composition, and method for manufacturing semiconductor device using composition |
| JPWO2016017678A1 (en) | 2014-07-31 | 2017-06-15 | アーゼッド・エレクトロニック・マテリアルズ（ルクセンブルグ）ソシエテ・ア・レスポンサビリテ・リミテ | Composition for sacrificial film, method for producing the same, semiconductor device having voids formed using the composition, and method for producing a semiconductor device using the composition |
-
1999
- 1999-08-31 KR KR1019990036439A patent/KR100307490B1/en not_active IP Right Cessation
-
2000
- 2000-08-31 JP JP2000262554A patent/JP3813424B2/en not_active Expired - Fee Related
- 2000-08-31 TW TW89117833A patent/TW495913B/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100909855B1 (en) * | 2002-07-15 | 2009-07-28 | 크로스텍 캐피탈, 엘엘씨 | Image sensor and its manufacturing method that can prevent crosstalk |
| KR100712517B1 (en) * | 2005-07-14 | 2007-04-30 | 삼성전자주식회사 | Interposer of semiconductor device having air gap structure |
| KR100867631B1 (en) * | 2007-02-01 | 2008-11-10 | 삼성전자주식회사 | Semiconductor device and Method of manufacturing the same |
| KR101038388B1 (en) * | 2009-01-29 | 2011-06-02 | 주식회사 하이닉스반도체 | Manufacturing method of metal line for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3813424B2 (en) | 2006-08-23 |
| KR100307490B1 (en) | 2001-11-01 |
| JP2001085519A (en) | 2001-03-30 |
| TW495913B (en) | 2002-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100307490B1 (en) | Method for reducing prostitute capacitance | |
| JP5305901B2 (en) | MIM capacitor and manufacturing method thereof | |
| US6177329B1 (en) | Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets | |
| US6130151A (en) | Method of manufacturing air gap in multilevel interconnection | |
| JP4328501B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3790469B2 (en) | Semiconductor device | |
| US6331481B1 (en) | Damascene etchback for low ε dielectric | |
| US5891805A (en) | Method of forming contacts | |
| US20060073695A1 (en) | Gas dielectric structure forming methods | |
| US6297149B1 (en) | Methods for forming metal interconnects | |
| US6576525B2 (en) | Damascene capacitor having a recessed plate | |
| US20030176056A1 (en) | Method for forming metal wiring layer of semiconductor device | |
| US6228770B1 (en) | Method to form self-sealing air gaps between metal interconnects | |
| US6160316A (en) | Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths | |
| KR100342639B1 (en) | Method of fabricating a semiconductor structure | |
| KR100684905B1 (en) | Method For Damascene Process | |
| US6686643B2 (en) | Substrate with at least two metal structures deposited thereon, and method for fabricating the same | |
| KR100330438B1 (en) | Integtated circuit fabrication | |
| JP2001085518A (en) | Manufacture of multilayer wiring structure and semiconductor device | |
| US6894364B2 (en) | Capacitor in an interconnect system and method of manufacturing thereof | |
| US20020149085A1 (en) | Method of manufacturing air gap in multilevel interconnection | |
| US6399482B1 (en) | Method and structure for a conductive and a dielectric layer | |
| US6358845B1 (en) | Method for forming inter metal dielectric | |
| KR100588665B1 (en) | Method for fabricating barrier metal of semiconductor device | |
| KR100652358B1 (en) | A method of forming dual damascene |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110719 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20120726 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |