KR20010019621A - Shared Architecture And Method Of System Paket Bus In Switching System - Google Patents

Abstract

PURPOSE: The method and structure for sharing a system PB(Packet Bus) are provided for each CPU to transceive a message with a system controller through one system PB bus by a plurality of receiving memories which transceive messages shared with a plurality of transmitting buffers. CONSTITUTION: When each CPU(20-1,20-2) of a local board having many CPUs(20-1,20-2) transmits a message to a system controller through one system PB(Packet Bus), a transmission message is recorded in transmission buffers(41,51). Write/read signals of each CPU(20-1,20-2) are detected, and a transmission priority register(64) is recorded according to priority of the transmission buffers(41,51). The transmission priority register(64) is checked and a transmission message recorded in a corresponding transmission buffer is moved to a transmission memory(60). A transmission enable register(61) of the transmission memory(60) is checked, and the moved transmission message is transmitted to the system controller.

Description

Shared Architecture And Method Of System Paket Bus In Switching System

The present invention relates to a shared structure and method of a system packet bus in a switching system. In particular, a plurality of CPUs share a single system packet bus (hereinafter, referred to as a 'PB bus') in a local board of a switching system to transmit and receive a message. The present invention relates to a shared structure and method of a system packet bus in an exchange system.

In general, a system bus that uses an existing PB (Packet Bus) bus in a switching system is designed so that only one central processing unit (CPU) can be used on a local board. Each CPU could not share the system PB bus. In other words, there was only one CPU on the local board, and the system PB bus could send and receive messages by one CPU.

In this conventional exchange system, the system PB bus of the local board is connected to the PB memory 12-1 through one CPU 11 and a data bus and an address bus, as shown in FIG. 1. The arbitration circuit unit 13 writes / reads the PB memory 12-1 and transmits / receives the PB buffer 12-2 according to the control signal and the write / read (WR / RD) signal of the CPU 11 (TX). / RX) is done.

At this time, the message transmission / reception direction of the corresponding PB bus 12 is controlled by a transistor-transistor logic according to a transmission / reception signal (TX / RX signal) for the PB buffer 12 output from the arbitration circuit unit 13. The PB memory 12-1 is configured with an external static random access memory (SRAM).

Therefore, even when two or more CPUs are provided and used in the same local board, only one CPU can write / read the PB memory to transmit and receive messages through the PB buffer. That is, the control of the PB bus by a large number of CPUs has been limited.

By the way, when one CPU on the same local board of a switching system does not function properly, but the CPU needs to be designed with multiple CPUs or when each CPU needs to perform a completely different process on the same local board, each CPU is the same. Although PB buses must be shared, they have not conventionally provided the functionality described above.

If multiple CPUs have the same number of PB memories of the corresponding PB bus to share the same system PB bus, the message reception of the corresponding PB bus can be read by each CPU, but at the same time at each CPU at the time of transmission. Could not be used.

As described above, the local board of the conventional switching system has a disadvantage in that the performance improvement of the local board is limited as data and addresses of one CPU and the system PB bus are connected to each other to transmit and receive messages only by the corresponding CPU.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and its object is to share a plurality of transmit buffers for transmitting a message to PB memory of a system PB bus when multiple CPUs are to be used on the same local board of a switching system. By constructing a transmission memory used and a plurality of reception memories for message reception, the CPUs can transmit and receive messages to and from the system control unit through one system PB bus.

1 schematically illustrates a system PB bus of a local board in a conventional exchange system.

2 is a diagram schematically illustrating a shared structure of a system PB bus in an exchange system according to the present invention.

3 is a detailed block diagram of the system PB bus in FIG. 2;

4 is a state transition diagram at the time of message transmission using the system PB bus of the local board in the switching system according to the present invention.

Explanation of symbols on the main parts of the drawings

20-1, 20-2: CPU 30: System PB Bus

31: PB memory 32: arbitration circuit

33: PB buffer 41, 51: transmit buffer

42, 52: Receive memory 43, 53: Enable register

44, 54: address pointer 60: transmission memory

61: transmit enable register 62: transmit address pointer

63: transmit status register 64: transmit priority register

A feature of the present invention for achieving the object as described above, in the switching system having a local board with a plurality of CPUs, each CPU is allocated for arbitrarily storing a message to be transmitted to the upper system control unit A plurality of transmit buffers; A plurality of receiving memories allocated to receive the messages received from the system control unit in each of the CPUs; A transmission memory which is used in common according to a temporal priority in the message transmission of each CPU; And an arbitration circuit unit that performs a PB memory arbitration function so as to share a system packet bus when transmitting and receiving messages of each CPU.

And the transmit buffer comprises an enable register indicating whether a transmit message has been written by the CPU; An address pointer for managing recording of a transmission message when the size of the transmission buffer is to be extended, wherein the transmission memory comprises: a transmission enable register indicating whether a stored message has been transmitted to a system controller; A transmission address pointer which manages recording of transmission messages when the size of the transmission memory is expanded, and serves as a write address pointer of the transmission memory for managing transmission message positions of the respective transmission buffers recorded according to priority; ; A transmission status register for managing a status of the transmission memory; And a transmission priority register indicating a transmission priority of the transmission buffer.

According to another aspect of the present invention, when receiving a message from the system controller through a system packet bus on a local board having a plurality of CPUs, the message received from the system controller is recorded in each receiving memory, and then in each CPU. It is to read and process the received message recorded in the corresponding receiving memory.

Still another aspect of the present invention provides a method of writing a transmission message to a transmission buffer when transmitting a message to a system controller through a system packet bus from each CPU of a local board having a plurality of CPUs; Detecting a write / read signal of each CPU and recording a transmit priority register according to the priority of the transmit buffer; Checking the transmission priority register to move a transmission message recorded in a corresponding transmission buffer to a transmission memory; And transmitting the moved transmission message to the system control unit by checking a transmission enable register of the transmission memory.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the switching system according to the present invention, the shared structure of the system PB bus may include a plurality of CPUs 20-1 and 20-2 for transmitting and receiving messages to and from the system controller through the system PB bus as shown in FIG. PB memory 31 for storing messages actually transmitted and received, arbitration circuitry 32 performing arbitration function of PB memory 31 so that the system PB bus can be shared when messages are transmitted and received by each CPU, and temporarily storing messages transmitted and received. The PB memory 31 and the arbitration circuit unit 32 of the system PB bus 30 are implemented as a Field Programmable Gate Array (FPGA), for convenience of description. Modeling is based on two CPUs 20-1 and 20-2.

The detailed configuration of the system PB bus 30 is as shown in FIG. 3, but the PB memory 31 is configured to transmit messages for each of the CPUs 20-1 and 20-2. 1st sending buffer 41 and 2nd sending buffer 42 (16 byte size), and 1st receiving memory 42 and 2nd receiving allocated for message reception of each CPU 20-1, 20-2. Memory 52 (256 bytes in size) and transmission memory 60 (16 bytes in size) which are commonly used for message transmission by each of the CPUs 20-1 and 20-2.

The first transmission buffer 41 and the second transmission buffer 51 are memories for arbitrarily storing messages to be transmitted from the CPUs 20-1 and 20-2 to the upper system control section. The first receiving memory 42 and the second receiving memory 52 store a message to be loaded in the memory. The first receiving memory 42 and the second receiving memory 52 store a message received from the system controller. A message is recorded by the first memory, and the transmission memory 60 stores the first CPU 20-1 and the second CPU 20-2 according to the temporal priority of the first transmission buffer 41 and the second transmission buffer 51. ) Is a memory for storing a message to be transmitted, and transmits the stored message by a hardware signal of the arbitration circuit unit 32.

Here, the first transmission buffer 41 and the second transmission buffer 51 have respective enable registers 43 and 53 indicating whether transmission messages have been recorded by the respective CPUs 20-1 and 20-2 ( 1 bit size) and respective address pointers 44 and 54 (24 bit size) for managing the recording of the transmission message when the size of each transmission buffer 41 or 42 is to be extended.

Then, the transmission memory 60 stores a transmission enable register 61 (1 bit size) indicating whether the stored message has been transmitted, and for managing recording of the transmission message when the transmission memory 60 is expanded in size. Transmission address pointer 62 (24 bit size), transmission status register 63 (1 bit size) for managing the state of the memory, and transmission priority register indicating the transmission priority of each transmission buffer 41, 51. The transmission address pointer 62 includes a recording address of the transmission memory 60 for managing the transmission message positions of the transmission buffers 41 and 51, which are recorded according to priority. A register that acts as a pointer, and the corresponding transmit priority register 64 stores a message of each transmit buffer 41 and 51 in the transmit memory 60 in a PB bus structure in which only one message can be written in one cycle. A first register indicating the priority.

At this time, the storage capacity of each component constituting the PB memory 31 may vary according to the size of a message or the size of a memory pool, and may vary depending on the type of the CPU, the hardware memory map, or the flag address. The number of CPUs used on the same local board determines the number of receive memory, transmit buffer and transmit priority register.

Meanwhile, the system PB bus 30 of the corresponding local board is shared between the first CPU 20-1 and the second CPU 20-2 by using each data bus, address bus, and control signals. A message is transmitted through one system PB bus 30 according to the data bus, address bus, and control signals of -1 and 20-2, and the system PB allocated to each CPU 20-1 and 20-2. Each of the CPUs 20-1 and 20-2 independently receives a message using the reception memories 42 and 52 of the bus 30.

Referring to the operation of receiving a message using the system PB bus 30 of the local board in the switching system according to the present invention configured as described above, the message received from the system control unit is the first receiving memory 42 by a hardware control signal Are simultaneously recorded in the second and second receiving memories 52, and the received messages recorded in the corresponding receiving memories 42 and 52 in the respective CPUs 20-1 and 20-2 are read out and processed. In the case where the hardware memory map or flag for reading the received message is different in -1 and 20-2, the hardware write address of each of the receiving memories 42 and 52 should be configured differently.

On the contrary, the operation of the message transmission using the system PB bus 30 of the local board in the switching system according to the present invention will be described with reference to the state transition diagram of FIG.

First, each CPU 20-1, 20-2 transmits one message to the system PB bus 30 in one 8ms period, but in the first period T1, the first transmission buffer is transmitted by the first CPU 20-1. After the message is recorded in (41), the second CPU 20-2 records the message in the second transmission buffer 51, and in the second period T2, the second transmission buffer 51 in the second CPU 20-2. It is assumed that the message is written to the first transmission buffer 41 by the first CPU 20-1 after the message is recorded.

A transmission address pointer 62 for managing the recording of the transmission memory 60 by fixing the transmission memory 60 to the size of one message, and for managing the recording of each of the transmission buffers 41 and 51. Assume that the address pointers 44 and 54 are not used.

In this state, when the local board is initialized, the arbitration circuit unit 32 of the corresponding local board transitions to a write / read check state that detects the write / read signals of the respective CPUs 20-1 and 20-2. By checking whether the WR / RD signal accesses the system PB bus first, the set / reset of the transmit priority register 64 indicating the priority of each transmit buffer 41, 51 is set. Will be decided.

In this case, it is assumed that the first CPU 20-1 is reset when the priority is given to the first CPU 20-1 and is set if the second CPU 20-2 is priority. The first transmission buffer 41 is transmitted to the first transmission buffer 41 by the first CPU 20-1 in the first period. As the message to be transmitted is recorded first, the first enable register 43 of the first transmission buffer 41 is reset.

Then, the arbitration circuit section 32 transitions to the buffer enable check state for detecting the enable registers 43 and 53 of the respective transmission buffers 41 and 51, and if any one of the enable registers is reset, the corresponding transmission memory. The transmission priority register 64 of 60 is recorded, but the first enable register 43 of the first transmission buffer 41 is reset, so that the transmission priority register 64 is reset. .

Thereafter, since the transmission priority register 64 of the transmission memory 60 is reset in the transmission priority check state, the message transferred to the message transfer state and recorded in the first transmission buffer 41 are transmitted to the transmission memory 60. ), And then transition to the transmit enable check state to reset the transmit enable register 61 of the corresponding transmit memory 60, and at the same time, the first enable register 43 of the first transmit buffer 41 is Will be set.

Then, the arbitration circuit unit 32 transitions to the message transmission state and transmits the transmission message of the first CPU 20-1 stored in the transmission memory 60 to the system control unit through the PB buffer 33 in hardware. Then, the state transitions to the buffer enable check state for detecting the enable registers 43 and 53 of the respective transmission buffers 41 and 51.

At this time, after the message is recorded in the first transmission buffer 41 by the first CPU 20-1 in the first period, the message is recorded in the second transmission buffer 51 by the second CPU 20-2. Since the second enable register 53 of the second transmission buffer 51 is reset, the transmission priority register 64 of the transmission memory 60 is set.

Thereafter, the arbitration circuit unit 32 transitions to the transmission priority check state and checks the transmission priority register 64 of the transmission memory 60. At this time, the transmission enable register 61 is set. After transiting to the message movement state, the message recorded in the second transmission buffer 51 is moved to the transmission memory 60, and then the state is transferred to the transmission enable check state to transmit the register of the transmission enable register of the transmission memory 60 ( 61 is reset and a second enable register 53 of the second transmission buffer 51 is set.

Then, the arbitration circuit unit 32 transitions to the message transmission state and transmits the transmission message of the second CPU 20-2 stored in the transmission memory 60 to the system control unit through the PB buffer 33 in hardware. In this case, the message transmission operation in the first period is terminated.

Next, in the second period, the arbitration circuit unit transitions to the write / read check state to determine which CPU's write / read signal first accesses the system PB bus 30. In the second period, the second CPU 20- As the message is first written to the second transmission buffer 51 by 2), the second enable register 53 of the second transmission buffer 51 is reset.

Then, the arbitration circuit unit 32 sets the transmission priority register 64 of the transmission memory 60 as the second enable register 53 is reset in the buffer enable check state, and then the corresponding transmission priority. Since the transmission priority register 64 of the transmission memory 60 is set in the checked state, the message is transferred to the transmission memory 60 by moving to the message movement state and moving the message recorded in the corresponding second transmission buffer 51 to the transmission memory 60. The transmission enable register 61 of the transmission memory 60 is reset.

Since the second enable register 53 of the second transmit buffer 51 is set and the transmit enable register 61 of the transmit memory 60 is reset in the transmit enable check state, the message is reset. After transiting to the transmission state and transmitting the transmission message of the second CPU 20-2 stored in the transmission memory 60 to the system control unit through the PB buffer 33 in hardware, each of the transmission buffers 41 and 51 A transition is made to the buffer enable check state for detecting the enable registers 43 and 53.

At this time, after the message is recorded in the second transmission buffer 51 by the second CPU 20-2, the message is recorded in the first transmission buffer 41 by the first CPU 20-1. Since the first enable register 43 of the first transmission buffer 41 is reset, the transmission priority register 64 of the transmission memory 60 is reset.

Thereafter, the arbitration circuit unit 32 transitions to the transmission priority check state and checks the transmission priority register 64 of the transmission memory 60. At this time, the transmission enable register 61 is set. After transiting to the message movement state, the message recorded in the first transmission buffer 41 is moved to the transmission memory 60, and then the state is transferred to the transmission enable check state, and the transmission enable register of the transmission memory 60 ( At the same time as the 61 is reset, the first enable register 43 of the first transmission buffer 41 is set.

Then, the arbitration circuit unit 32 transitions to the message transmission state and transmits the transmission message of the first CPU 20-1 stored in the transmission memory 60 to the system control unit through the PB buffer 33 in hardware. In this case, the message transmission operation in the second period is terminated.

In the present invention, by repeatedly performing the above-described operation, multiple CPUs of the local board in the corresponding exchange system can share and use the system PB bus.

As described above, the present invention uses a plurality of CPUs or local boards due to a problem in hardware performance of a corresponding local board among systems that transmit and receive messages between a system controller and a local board through an existing system PB bus. The main board and the sub-board can be applied to the boards in which both CPUs operate, and can also be applied to a case where a plurality of local boards want to transmit a message to the system controller through one system PB bus.

In addition, the embodiments according to the present invention are not limited to the above-described embodiments, and various alternatives, modifications, and changes can be made within the scope apparent to those skilled in the art.

As described above, the present invention provides a transmission memory and a plurality of transmission memories used in common with a plurality of transmission buffers for message transmission to a PB memory of a system PB bus when a plurality of CPUs must be used in the same local board of a switching system. By configuring the receiving memory of the CPU, each CPU can transmit and receive messages to and from the system control unit through one system PB bus, thereby realizing the performance improvement of the corresponding local board.

Claims (5)

In a switching system having a local board with a plurality of CPUs, A plurality of transmission buffers allocated for arbitrarily storing a message to be transmitted from each CPU to an upper system control unit; A plurality of receiving memories allocated to receive the messages received from the system control unit in each of the CPUs; A transmission memory which is used in common according to a temporal priority in the message transmission of each CPU; And an arbitration circuit unit configured to perform a PB memory arbitration function so as to share a system packet bus when transmitting and receiving messages of each CPU. The method of claim 1, The transmit buffer includes an enable register indicating whether a transmission message has been written by the CPU; And an address pointer for managing the recording of the transmission message when the size of the transmission buffer is to be extended. The method of claim 1, The transmit memory includes: a transmit enable register indicating whether a stored message has been transmitted to the system control section; A transmission address pointer which manages recording of transmission messages when the size of the transmission memory is expanded, and serves as a write address pointer of the transmission memory for managing transmission message positions of the respective transmission buffers recorded according to priority; ; A transmission status register for managing a status of the transmission memory; And a transmission priority register indicating a transmission priority of the transmission buffer. When receiving a message from a system controller through a system packet bus in a local board equipped with a plurality of CPUs, a message received from the system controller is recorded in each receiving memory, and then written in a corresponding receiving memory in each CPU. A method of sharing a system packet bus in a switching system, comprising reading and processing a received message. Writing a transmission message to a transmission buffer when the CPU transmits a message to a system controller through a system packet bus from each CPU of a local board including a plurality of CPUs; Detecting a write / read signal of each CPU and recording a transmit priority register according to the priority of the transmit buffer; Checking the transmission priority register to move a transmission message recorded in a corresponding transmission buffer to a transmission memory; And transmitting the shifted transmission message to the system control unit by checking a transmission enable register of the transmission memory.