KR20010017725A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Displayer) is provided not to reduce a display quality by minimizing a change of a gate driving signal. CONSTITUTION: An LCD(601) comprises a display unit(200), a backlight assembly(300), a chassis(400) and a cover(500). The backlight assembly(300) comprises optical sheets(310), a light incident plate(320), a lamp assembly(330), a reflecting plate(340), and a mold frame(350). The display unit(200) comprises LCD panels(240,250); a liquid crystal; driving signal feeding time deciding devices(210,220) to feed a driving signal to the LCD panels and to decide a feeding timing; and a united PCB(Printed Circuit Board)(230). The LCD panels(240,250) comprise a TFT(Thin Film Transistor) substrate(240) and a color filter substrate(250). In removing a gate PCB, a high resistance of a signal transmission pattern in the TFT substrate is removed. Thereby, a thickness of the LCD is reduced and a display quality of the LCD is not reduced.

Description

Liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to an integrated printed circuit in which a gate printed circuit board generating a gate driving signal to be applied to a gate line of a liquid crystal display panel is removed, and both a gate driving signal and a data driving signal are generated. The gate driving signal generated from the substrate is transmitted to the gate tape carrier package using the driving signal transmission pattern formed on the liquid crystal display panel, and the liquid crystal display panel is prevented from deteriorating display performance in the liquid crystal display panel due to the pattern resistance caused by the driving signal transmission pattern. The present invention relates to a liquid crystal display device in which the thickness of the display device is greatly reduced.

Recently, due to the rapid development of technology in the semiconductor industry, technology development in almost all industries is progressing, as well as many products that are more compact and lighter and more powerful in performance are being produced.

One of these products, a liquid crystal display device having a large screen of 14.1 inches or more, is installed in almost all information processing devices requiring a display device as well as a monitor of a desktop computer.

Since the liquid crystal display device has a large screen and increases in weight and volume, a lot of technologies have been developed to implement a large screen and have a small but light weight other than the screen.

In particular, Korean Patent Application No. 99-13650, "Tape carrier package, liquid crystal display panel assembly including the same, a liquid crystal display device employing the same, and a method for assembling thereof" includes an integrated printed circuit board on which a gate driving signal and a data driving signal are generated. Data drive signal from the integrated printed circuit board-data tape carrier package-data line through the path of the data line, and the gate drive signal is integrated printed circuit board-data tape carrier package-signal transmission pattern formed on the TFT substrate- Background Art A liquid crystal display device has been disclosed in which a gate printed circuit board, which acts as a factor of increasing thickness of a liquid crystal display panel by inputting the gate line along a path of a gate tape carrier package-gate line, is removed.

However, the liquid crystal display described above transmits the gate driving signal generated in the integrated printed circuit board to the gate tape carrier package through a thin film type signal transmission pattern formed by a sputtering method, which is one of the semiconductor processes. It has a relatively very high pattern resistance compared to the signal transmission pattern formed by.

The increased pattern resistance greatly affects the display state of the liquid crystal display, and the pattern resistance tends to increase in proportion to the length of the signal transmission pattern.

For example, it has been experimented that the greatest influence on the turn-off signal (hereinafter referred to as V _off signal) for turning off the thin film transistor formed on the TFT substrate, namely, voltage drop, signal modulation and distortion, etc. Signals have also been tested to be greatly affected by this pattern resistance.

In particular, the signal transmission pattern for transmitting the V _off signal is composed of three V _off 1 signal transmission pattern, V _off 2 signal transmission pattern, three V _off 3 signal transmission pattern as disclosed in Korean Patent Application No. 99-13650. If V _off 1 signal transmission pattern is the shortest and the pattern length is increased in the order of V _off 2 and V _off 3 signal transmission patterns, the pattern resistances acting on the three signal transmission patterns are all different (V _off 1 V _off 2 V _off 3) The V _off signal, which should be the same for all the gate lines, is changed so that the brightness of the screen is not uniform, and the screen is divided enough to be visually recognized due to the difference in brightness.

Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to change a gate driving signal by a signal transmission pattern formed on a TFT substrate when driving a liquid crystal display by forming a signal transmission pattern on a TFT substrate. The minimum is to prevent display degradation.

Other embodiments of the present invention will become more apparent from the following detailed description of the invention.

1 is an exploded perspective view of a liquid crystal display according to the present invention.

FIG. 2 is a partially enlarged plan view illustrating an enlarged portion of the liquid crystal display panel of FIG. 1; FIG.

FIG. 3 is a rear perspective view of the gate tape carrier package of FIG. 1 with the rear surface facing upward. FIG.

FIG. 4 is a partially enlarged plan view of the liquid crystal display panel with the integrated printed circuit board, the gate tape carrier package, and the data tape carrier package removed from the liquid crystal display panel of FIG.

5 to 7 is an operation explanatory diagram for explaining the operation of the present invention.

In order to achieve the object of the present invention, an LCD device includes an integrated printed circuit board on which a gate driving signal and a data driving signal are generated, at least one gate line group composed of a plurality of gate lines, and a plurality of data lines. A liquid crystal display panel including a TFT substrate including at least one data line group intersecting the gate line groups and a thin film transistor connected to the gate line and the data line, a flexible substrate, and a flexible substrate. Means for determining at least one data driving signal application time at which one end has an input line connected to the integrated printed circuit board, a data IC connected to the input line, and one side connected to the data IC, and the other side has an output line connected to the data line group And a flexible substrate, a gate IC formed on the substrate, and a gate IC At least one input line for receiving a gate driving signal from a printed circuit board, a plurality of bypass lines surrounding a gate IC and a predetermined signal is input at one end and a predetermined signal is output at the other end. A gate drive signal application timing determining means, a main drive signal application pattern formed on a TFT substrate to apply a gate drive signal to an input line of any one of the gate drive signal application timing determining means from an integrated printed circuit board, and a gate drive signal application A signal which is formed between the timing determining means and the adjacent gate driving signal application timing determining means, and which connects the output side of the bypass line formed in any one of the gate driving signal application timing determining means and the input line of the adjacent gate driving signal application timing determining means. Transmission pattern, when any gate driving signal is applied A sub-drive signal composed of a shared signal transmission pattern connected to the bypass line of the gate drive signal application timing determining means adjacent to the output side of the remaining bypass line formed in the positive means, and the gate drive signal is shared to prevent modulation of the gate drive signal; It includes an application pattern.

Hereinafter, an embodiment of the liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view for explaining an internal configuration of a liquid crystal display according to the present invention. The liquid crystal display 601 is generally viewed as a display unit 200, a backlight assembly 300, a chassis 400, and a cover. It consists of 500.

First, the backlight assembly 300 is composed of an optical sheet 310, a light guide plate 320, a lamp assembly 330, a reflector 340, and a mold frame 350.

The display unit 200 again applies the driving signal to the liquid crystal display panels 240 and 250, the liquid crystal (not shown), and the driving signal to the liquid crystal display panels 240 and 250, and determines the timing at which the driving signals are applied. And an integrated printed circuit board 230, and the liquid crystal display panels 240 and 250 are composed of the TFT substrate 240 and the color filter substrate 250 again.

Hereinafter, the driving signal application timing determining means will be referred to as a gate tape carrier package and a data tape carrier package, respectively.

The TFT substrate 240 is a rectangular transparent substrate, and tens to millions of thin film transistors are formed on the transparent substrate by a semiconductor thin film process.

As described above, a data line having a predetermined width is connected to a source terminal of the thin film transistor by a metal process such as sputtering, and a gate terminal of the thin film transistor is orthogonal to the data line in an insulated state from the data line. The gate line is in communication.

Accordingly, when a predetermined voltage is applied to the gate line while a predetermined power is applied to the data line, the thin film transistor is turned on and power is applied to the drain terminal of the thin film transistor.

The drain terminal is electrically connected to a pixel electrode having a predetermined area of a conductive and transparent indium tin oxide material.

Meanwhile, an indium tin oxide material and an RGB pixel are formed on the front surface of the color filter substrate 250 facing the TFT substrate 240 thus formed, and liquid crystal is injected between the color filter substrate 250 and the TFT substrate 240. do.

More specifically, a gate signal transmission pattern and a resistance reduction pattern are formed on the TFT substrate 240.

Referring to FIG. 2, the plurality of gate lines and data lines formed on the TFT substrate 240 may be gathered to form one gate line group 241 and a data line group 242.

In the present invention, three gate line groups 241a, 241b, 241c; 241 and six data line groups are formed. In FIG. 2 or 4, two of the six data line groups 242a and 242b are formed. Only 242).

As described above, the TFT substrate 240 including the gate line group 241, the data line group 242, the thin film transistor, and the pixel electrode may be gated from one side of the TFT substrate 240 toward the data line group 242. The main gate signal transmission patterns 243a, 243b, 243c; and 243, which transfer gate driving signals to the other side of the TFT substrate 240 on the line group 241 side, are located between the gate line group and the gate line group, and drive the gate. A gate signal transmission pattern composed of the first and second shared gate signal transmission patterns 244 and 245 in which the signal is shared is formed.

More specifically, referring to FIG. 2 or FIG. 4, the main gate signal transmission patterns 243 are three in one embodiment. As shown in FIG. 2, one end portion is formed outside the outermost data line group 242a as shown in FIG. 2. Is formed, and the other end is formed to be adjacent to the gate line group 241a located at the closest distance to the data line group 242a.

As described above, the second and third shared gate signal transmission patterns 244 and 245 are formed between the gate line groups 241a, 241b and 241c, but their shapes are not the same and change with a certain rule.

Specifically, the second and third shared gate signal transmission patterns 244 and 245 have wiring widths suitable for preventing the pattern resistance from increasing and at least two signal lines formed in the gate tape carrier package to be described later and further required to further reduce the pattern resistance. Is shorted.

Before describing the second and third shared gate signal transmission patterns 244 and 245 in order to facilitate understanding of the present invention, the data tape carrier package 220 and the gate tape carrier package 210 will be described first. The third shared gate signal transmission patterns 244 and 245 will be described in more detail.

Referring to FIG. 2, the data tape carrier package 220 is configured as six embodiments, and the first data tape carrier package 221 is formed at the outermost side, and the second data tape carrier package ( 222).

The first data tape carrier package 221 is separate from the base substrate 221a, the gate signal transmission lines 221b, 221c and 221d connecting the both ends of the base substrate 221a, and the gate signal transmission lines 221b, 221c and 221d. It consists of the data drive drive IC 221e provided in the position, the input line 221f and the output line 221g connected to the data drive drive IC 221e.

In this case, the base substrate 221a may be a flexible printed circuit (FPC) or a flexible printed circuit (FPC) or a circuit pattern formed on a thin tape, and the input line 221f may be an integrated printed circuit. The output line 221g of the first data tape carrier package 221 is connected to the data line group 242a located at the outermost side by an anisotropic conductive film (not shown).

In addition, one end of the gate signal transmission lines 221b, 221c, and 221d is also connected to the integrated printed circuit board 230, and the other end is connected to the main gate signal transmission patterns 243a, 243b, and 243c described above.

In this case, the gate signal transmission lines 243a, 243b, and 243c should be formed outside the first data tape carrier package 221 as shown in FIG. 2.

On the other hand, the second data tape carrier package 222 is connected to the remaining data line group 242b. The second data tape carrier package 222 includes the base substrate 222a, the data driving drive IC 222e, It consists of an input line 222f and an output line 222g.

At this time, the output line 222g is connected to the remaining data line group 242b by an anisotropic conductive film (not shown).

The gate tape carrier package 210 has a very unique structure compared to the data tape carrier packages 221 and 222 described above.

2 or 3, the gate tape carrier package 220 may include three base substrates 212a, 214a, and 216a, gate drive driver ICs 212j, 214j, and 216j, and gate drive drives. Input lines 212c, 214f, and 216i, gate driving drive ICs of which one end is connected to the input terminals of the ICs 212j, 214j, 216j and the other end extends to the one end of the base substrates 212a, 214a, and 216a. The one end is connected to the output terminals of 212b, 214b, and 216b.

On the other hand, the other end is similarly the output line (212k, 214k, 216k) and the input line (212c, 214f, 216i) and the gate drive drive IC (212j, 214j) extending to the one end of the base substrate (212a, 214a, 216a) , 216j) and bypass lines (a, b, d, e, g, h) extending at both ends to one end of the base substrates 212a, 214a, and 216a while surrounding the output lines 212k, 214k, and 216k. It is composed.

In this case, at least two bypass lines a, b, d, e, g, and h should be formed when three gate tape carrier packages 212, 214, and 216 are used.

That is, when the number of gate tape carrier packages 212, 214, 216 is defined as n, and the number of bypass lines a, b, d, g, and h formed in each gate tape carrier package 212, 214, 216 is defined as X, The number of vise pass lines X must be equal to or greater than (n-1). Referring to <Equation 1> is as follows.

X

(n-1)

For example, if 10 gate tape carrier packages are used for a liquid crystal display device having a large effective display screen and requiring a high resolution of XGA or higher, each gate tape carrier package has at least 9 or more than 9 bypass lines. To form.

The bypass line is set as shown in Equation 1 so that the gate driving signal generated from the integrated printed circuit board 230 is individually applied to each bypass line.

When the output lines 212k, 214k, 216k of the gate tape carrier packages 212, 214, 216 configured as described above are all connected to the gate line groups 241a, 241b, 241c by the anisotropic conductive film, as shown in FIG. As shown in FIG. 212c of the gate tape carrier package 212 closest to the first data tape carrier package 221, an anisotropic conductive film has an end portion of the first gate signal transmission pattern indicated by 243c. Connected.

The remaining main gate signal of 243b and 243a of the gate tape carrier package 212 that is closest to the first data tape carrier package 221 is provided at the input terminal of the bypass line indicated by a and b. The transmission patterns are all connected.

The ends of the bypass lines, indicated by reference numerals 243b and 243a, are connected to the second shared gate signal transmission pattern 244 described above.

In this case, the second shared gate signal transmission pattern 244 is formed between the gate line group 241a and the gate line group 241b, and the shape of the third shared gate signal transmission pattern 245 has a predetermined rule. This will be described with reference to FIG. 4.

First, a second shared gate signal transmission pattern 244 is formed between the gate line group 241a formed near the end of the main gate signal transmission pattern 243 and the next gate line group 241b.

The second shared gate signal transmission pattern 244 is composed of two parts shown by reference numerals 244a and 244b. One of the second shared gate signal transmission patterns 244a and 244b has one end as described above. Similarly, it is connected to the bypass line indicated by reference numeral b, and the other end is connected to the input line indicated by reference numeral 214f of the adjacent gate tape carrier package 214.

One end of the other second shared gate signal transmission pattern 244b is connected to the bypass line indicated by reference a, and the other end is denoted by d, e of the adjacent gate tape carrier package 214. It is simultaneously connected to the two bypass lines shown.

It is important here that the width of the second shared gate signal transmission pattern 244b is the same, and the width of the second shared gate signal transmission pattern 244b should be at least equal to the width connected to both the bypass lines d and e.

The third shared gate signal transmission pattern 245 is formed between the second gate tape carrier package 214 and the next gate tape carrier package 216 adjacent to each other among the three gate tape carrier packages 212, 214, and 216.

The third shared gate signal transmission pattern 245 has one signal transmission pattern 245a since there is no longer a gate tape carrier package to transmit the gate driving signal.

One end of the signal transmission pattern 245a of the third shared gate signal transmission pattern 245 is commonly connected to one end of the bypass line shown by reference numeral d and e, and the other end is denoted by g, Both the bypass line indicated by reference numeral h and the input line indicated by reference numeral 216i are connected.

In this case, the width of the third shared gate signal transmission pattern 245 should be formed to be at least equal to the width of the sum of the signal input line 216i and the two bypass lines g and h formed in the gate tape carrier package 216.

As such, the unique shapes of the second and third shared gate signal transmission patterns 244 and 245 formed on the TFT substrate 240 play an important role in solving the object of the present invention. 244,245) will be described.

The accompanying Figure 5 is the first gate tape carrier packages turned on (212) - V _off signal generated in the drawing shown to be applied to the off-signal (V _off signal), an integrated printed circuit board 230 includes a first data tape carrier After being applied to the gate signal transmission line 221b of the package 221, it is applied to the first gate signal transmission pattern shown by 243c and then to the input line of the gate tape carrier package 212 shown by 212c. .

Thereafter, the gate driving drive IC 212j is sequentially applied to the gate line group 241a to display an image in the region I shown.

Subsequently, when all the images are displayed in region I, the integrated printed circuit board 230 applies a V _off signal to the gate signal transmission line 221c as shown in FIG. 6, and the V _off signal is indicated by the reference numeral 243b. After being applied to the gate signal transmission pattern, it is applied to the bypass line of the gate tape carrier package 212 indicated by reference numeral b, and then to the signal transmission pattern 244a of the second shared gate signal transmission pattern 244. It is then input to the input line of the gate tape carrier package 214, indicated at 214f.

Then, the V _off signal is input to the gate driving drive IC 214j and then applied to the gate line group 241b so that the image is displayed in the region II shown.

Subsequently, when an image is displayed in region II, the integrated printed circuit board 230 applies a V _off signal to the gate signal transmission line 221d as shown in FIG. 7, and the V _off signal is indicated by the reference numeral 243a. After being applied to the gate signal transmission pattern, and then applied to the bypass line of the gate tape carrier package 212 shown by a, one side of the signal transmission pattern 244b of the second shared gate signal transmission pattern 244. Is applied to the end.

Thereafter, the V _off signal is supplied to the bypass line of the gate tape carrier package 214 shown by reference numeral d and reference numeral e, and then, through one end of the third shared gate signal transmission pattern 245. g, is applied to the input line 216i of the gate tape carrier package 216, as well as the bypass line of the gate tape carrier package 216, indicated by reference h.

The V _off signal applied to the input line 216i is applied to the gate driving drive IC 216j and then to the gate line group 241c to display an image in the region III.

Here, the other end of the signal transmission pattern 244b of the second shared gate signal transmission pattern 244 having one end connected to the end of the bypass line indicated by reference a is a width that is connected to both the reference d and the reference e. Since the V _off signal has a magnitude and the current drops by 1/2, the resistance is also reduced by 1/2, thereby connecting to one end of the signal transmission pattern 245a of the third shared gate signal transmission pattern 245. do.

Further, the V _off signal applied to one end of the signal transmission pattern 245a of the third shared gate signal transmission pattern 245 is denoted by g and h before being applied to the input line shown by reference numeral 216i. By being connected to all of the bypass lines shown, the current drops to one third, so that the resistance is also reduced to one third and is input to the gate driving drive IC 216j.

The longer the gate tape carrier package 212, 214, 216 moves away from the first data tape carrier package 221, the longer the transmission pattern for transmitting the V _off signal becomes, and the resistance increases in proportion to the length of the transmission pattern. By actively preventing the modulation and distortion of the V _off signal by the display quality degradation is not prevented.

In the present invention, a case of three gate tape carrier packages is described as a preferred embodiment. However, even when there are five or more gate tape carrier packages, the present invention can be applied in the same manner as the above-described embodiment, which limits the wiring width of the signal transmission pattern. It can be maximized in space, as well as the characteristics of the resistance and the relationship between the voltage and the current, that is, the resistance is also reduced when the current is reduced under the same voltage, thereby eliminating the gate printed circuit board of the liquid crystal display device. This can not only significantly reduce the thickness but also solve the problem of deterioration of image quality, which may occur incidentally by removing the gate printed circuit board.

As described in detail above, the problem caused by the high resistance of the signal transmission pattern, which must be formed on the TFT substrate by removing the gate printed circuit board, is improved by improving the signal transmission pattern and reducing the thickness of the liquid crystal display device. There is an effect that the image quality is not degraded.

Claims (3)

An integrated printed circuit board generating a gate driving signal and a data driving signal; At least one gate line group composed of a plurality of gate lines, at least one data line group composed of a plurality of data lines and intersecting the gate line groups, a thin film connected to the gate line and the data line A liquid crystal display panel comprising a TFT substrate including a transistor; A flexible substrate, an input line formed on the substrate, one end of which is connected to the integrated printed circuit board, a data IC connected to the input line, and an output line connected to the data IC and the other side connected to the data line group. At least one or more data driving signal application timing determining means; A flexible substrate, a gate IC formed on the substrate, an input line connected to the gate IC, for receiving a gate driving signal from the integrated printed circuit board, a predetermined signal is input to one end while surrounding the gate IC, At least one gate driving signal application timing determining means including a plurality of bypass lines to which a predetermined signal is output; A main drive signal application pattern formed on said TFT substrate for applying a gate drive signal from said integrated printed circuit board to said input line of any one of said gate drive signal application timing determination means; Is formed between the gate driving signal application timing determining means and the gate driving signal application timing determining means, wherein the output side of the bypass line formed in any one of the gate driving signal application timing determining means and the adjacent gate driving signal application timing A signal transmission pattern connecting the input line of the determining means, connected to an output side of the remaining bypass line formed in any one of the gate driving signal application timing determining means, and a bypass line of the adjacent gate driving signal application timing determining means And a sub driving signal applying pattern formed of a shared signal transmission pattern for preventing the modulation of the gate driving signal by a gate driving signal being shared. The liquid crystal display of claim 1, wherein a width of the shared signal transmission pattern is equal to or greater than a sum of all of the bypass lines formed in the gate driving signal application timing determining unit. The number of the bypass lines formed in the gate driving signal application timing determining means is X (n-1) (X is the number of bypass lines, n is the number of gate driving signal application timing determining means) Liquid crystal display device having a relationship of.