KR20010017604A - Apparatus for controlling phase lock loop and method thereof - Google Patents

Abstract

PURPOSE: A device and a method for controlling PLL(Phase Locked Loop) are provided to shorten the lock up time of a phase detector by boosting a frequency generated in the PLL to a desired control voltage. CONSTITUTION: The control device of PLL comprises a memory(110), a signal converter(10) and a controller(100). Reference data proportional to the frequency to be generated in a PLL in accordance with the selection of a channel or a band are stored in the memory(110). The signal converter(10) varies the voltage of a signal output from a phase detector(140) in accordance with a predetermined control signal. The controller(100) generates the predetermined control signal on the basis of the reference data stored in the memory.

Description

Control device and method of phase-locked loop {APPARATUS FOR CONTROLLING PHASE LOCK LOOP AND METHOD THEREOF}

The present invention relates to a phase locked loop, and more particularly, to an apparatus and a method for minimizing lac time.

1 is a schematic configuration diagram of a conventional phase locked loop.

Typically, a phase-locked loop (PLL: referred to as a "phase-locked loop" below PHASE LOCK PLOOP) is a phase detector (called "phase detector" below PHASE DETECTOR) and a loop filter (called "loop filter" below LOOP-FILTER) And a voltage controlled oscillator (VCO: VOLTAGE CONTROLED OSCILLATOR) and a divider ("VIVI" and "divider").

The phase-locked loop is intended to compensate for the problem that the output frequency may be shaken depending on the characteristics of the device or the device used when the specific frequency is oscillated. The phase-locked loop as described above is used when generating an intermediate frequency or a carrier wave of a wireless terminal. Usually, the frequency generated from the phase-locked loop is fixed. However, in the case of a terminal using a dual mode, the frequency used is greatly changed depending on the mode. That is, the need arises that the frequency generated in the phase-lock loop itself varies. Even in the case described above, if there is a need to change the frequency generated in the phase-locked loop may occur frequently.

In general, the operation of the phase locked loop divides the signal output from the voltage controlled oscillator at a constant ratio to detect the phase difference in the phase detector and adjusts the voltage controlled oscillator. Thereafter, the signal output from the voltage controlled oscillator is divided again to detect a phase difference from the reference frequency in the phase detector, and the voltage controlled oscillator is readjusted. However, there is a problem in that the above operation takes a long time when the frequency conversion width is large as described above.

It is therefore an object of the present invention to provide an apparatus and method for minimizing the lactime of a phase locked loop.

In order to achieve the above object, the present invention provides a phase synchronization loop control device including a phase detector, a loop filter, an amplifier, and a voltage controlled oscillator, which is proportional to a frequency to be generated in the phase synchronization loop according to channel or band selection. A memory storing one reference data, a signal converter for changing a voltage value of a signal output from a phase detector according to a predetermined control signal, and reference data stored in the memory according to the channel or band selection It characterized in that it comprises a control unit for generating the predetermined control signal.

1 is a schematic configuration diagram of a conventional phase locked loop.

2 is a schematic block diagram for controlling a phase locked loop according to an embodiment of the present invention.

3 is a schematic circuit diagram for controlling a phase locked loop according to an embodiment of the present invention.

4 is a graph showing a change in a signal according to an embodiment of the present invention.

5 is a control flowchart for controlling the operation of the phase locked loop according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Specific details appear in the following description, which is provided to aid a more general understanding of the present invention, and it should be understood by those skilled in the art that the present invention may be practiced without these specific details. It will be self explanatory. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a schematic block diagram for controlling a phase locked loop according to an embodiment of the present invention.

3 is a schematic circuit diagram for controlling a phase locked loop according to an embodiment of the present invention.

4 is a graph showing a change in a signal according to an embodiment of the present invention.

5 is a control flowchart for controlling the operation of the phase locked loop according to an embodiment of the present invention.

A configuration according to an embodiment of the present invention will be described below with reference to FIG. 1.

The controller 100 controls the overall operation of the wireless terminal, and performs an operation for controlling the phase locked loop according to the embodiment of the present invention. The memory 110 may include a ROM that stores an operating program, an electrically programmable EEPROM, and a RAM. The memory 110 stores reference data for quickly operating frequency conversion by changing the phase detector 140 output signal of the phase locked loop according to the embodiment of the present invention. The transceiver 101 is controlled by the controller 100 and transmits various data to the base station through an antenna. In addition, the transceiver 101 converts and outputs a radio signal received through the antenna.

The signal converter 10 is controlled by the controller 100 and changes the voltage value of the signal output from the phase detector.

The signal converter 10 includes a PDMSE MODULATION GENERATOR 120, a digital analog converter 130, and an adder 160.

The PDM generator 120 outputs a pulse modulated signal having a predetermined density under the control of the controller. The signal output from the PDM generator 120 is converted into an analog signal by the DA converter 10 and supplied to the adder 160. The adder 160 adds and outputs the signal output from the phase detector 140 and the signal output from the DA converter 130. In the configuration of FIG. 2, the adder 160 is positioned between the loop filter 150 and the amplifier 170, but the position thereof may be located at the front end of the loop filter 150 or at the front end of the voltage controlled oscillator 180. Of course it can.

The phase detector 140 detects a phase of an input reference frequency and a feedback frequency and outputs a current according to a phase difference. The amplifier 170 amplifies and outputs a signal input from the phase detector 100. The loop filter 150 may be configured as a low pass filter. The voltage controlled oscillator 180 oscillates a frequency in proportion to the input voltage. The divider 190 divides the output frequency of the voltage controlled oscillator 180 by N times and feeds it back to the phase detector 140.

Looking at the specific circuit configuration according to an embodiment of the present invention with reference to FIG. The signal output from the PDM generator 120 is converted into a DC component by an RC filter composed of a resistor R1 and a capacitor C1. The changed signal is added to the signal output from the phase detector 140 by the adder 160 (point “A”), and the voltage is boosted and output. As shown in FIG. 4, the first control signal PDM_in is added to the output signal V_source of the phase detector 140 to output the output signal V_load.

The operation according to the present invention is described below with reference to FIGS. 2 to 5.

In step 500, the controller 100 checks whether a situation in which the output frequency of the phase locked loop needs to be converted by handoff or band conversion occurs. The detection of the situation may be made by detecting a handoff command received from the base station or a key input for selecting a band of the user. If a situation for frequency conversion occurs, the process proceeds to step 510 to detect the reference data stored in the memory 110 and outputs a pulse density modulation signal through the PDM generator 120. An example of reference data stored in the memory 110 is shown in Table 1 below.

Channel or band frequency parameter Channel 1 300 MHz 100 Channel 2 310 MHz 110 ... ... 2nd band 500 MHz 190

For example, if a frequency conversion request to channel 1 is generated by a handoff command from a base station, that is, when generation of a frequency of 300 MHz is required, the output pulse density of the PDM generator 120 accordingly becomes "100". The PDM generator 120 is controlled by a predetermined value. In step 520, the DA converter 10 converts the input pulse signal into a digital signal (DC component) through an RC filter and outputs the digital signal. The output signal is added to the output signal of the phase detector 140 by the adder 160. That is, the voltage input to the voltage controlled oscillator 180 is stepped up.

Then, if the control voltage of the voltage controlled oscillator 180 to obtain the desired frequency is V_load, the voltage of V_load is obtained by the signal already output from the PDM generator 120, so that the time for the phase-up loop lockup is shortened. Able to know. Generally, in order to obtain a voltage value of V_load, phase synchronization is performed by gradually increasing the voltage value of the voltage controlled oscillator 180 as mentioned in the related art.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims below, but also by the equivalents of the claims of the present invention.

As described above, the present invention can shorten the lockup time of the phase detector by boosting the control voltage of a desired frequency in advance through the signal converter.

Claims (10)

In the phase synchronization loop control device having a phase detector, a loop filter, an amplifier, and a voltage controlled oscillator, A memory storing reference data proportional to the frequency to be generated according to channel or band selection; A signal converter which changes a voltage value input to the voltage controlled oscillator according to a predetermined control signal; And a controller for generating the control signal according to the reference data stored in the memory by the channel or band selection. The method of claim 1, wherein the signal conversion unit, And located between the phase detector and the loop filter. The method of claim 1, wherein the signal conversion unit, And located between the loop filter and the amplifier. The method of claim 1, wherein the signal conversion unit, And located between the amplifier and the voltage controlled oscillator. The method according to any one of claims 1 to 4, wherein the signal conversion unit, A PD generator for generating a pulse density converted signal by the control signal output from the controller; A digital analog converter for converting the output signal of the PD generator into analog; And an adder for adding an output signal of the digital to analog converter to an input signal of the voltage controlled oscillator. The method of claim 5, wherein the digital to analog converter, And a resistor and a capacitor. A method of controlling a phase locked loop having a memory storing reference data proportional to a frequency to be generated in the phase locked loop according to channel or band selection, Detecting frequency conversion information for converting a frequency generated in the phase locked loop; Reading the reference data stored in the memory according to the detected frequency conversion information to generate a first control signal; And adding a signal input to the first control signal and the voltage controlled oscillator of the phase-locked loop. The method of claim 7, wherein the adding process, Dropping or boosting a voltage input to the voltage controlled oscillator of the phase-locked loop. The method of claim 7, wherein the first control signal, A method of digitally converting a pulse amplitude modulated signal. The method of claim 9, wherein the first control signal, And a signal obtained by filtering the pulse amplitude modulated signal by an ALSI filter.