KR20010011553A - method of forming a gate electrode in semiconductor device - Google Patents
method of forming a gate electrode in semiconductor device Download PDFInfo
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- KR20010011553A KR20010011553A KR1019990030976A KR19990030976A KR20010011553A KR 20010011553 A KR20010011553 A KR 20010011553A KR 1019990030976 A KR1019990030976 A KR 1019990030976A KR 19990030976 A KR19990030976 A KR 19990030976A KR 20010011553 A KR20010011553 A KR 20010011553A
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- titanium silicide
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- silicide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title abstract description 21
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract 2
- 230000001681 protective effect Effects 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 66
- 239000011148 porous material Substances 0.000 description 11
- 239000010410 layer Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010406 interfacial reaction Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 형성 방법에 관한 것으로, 보다 구체적으로는 폴리실리콘막과 티타늄 실리사이드막의 적층 구조로 이루어진 게이트 전극을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly, to a method of forming a gate electrode having a laminated structure of a polysilicon film and a titanium silicide film.
일반적으로, 게이트 전극은 모스 트랜지스터를 셀렉팅하는 전극으로서, 주로 불순물이 도핑된 폴리실리콘막으로 형성되거나 또는 불순물이 도핑된 폴리실리콘막과 텅스텐 실리사이드막(WSi2)의 적층막으로 형성된다.In general, the gate electrode is an electrode for selecting a MOS transistor, and is mainly formed of a polysilicon film doped with impurities or a laminated film of a polysilicon film and a tungsten silicide film WSi 2 doped with impurities.
그러나, 상기한 불순물이 도핑된 폴리실리콘막과 불순물이 도핑된 폴리실리콘막/텅스텐 실리사이드막은 낮은 집적도를 갖는 반도체 소자에는 용이하게 사용되나, 현재의 고집적 반도체 소자의 미세 게이트 전극으로는 낮은 저항값 특성을 만족시키지 못하여, 이를 사용하는데 어려움이 있다.However, the above-described impurity doped polysilicon film and impurity-doped polysilicon film / tungsten silicide film are easily used in semiconductor devices having low integration, but have low resistance value characteristics as the fine gate electrodes of the current highly integrated semiconductor devices. There is a difficulty in using it because it is not satisfied.
이에 따라, 종래에는 텅스텐 실리사이드막보다 전도 특성이 우수한 티타늄 실리사이드막(TiSi2)을 폴리실리콘막 상부에 적층하여 게이트 전극을 형성하는 방법이 제안되었는데, 이 방법을 개략적으로 설명하면 다음과 같다.Accordingly, in the related art, a method of forming a gate electrode by stacking a titanium silicide layer (TiSi 2 ) having superior conductive properties than a tungsten silicide layer on a polysilicon layer has been proposed.
반도체 기판 상부에 게이트 산화막을 열성장 또는 증착 방식에 의하여 형성한 다음, 게이트 산화막 상부에 불순물이 도핑된 폴리실리콘막을 소정 두께로 증착한다. 그 후, 폴리실리콘막 상부에 물리적 증착 방식으로 티타늄 실리사이드막을 증착한다. 이때, 증착시 티타늄 실리사이드막은 비정질 상태이다.A gate oxide film is formed on the semiconductor substrate by thermal growth or vapor deposition, and then a polysilicon film doped with impurities is deposited on the gate oxide film to a predetermined thickness. Thereafter, a titanium silicide film is deposited on the polysilicon film by physical vapor deposition. At this time, the titanium silicide film is in an amorphous state during deposition.
그런 다음, 기판 결과물에 소정 온도에서 수 초 동안 급속 열처리 공정(Rapid Thermal Process:이하 RTP로 영문표기함)을 실시하여, 비정질 상태의 티타늄 실리사이드막을 결정질 상태의 티타늄 실리사이드막으로 상변화시킨다.Subsequently, a rapid thermal process (hereinafter referred to as RTP) is performed on the substrate resultant at a predetermined temperature for a few seconds to change the amorphous titanium silicide film into a crystalline titanium silicide film.
이어서, 티타늄 실리사이드막 상부에 고집적 소자에서 자기 정합 콘택 형성을 목적으로 사용되는 보호막으로 산화막 또는 질화막을 증착한다. 이어, 공지의 포토리소그라피 방식을 이용하여 보호막과 티타늄 실리사이드막, 도핑된 폴리실리콘막 및 게이트 절연막을 식각하여, 게이트 전극을 형성한다.Subsequently, an oxide film or a nitride film is deposited on the titanium silicide film as a protective film used for forming a self-aligned contact in the highly integrated device. Subsequently, the protective layer, the titanium silicide layer, the doped polysilicon layer, and the gate insulating layer are etched using a known photolithography method to form a gate electrode.
그런데, 비정질의 티타늄 실리사이드막은 미세한 기공(void)이 존재하거나 또는 기공이 없더라도 조밀도가 매우 낮다. 이러한 비정질의 티타늄 실리사이드막을 750℃ 이상의 고온하에서 RTP 처리를 하여 결정질 상태의 티타늄 실리사이드막으로 형성하면, 이 박막 내부에 기공이 발생된다. 부연하면, RTP 공정을 통해서 낮은 저항을 갖는 결정질 상태의 티타늄 실리사이드막 형성시, 박막의 수축이 급속히 진행되어 국부적인 기공이 티타늄 실리사이드막에 발생된다.However, the amorphous titanium silicide film has a very low density even if there are fine pores or no pores. When the amorphous titanium silicide film is subjected to RTP treatment at a high temperature of 750 ° C. or higher to form a titanium silicide film in a crystalline state, pores are generated in the thin film. In other words, when the titanium silicide film having a low resistance is formed through the RTP process, shrinkage of the thin film proceeds rapidly, and local pores are generated in the titanium silicide film.
이와 같이, 게이트 전극에 기공이 존재하면, 게이트 전극의 유효폭이 감소할수록 게이트 전극의 저항이 증가되고 반도체 소자의 동작 및 신뢰성에 문제가 발생된다.As such, when pores exist in the gate electrode, as the effective width of the gate electrode decreases, the resistance of the gate electrode increases and a problem occurs in the operation and reliability of the semiconductor device.
본 발명은 RTP 공정에 통해서 형성되는 결정질 상태의 티타늄 실리사이드막에 기공이 발생되는 것을 최대한 억제하여, 비저항을 감소시킬 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는데 목적이 있다.An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of suppressing the generation of pores in the titanium silicide film of the crystalline state formed by the RTP process to the maximum, thereby reducing the specific resistance.
도 1 및 도 2는 본 발명에 따른 게이트 전극 형성 방법을 순차적으로 나타낸 단면도.1 and 2 are cross-sectional views sequentially illustrating a method of forming a gate electrode according to the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
1 ; 반도체 기판 2 ; 게이트 산화막One ; Semiconductor substrate 2; Gate oxide
3 ; 폴리실리콘막 4 ; 비정질의 티타늄 실리사이드막3; Polysilicon film 4; Amorphous titanium silicide film
5 ; 결정질의 티타늄 실리사이드막 6 ; 보호막5; Crystalline titanium silicide film 6; Shield
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 게이트 전극 형성 방법은 다음과 같다.In order to achieve the above object of the present invention, the gate electrode forming method according to the present invention is as follows.
반도체 기판상에 게이트 산화막과 폴리실리콘막을 순차적으로 증착한다. 이어서, 폴리실리콘막상에 비정질의 티타늄 실리사이드막을 1∼20Å/초의 속도, -50∼100℃의 온도하에서 증착한다. 그런 다음, 기판 결과물을 급속 열처리하여 결정질의 티타늄 실리사이드막을 형성하는데, 급속 열처리는 750∼900℃의 온도하에서 10∼60초 동안 실시하고, 특히 온도 증가비(ramping rate)는 50∼150℃/초로 한다.A gate oxide film and a polysilicon film are sequentially deposited on the semiconductor substrate. Subsequently, an amorphous titanium silicide film is deposited on the polysilicon film at a rate of 1 to 20 Pa / sec and a temperature of -50 to 100 ° C. The resulting substrate is then subjected to a rapid heat treatment to form a crystalline titanium silicide film, wherein the rapid heat treatment is carried out at a temperature of 750 to 900 ° C. for 10 to 60 seconds, in particular at a temperature ramping rate of 50 to 150 ° C./sec. do.
결정질의 티타늄 실리사이드막상에 보호막을 증착한 후, 전체를 패터닝하여 게이트 전극을 형성한다.After depositing a protective film on the crystalline titanium silicide film, the whole is patterned to form a gate electrode.
상기된 본 발명에 의하면, 비정질의 티타늄 실리사이드막을 낮은 온도 및 속도 조건에서 증착하게 되므로, 비정질의 티타늄 실리사이드막이 균일해진다. 따라서, 후속 RTP 공정을 실시하여 결정질의 티타늄 실리사이드막을 형성하게 되면, 이 박막에 기공이 거의 발생되지 않게 된다.According to the present invention described above, since the amorphous titanium silicide film is deposited at low temperature and speed conditions, the amorphous titanium silicide film becomes uniform. Therefore, when the subsequent RTP process is performed to form a crystalline titanium silicide film, pores are hardly generated in the thin film.
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 및 도 2는 본 발명에 따른 게이트 전극 형성 방법을 순차적으로 나타낸 단면도이다.1 and 2 are cross-sectional views sequentially illustrating a method of forming a gate electrode according to the present invention.
먼저, 도 1을 참조하여, 반도체 기판(1) 상부에 게이트 산화막(2)을 공지의 열성장 또는 증착 방식에 의하여 형성한 다음, 게이트 산화막(2) 상부에 불순물이 도핑된 폴리실리콘막(3)을 소정 두께로 증착한다.First, referring to FIG. 1, a gate oxide film 2 is formed on a semiconductor substrate 1 by a known thermal growth or deposition method, and then a polysilicon film 3 doped with impurities on the gate oxide film 2 is formed. ) Is deposited to a predetermined thickness.
그런 다음, 비정질 상태의 티타늄 실리사이드막(4)을 폴리실리콘막(3)상에 증착한다. 여기서, 비정질의 티타늄 실리사이드막(4)은 개방 구조를 가지면서 하부층인 폴리실리콘막(3)과 계면 반응을 일으키기 때문에, 비정질과 결정질이 혼합상으로 형성된다. 따라서, 비정질의 티타늄 실리사이드막(4)을 균일하게 형성하기 위해서는, 증착 온도는 상온 이하가 되도록 하고 증착 속도는 수 십 Å/초 이내로 최대한 낮추어야 한다. 이에 따라, 본 발명에서 제시되는 증착 조건은 다음과 같다. 먼저, 온도는 -100℃ 내지 상온, 속도는 1∼20Å/초, 전력은 100∼1,000W, 압력은 0.1∼5mTorr이다.Then, an amorphous titanium silicide film 4 is deposited on the polysilicon film 3. Here, since the amorphous titanium silicide film 4 has an open structure and causes an interfacial reaction with the polysilicon film 3 as the lower layer, amorphous and crystalline are formed in a mixed phase. Therefore, in order to form the amorphous titanium silicide film 4 uniformly, the deposition temperature should be lower than room temperature and the deposition rate should be as low as possible within several tens of Pa / sec. Accordingly, the deposition conditions presented in the present invention are as follows. First, the temperature is from -100 deg. C to room temperature, the speed is from 1 to 20 mA / sec, the power is from 100 to 1,000 W, and the pressure is from 0.1 to 5 mTorr.
이러한 증착 조건으로 비정질의 티타늄 실리사이드막(4)을 증착한 후, RTP 공정을 실시하여 비정질의 티타늄 실리사이드막(4)을 도 2와 같이 결정질의 티타늄 실리사이드막(5)으로 형성한다. RTP 공정은 질소 또는 아르곤 가스 분위기에서 750∼900℃의 온도하에서 10∼60초 동안 실시한다. 또한, 온도 증가비를 50∼150℃/초로 한다.After depositing an amorphous titanium silicide film 4 under such deposition conditions, an RTP process is performed to form an amorphous titanium silicide film 4 as a crystalline titanium silicide film 5 as shown in FIG. 2. The RTP process is carried out in a nitrogen or argon gas atmosphere at a temperature of 750 to 900 ° C. for 10 to 60 seconds. In addition, the temperature increase ratio is 50-150 degreeC / sec.
이러한 RTP 공정을 통해 형성된 결정질의 티타늄 실리사이드막(5)에는 기공이 거의 존재하지 않게 된다. 그 이유는, 비정질의 티타늄 실리사이드막(4)이 저온 및 저속 조건하에서 증착되었기 때문이다. 부연하면, 만일 종래와 같이 비정질의 티타늄 실리사이드막(4)을 고온 및 고속으로 증착하게 되면, 비정질과 결정질의 혼합상으로 형성되고 폴리실리콘막(3)과 계면 반응을 일으키게 된다. 이로 인하여, RTP 공정시, 불균일한 상변태가 발생되어, 결정질의 티타늄 실리사이드막(5)에 기공이 발생된다. 따라서, 본 발명과 같이 저온 및 저속 조건으로 증착된 비정질의 티타늄 실리사이드막(4)을 RTP 공정을 통해서 결정질의 티타늄 실리사이드막(5)으로 형성하면, 기공이 거의 발생되지 않게 된다.Pores are hardly present in the crystalline titanium silicide layer 5 formed through the RTP process. The reason is that the amorphous titanium silicide film 4 was deposited under low temperature and low speed conditions. In other words, if the amorphous titanium silicide film 4 is deposited at a high temperature and high speed as in the prior art, it is formed in a mixed phase of amorphous and crystalline and causes an interfacial reaction with the polysilicon film 3. For this reason, in the RTP process, uneven phase transformation occurs, and pores are generated in the crystalline titanium silicide film 5. Therefore, when the amorphous titanium silicide film 4 deposited at low temperature and low temperature conditions as the present invention is formed of the crystalline titanium silicide film 5 through the RTP process, pores are hardly generated.
계속해서, 결정질의 티타늄 실리사이드막(5)상에 산화막 또는 질화막인 보호막(6)을 증착한 후, 전체 막들을 패터닝하면, 도 2에 도시된 게이트 전극이 완성된다.Subsequently, after the protective film 6, which is an oxide film or a nitride film, is deposited on the crystalline titanium silicide film 5, the entire films are patterned to complete the gate electrode shown in FIG.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면 비정질의 티타늄 실리사이드막을 저온 및 저속 조건하에서 증착하므로써, 비정질의 티타늄 실리사이드막을 균일하게 형성시킬 수가 있게 된다. 따라서, 균일한 비정질의 티타늄 실리사이드막을 RTP 처리하여 형성되는 결정질의 티타늄 실리사이드막에 기공이 발생되지 않게 된다.As described in detail above, according to the present invention, the amorphous titanium silicide film can be uniformly formed by depositing the amorphous titanium silicide film under low temperature and low speed conditions. Therefore, pores are not generated in the crystalline titanium silicide film formed by RTP treatment of a uniform amorphous titanium silicide film.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR1019990030976A KR20010011553A (en) | 1999-07-29 | 1999-07-29 | method of forming a gate electrode in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011027992A2 (en) | 2009-09-05 | 2011-03-10 | 주식회사 크리스텍 | Method and apparatus for growing a sapphire single crystal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011027992A2 (en) | 2009-09-05 | 2011-03-10 | 주식회사 크리스텍 | Method and apparatus for growing a sapphire single crystal |
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