KR20010011494A - Apparatus for receiving of digital TV - Google Patents

Abstract

PURPOSE: A receiving device of a digital TV is provided to use a four-level slicer in a channel equalizing process when reliability of a predicted value is high, after predicting a register value of a trellis coder in a transmitting side, and to use an eight-level slicer when the reliability of the predicted value is low, so as to minimize decision errors of slicers to prevent a deterioration of a signal to noise ratio(SNR), which is caused by a noise amplification of a feedback filter in a channel equalizer, even in a channel having a severe ghost, to improve the capacity of the channel equalizer. CONSTITUTION: A feed forward filter(74-1) attenuates the influence of a near ghost. A feedback filter(74-7) attenuates the influence of a remote ghost. An adder(74-2) adds an output of the feed forward filter(74-1) to an output of the feedback filter(74-7). The first to the third slicer(74-3-74-5) decide the added output of the adder(74-2) with a nearest signal level. A multiplexer(MUX)(74-6) selects one of outputs of the first to the third slicer(74-3-74-5) according to the output of a slicer predictor(75), and feeds back the selected output to the feedback filter(74-7).

Description

Apparatus for receiving of digital TV

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a receiver for digital television using vestigial side band (VSB) modulation, and more particularly to a channel equalizer.

In general, digital TVs have a much higher resolution and wider horizontal orientation than analog TVs, and CD-level sound is supplied in multiple channels.

Such digital TVs are being standardized by the US, Europe, and Japan in their own broadcasting methods and standards. In the United States, the transmission format adopts the residual sideband (VSB) method proposed by Zenith in the United States, the compression format adopts MPEG (MPEG) for video compression, and Dolby AC-3 for audio compression. The display format is specified to be compatible with existing display methods. In particular, the United States adopted the trellis-coded 8VSB transmission system as a standard in 1995 for terrestrial digital broadcasting, and has been broadcasting since the second half of 1998.

In this case, when the amplitude modulation of the signal, the VSB modulation modulates only the remaining part when one sideband signal of the two sidebands generated up and down about the carrier is greatly attenuated.

In other words, the DSB (Double Side Band), which uses both upper and lower sidebands, has a low bandwidth efficiency. Thus, SSB (Single Side Band) using only one side band has emerged.

In addition, the Grand Alliance (GA), the organization that unifies digital TV, adopted 8VSB as a terrestrial broadcast transmission system, and later the Advisory Committee on Advanced Television Service (ACATS), the FCC's advisory committee, also terrestrial. Decided to adopt 8VSB for broadcasting.

The 8VSB has 8 levels of transmitted signals. The 8VSB is allocated such that 4 data levels exist on the positive side and 4 data levels exist on the negative side based on '0'.

Therefore, if the broadcasting station modulates the digital data to 8VSB and sends it to the air through the antenna, the digital TV in each home can receive, demodulate and view it.

Fig. 1 is a block diagram showing the structure of a conventional transmission apparatus of a digital TV. The data randomizer 11 randomly outputs the data to the Reed-Solomon encoder 12, and the Reed-Solomon encoder 12. Re-Solomon encodes randomly input data, adds a 20-byte parity code, and outputs the parity code to the data interleaver 13. The data interleaver 13 interleaves the data according to a predetermined rule and outputs the data to the VSB encoder 14. The VSB encoder 14 converts the interleaved data from bytes into symbols and trellis-codes the multiplexer 15. Will output The multiplexer 15 muxes the trellis coded symbol sequence, the segment synchronization signal, and the field synchronization signal, and the pilot inserter 16 inserts a pilot signal into the muxed symbol string and outputs the result to the VSB modulator 17. The VSB modulator 17 modulates the symbol string into which the pilot signal is inserted into an 8VSB signal and outputs the RF string to the RF converter 18. The RF converter 18 converts the modulated baseband 8VSB signal into an RF band signal. Transmit through an antenna.

In this case, the VSB encoder 14 has 12 identical trellis encoders and precoders combined as interleavers for noise dispersion, as shown in FIG. It is composed together. At this time, the input symbol is 2 bits X ₂ X ₁ . X ₂ is precoded to Y ₂ (= Z ₂ ) in the precoder 31. On the other hand, in the trellis encoder 32, Y ₂ is not trellis coded, and only Y ₁ (= X ₁ ) is trellis coded to become two bits Z ₁ Z ₀ . The output 3-bit Z ₂ Z ₁ Z ₀ of the trellis encoder 32 is input to the 8-level symbol mapper 33 and mapped to 8-level symbols {± 7, ± 5, ± 3, ± 1}. .

Fig. 4 is a block diagram showing the configuration of a conventional digital TV receiver for receiving data modulated and transmitted to 8VSB as described above, in the reverse order of the transmitter. That is, the demodulator 41 converts the signal of the RF band to the base band and outputs the signal to the synchronization and timing recovery unit 42 and the comb filter 43. The synchronization and timing recovery unit 42 recovers the segment synchronization signal, the field synchronization signal, the symbol timing, and the like, and the comb filter 43 removes the NTSC interference signal and outputs it to the channel equalizer 44. The channel equalizer 44 compensates for channel distortion generated during the transmission of data through the transmission channel and outputs it to the phase decompressor 45. The phase decompressor 45 recovers the phase and then the VSB decoder 46 ) The VSB decoder 46 performs Viterbi decoding on the phase-restored data and outputs the data to the data deinterleaver 47. The data deinterleaver 47 deinterleaves the input data by reverse operation of the data interleaver, and then reads Reed-Solomon. Output to decoder 48. The Reed-Solomon decoder 48 decodes the Reed-Solomon-coded data and outputs the data to the data derandomizer 49. The data derandomizer 49 arranges the data in a reverse operation of the data randomizer.

At this time, the VSB decoder 46, as shown in Fig. 5, 12 identical trellis decoder is coupled to the deinterleaver.

As described above, the trellis-encoded 8VSB transmitting apparatus transmits 2 bits of information per transmission symbol. In this case, 4 VSB modulation is sufficient when trellis coding is not performed. However, since trellis coding adds 1 bit for each symbol, the signal level is doubled to 8VSB. In addition, the trellis coding as described above doubles the number of levels, but instead, the signal-to-noise ratio of about 1 dB is compared to 4 VSB without trellis coding in the Additive White Gaussian Noise (AWGN) channel. Signal to Noise Ratio (SNR) gain. That is, the 4VSB transmission system is inferior to the trellis coded 8VSB transmission system in the additive white Gaussian noise channel.

On the other hand, the trellis coded 8VSB has a signal-to-noise ratio gain of about 1 dB in the additive white Gaussian noise channel compared to the 4VSB without trellis coding, but the performance is lower in the channel with high distortion caused by distant ghost. That is, the trellis-coded digital 8VSB modulation method amplifies the noise more than the signal-to-noise ratio gain obtained by trellis coding because the amplification of the feedback filter of the channel equalizer 44 is large in a channel with large distortion caused by distant ghost. The signal-to-noise ratio decrease by

The reason for this is as follows.

6 is a detailed block diagram of the channel equalizer 44, a feed forward filter 61 to offset the effects of near ghosts, and a feed back filter to offset the effects of distant ghosts. (64), an adder 62 that adds the output of the feed forward filter 61 and the output of the feed back filter 64, and determines the output of the adder 62 as the signal level closest to the distance to the feed back filter. The slicer 63 which feeds back to 64 is comprised. Here, the slicer 63 is an eight-level {-7, -5, -3, -1, + 1, + 3, + 5, + 7} slicer.

In FIG. 6 configured in this manner, the feed forward filter 61 cancels the influence of the near ghost, and the feed back filter 64 cancels the influence of the distant ghost. When the adder 62 adds the output of the feed forward filter 61 and the output of the feed back filter 64 and outputs the slicer 63, the slicer 63 determines the input signal as the signal level closest to the distance.

However, since the output of the slicer 63 is input to the feed back filter 64, the determination error of the slicer 63 passes through the feed back filter 64, and the adder 62 returns the feed forward filter 61. Is added to the output.

Here, the performance of the slicer 63 is closely related to the number of levels of the signal. That is, since 8VSB has twice the number of levels compared to 4VSB, the interval between signal levels is reduced by approximately half when the signals have the same power. For this reason, the probability of determination error in the slicer 63 is very large. Therefore, the coefficient of the feedback filter 64 has a large value in a channel having a large ghost effect, and the larger the determination error of the slicer 63 is, the larger the noise amplification of the feedback filter 64 is. This greatly reduces the performance of the receiver.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a channel equalizer with a plurality of slicers having a different number of signal levels, and to select and receive one of them through prediction of trellis-coded data. To provide a receiving device of a digital TV to slice the.

1 is a block diagram showing a transmission apparatus of a conventional digital TV

FIG. 2 is a block diagram showing the structure of twelve VSB encoders of FIG.

3 is a block diagram illustrating each VSB encoder of FIG. 2;

4 is a block diagram showing a conventional receiving device of a digital TV

FIG. 5 is a block diagram showing the structure of twelve VSB decoders of FIG.

6 is a detailed block diagram of the channel equalizer of FIG.

7 is a block diagram showing the configuration of a receiving apparatus of a digital TV according to the present invention.

8 is a detailed block diagram of the channel equalizer of FIG.

9 (a) to 9 (c) show the types of slicers in the channel equalizer of FIG.

10 is a trellis diagram of trellis coded 8VSB

11 is a block diagram showing the structure of 12 slice predictors.

Explanation of symbols for main parts of the drawings

71: demodulator 72: synchronization and timing recovery unit

73: comb filter 74: channel equalizer

74-1: feed forward filter 74-2: adder

74-3 to 74-5: Slicer 74-6: mux

74-7: Feedback Filter 75: Slicer Predictor

76: phase restorer 77: 8VSB decoder

78: data deinterleaver 79: Reed-Solomon decoder

80: data derandomizer

A reception apparatus of a digital TV according to the present invention for achieving the above object comprises: an adder for adding outputs of a feed forward filter for removing near ghosts and a feed back filter for removing distant ghosts included in the transmitted signal; A slicing unit comprising a plurality of slicers having different number of signal levels and determining the output of the adder as the signal level closest to the distance and outputting the determined signal level value to the feedback filter; The channel equalizer is configured to include a slicer predictor for predicting trellis coded data values and selecting any one of the plurality of slicers according to the prediction result.

The slicer predictor selects a four-level slicer having a {-7, -3, + 1, + 5} signal level set when the trellis coded bit value of the transmitting side is zero predicted and the reliability of the predicted value is high. When the bit value is predicted to 1 and the reliability of the predicted value is high, a four-level slicer having a {-5, -1, + 3, + 7} signal level set is selected.

The slicer predictor selects an 8-level slicer if the reliability of the predicted value is low after predicting the trellis coded bit value of the transmitter.

The slicer predictor sets register m0m1 of the trellis encoder of the transmitting side as a state value, and predicts the trellis coded least significant bit value of the transmitting side with a state value having a minimum cumulative metric value at any time. Characterized in that.

The receiving apparatus of the digital TV according to the present invention includes a demodulator for trellis-coding, receiving data transmitted by the 8VSB modulation scheme, switching to baseband, and then eliminating interference by other broadcasting schemes, and a transmitting side from the output of the demodulator. After predicting the trellis-coded bit value of, the 4th level slicing is performed if the reliability of the prediction value is high, and the 8th level slicing is performed if the reliability of the prediction value is low, thereby compensating for the channel distortion of the data generated during transmission An equalizer, a trellis decoder for performing Viterbi decoding after restoring the phase of the channel equalized data, and an error correction unit for performing error correction after deinterleaving the trellis decoded data; Characterized in that the configuration.

The present invention predicts a value stored in register m1 of the trellis encoder on the transmitting side, selects a 4-level slicer if the reliability of the prediction result is high, and slices the received data by selecting an 8-level slicer if the reliability of the prediction result is low. To improve the performance of the channel equalizer.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 7 is a block diagram of a receiving apparatus of a digital TV according to the present invention, wherein a conventional receiver is further provided with a slicer predictor 75, and the channel equalizer 74 has a plurality of slicers 74-3 to 74-. 5) and a selection unit 74-6 for selecting any one of the plurality of slicers 74-3 to 74-5 by the control of the slice predictor 75.

That is, FIG. 8 is a detailed block diagram of the channel equalizer 74. The feed forward filter 74-1 cancels the influence of the near ghost, the feed back filter 74-7 cancels the influence of the distant ghost, An adder 74-2, which adds the output of the feed forward filter 74-1 and the output of the feed back filter 74-7, determines the output of the adder 74-2 as the signal level closest to the distance. According to the output of the first to third slicers 74-3 to 74-5 and the slicer predictor 75, one of the outputs of the first to third slicers 74-3 to 74-5 is selected And a multiplexer (hereinafter, referred to as mux) that feeds back to the feed back filter 74-7.

Here, the first slicer 74-3 is a four-level {-7, -3, + 1, + 5} slicer as shown in FIG. 9 (a), and the slice predictor 75 of the trellis encoder It is selected when the value of register m1 is predicted to be zero and the reliability of the predicted value is high. The second slicer 74-4 is a four-level {-5, -1, + 3, + 7} slicer as shown in FIG. 9 (b), and the slice predictor 75 of the trellis encoder It is selected when the value of register m1 is predicted to be 1 and the reliability of the predicted value is high. In addition, the third slicer 74-5 is an eight-level {-7, -5, -3, -1, + 1, + 3, + 5, + 7} slicer as shown in FIG. 9 (c), It is selected when the reliability of the value predicted by the slice predictor 75 is low.

That is, looking at the trellis encoder 32 of the transmitter of FIG. 3, the input bits Y ₂ , Y ₁ are replaced with the output bits Z _2, Z ₁ , and the output bit Z ₀ is the trellis encoder 32. Is determined by the value stored in register m1. The signal levels mapped according to the output bit strings {Z ₂ , Z ₁ , Z ₀ } of the trellis encoder 32 are determined, and the entire signal level set {-7, -5, -3, -1, +1, +3, +5, +7} are two sets of signal levels with the number of levels 4 depending on whether the value of bit Z ₀ is 0 or 1 {-7, -3, + 1, + 5} {-5, -1, + 3, + 7}. That is, when the value of Z ₀ is 0, the signal level of any one of the signal level set {-7, -3, + 1, + 5} is selected, and when the value of Z ₀ is 1, the signal level set { -5, -1, +3, +7} any one signal level is selected and output.

Therefore, if the value stored in register m1 of the trellis encoder 32 can be predicted, then the output signal level of the following trellis encoder 32 is the set of two signal levels {-7, -3, + 1, + 5 } Which one of {-5, -1, + 3, + 7} can be predicted, and using this information, instead of the eight-level slicer 74-5 as shown in FIG. Four-level slicers 74-3 or 74-4 such as a) or (b) may be used. Here, the four-level slicer has a distance between levels twice that of the eight-level slicer.

To this end, the slicer predictor 75 predicts the value stored in the register m1 of the trellis encoder as shown in FIG. 3 from the output data of the adder 74-2, and thus the first to third slicers of the channel equalizer 74. One of (74-3 to 74-5) is selected.

That is, register m1 of trellis encoder 32 is determined by Y ₁ and register m0. In this case, a state machine having the register m0m1 as a state value may be represented by a trellis diagram as shown in FIG. 10.

Here, for each transition, states S1 = (00), S2 = (01), S3 = (10), and S4 = (11) occur in each section with respect to the input signal. Meet.

And, the relationship where two passes meet in each state is equally established in each section. For example, in the S1 state of the k + 1 section, the path of the previous section, that is, the S1 state and the S3 state of the k section, meets the S1 state and the S3 state path in the S2 state, and the S2 state and the S4 state in the S3 state. Paths meet, and in the S4 state, the paths of the S2 state and the S4 state meet.

At this time, each state may be divided into (S1, S3) and (S2, S4) according to the value of the register m1 of the trellis encoder.

Therefore, predicting the value of the register m1 is equivalent to predicting the most probable state in the trellis diagram as shown in FIG.

At this time, the probability P (Si) that the state value of the trellis encoder at Si is Si is inversely proportional to the cumulative metric Mi of Si as shown in Equation 1 below. Proportional to In other words, the smaller the cumulative metric Mi, the greater the probability.

The cumulative metric Mi up to an arbitrary time k is as shown in Equation 2 below.

In Equation 2, yj is a received 8VSB signal value, and xj is an 8VSB signal level value assigned to a branch connecting states in the state diagram of FIG. 10. At this time, the 8VSB signal level values assigned to the branches connecting the states are represented by A, B, C, and D in FIG. 10, where A = {-7, +1}, B = {-3, +5}, C = {-5, +3} and D = {-1, +7} are assigned.

Here, in order to calculate the cumulative metric Mi of each state, first, it is necessary to know the state values of two passes meeting each state.

To do this, calculate the difference between the received 8VSB signal value and the 8VSB signal level value assigned to the branch, add the calculated value and the accumulated previous state value at each transition to obtain the current state value, and pass each pass for each state. The state value of is compared and the smallest state value, that is, the minimum value is determined as the cumulative metric value Mi of the state. Therefore, in the trellis diagram in which four states exist as shown in FIG. 10, cumulative metric values M1, M2, M3, and M4 of each state are obtained for the received signal. If the minimum value of M1 and M3 is set to M (0) and the minimum value of M2 and M4 is set to M (1), the value of the register m1 can be predicted as 0 when M (0) < M (1).

That is, the probability P (m1 = 0) where the value of the register m1 is 0 is when the minimum value of the cumulative metric value is detected in the state S1 or the state S3, and the probability P (m1 = 1) where the value of the register m1 is 1 is the state The minimum value is detected in S2 or state S4.

Therefore, if P (m1 = 0) > P (m1 = 1), that is, M (0) < M (1), the value of the register m1 is predicted as 0, and vice versa, 1 is predicted.

At this time, there may be an error in the prediction, and if the prediction for the signal level set is not correct, the error of the determination value becomes larger.

In other words, when the value of the register m1 is 0, the prediction is 1 when P (m1 = 0) < P (m1 = 1). Probably this can be expressed as Equation 3 below.

In Equation 3, M (0) is a minimum cumulative metric among states S1 and S3, and M (1) is a minimum cumulative metric among states S2 and S4. And? = M (1) -M (0). Accordingly, it can be seen that in Equation 3, the larger the value of Δ, that is, the larger the difference between M (1) and M (0), the smaller the probability of prediction error. This means that the larger the value Δ, the more accurate the prediction. The smaller value of Δ is a case where the values of M (1) and M (0) are similar, which increases the probability that the prediction is wrong.

Therefore, using the four-level slicer 74-3 or 74-4 only when the reliability of the predicted value is high, and using the original eight-level slicer 74-5 when the reliability is low minimizes the determination error of the slicer. can do.

To this end, if M (0) < M (1) and Δ = M (1) -M (0) > Threshold, the slice predictor 75 uses the mux 74-6 to determine the ( select a first slicer 74-3 having the same signal level set {-7, -3, + 1, + 5} as a), where M (0) > M (1) and Δ = M (1) If -M (0)> threshold, the second slicer 74-4 having the signal level set {-5, -1, +3, +7} as shown in FIG. 9B is selected. In other cases, that is, when the absolute value of Δ is smaller than the threshold value, the signal level set {-7, -5, -3, -1, + 1, + 3, + 5, + 7 as shown in FIG. } Selects a third slicer 74-5 having " Here, the threshold is a value that determines how certain the predicted value of m1 may vary by the designer.

The data determined by the slicer selected through the mux 74-6 is added to the output of the feed forward filter 74-1 by the adder 74-2 through the feed back filter 74-7.

In this case, the slicer predictor 75 operates by deinterleaving 12 slicer predictors as shown in FIG. 11.

As described above, according to the reception apparatus of the digital TV according to the present invention, after predicting the register value in the trellis encoder on the transmitting side, if the reliability of the predicted value is high, a four-level slicer is used for channel equalization, If the reliability is low, the 8-level slicer minimizes the decision error of the slicer and prevents signal-to-noise ratio degradation due to noise amplification of the channel equalizer's feedback filter even in severe ghost channels, thereby improving the performance of the channel equalizer. It is effective to let.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (8)

Claims [1] A digital TV receiving apparatus for receiving trellis-coded data and performing channel equalization after receiving data transmitted by an eight residual sideband (VSB) modulation scheme. A feed forward filter for removing near ghosts included in the transmitted signal; A feed bag filter to remove distant ghosts; An adder for adding the output of the feed forward filter and the output of a feed back filter; A slicing unit including a plurality of slicers having a different number of signal levels, which determines an output of the adder as a signal level closest to the distance and outputs the determined signal level value to the feedback filter; And Receiving a digital TV comprises a channel equalizer comprising a slicer predictor for predicting trellis-coded data values of the transmitter from the output of the adder and selecting one of the plurality of slicers according to the prediction result Device. The method of claim 1, wherein the slicing unit It has a signal set of four levels divided according to the trellis-coded bit value of the transmitting side, and determines the output of the adder as the signal level closest to the distance and selects the determined signal level value when selected by the slice predictor. First and second slicers output to the feedback filter; A third slicer having an eight-level signal set and determining the output of the adder as the signal level closest to the distance and outputting the determined signal level value to the feedback filter when selected by the slice predictor. A digital TV receiver. 3. The slicer predictor of claim 2, wherein After predicting the trellis coded bit value of the transmitting side, if the reliability of the prediction value is high, the first or second slicer is selected, and if the reliability of the prediction value is low, the third slicer is selected. Receiving device. 4. The slicer predictor of claim 3, wherein If the trellis coded bit value of the transmitting side is predicted to be zero and the reliability of the predicted value is high, the first slicer having the {-7, -3, + 1, + 5} signal level set is selected, and the bit value is And a second slicer having a {-5, -1, + 3, + 7} signal level set if it is predicted to be 1 and the reliability of the predicted value is high. 3. The slicer predictor of claim 2, wherein A register m0m1 of the trellis encoder on the transmitting side is set as a state value, and the trellis-coded bit value on the transmitting side is predicted by a state value having a minimum cumulative metric value at any time. Digital TV receiver. The method of claim 5, A cumulative metric Mi up to a predetermined time k is obtained by applying the following equation. Where yj is a received 8VSB signal value and xj is an 8VSB signal level value assigned to the branch connecting the states. 6. The slicer predictor of claim 5, wherein If the difference between the minimum value M (0) of M1 and M3 and the minimum value M (1) of M2 and M4 among the cumulative metric values M1, M2, M3 and M4 of each state at any time is greater than or equal to the preset threshold, the predicted reliability of the value The receiving device of the digital TV, characterized in that it is determined that is high. A demodulator for trellis coding to receive data transmitted in an eight residual sideband (VSB) modulation scheme, convert the data to a baseband, and then remove interference from other broadcasting schemes; After predicting the trellis-coded bit value of the transmitter from the output of the demodulator, 4-level slicing is performed if the reliability of the predicted value is high, and 8-level slicing is performed if the reliability of the predicted value is low, thereby generating data during transmission. A channel equalizer for compensating for channel distortion of the channel; A trellis decoder for performing Viterbi decoding after restoring the phase of the channel equalized data; And And an error correction unit configured to perform error correction after deinterleaving the trellis decoded data.