KR20010011314A - an node synshronization unit of ADSL system - Google Patents

Abstract

PURPOSE: A node synchronization unit of an asymmetrical digital subscriber line(ADSL) is provided to supply stable clocks according to operation modes divided into an internal operation mode and an external operation mode even when an error is generated in an external clock. CONSTITUTION: A divider/failure detector(302) inputs a reference clock from a network to detect a failure, and generates a predetermined comparison reference clock. A reference clock selector(304) selects the reference clock according to a failure condition. A digital phase locked loop(PLL)(306) compares the selected reference clock with a clock generated from a voltage controlled crystal oscillator(VCXO)(308), and generates a control signal. If a failure is generated in an external reference clock, the digital PLL(306) generates the control signal as having information of a previous reference clock. The VCXO(308) generates a predetermined clock according to the control signal. A controller(310) controls the reference clock selector(304) and the digital PLL(306), according to a clock state and an operation mode. A divider(312) divides clocks generated from the VCXO(308), and supplies clocks for being supplied to an exterior.

Description

Node Synchronization Unit of Asymmetric Digital Subscriber Network System

The present invention relates to an asymmetric digital subscriber network system (ADSL), and more particularly, to a node synshronization unit for synchronizing a clock of a distributed ADSL system to a network.

In recent years, new communication services such as video-on-demand (VOD), home shopping, distance education, and high-speed web have emerged, and technology for connecting digital subscribers to the network at high speed is required. In other words, in the video business commonly referred to as VOD service, a subscriber network for connecting high speed video signals from the VOD server to the subscriber set-top box (STB) is required. When using an optical cable, broadband signals can be transmitted. However, ADSL technology using existing telephone lines has been widely studied because of the enormous cost added to construct a new optical line.

Asymmetrical Digital Subscriber Line (ADSL) system focuses on the asymmetrical traffic between network and subscriber, and the downlink channel transmitted from network to subscriber is allocated wide band for high speed transmission. It is a technology that efficiently uses the capacity of transmission line by allocating narrow bandwidth to the uplink channel.

When implementing such an asymmetric digital subscriber network system, a node synchronization device for synchronizing the operation clock of the distributed ADSL system to the network is required.

Accordingly, an object of the present invention is to provide a node synchronization device in an asymmetric digital subscriber network system in order to meet the above needs.

In order to achieve the above object, the apparatus of the present invention is connected to a subscriber through a telephone line to transmit the data signal to the ATM network, the voice signal to the public telephone network in an asymmetric digital subscriber network system, network or A division and failure detection unit which receives a reference clock from the standard synchronization device to detect a failure and generates a predetermined comparison reference clock; A reference clock selection unit for selecting a reference clock according to a fault condition; A digital PLL which generates a control signal by comparing the clock generated by the selected reference clock with a voltage controlled oscillator (VCXO), and generates a control signal with information of a reference clock that has been previously present when a failure occurs in the external reference clock; The voltage controlled oscillator generating a predetermined clock in accordance with a control signal of the digital PLL; A controller controlling the reference clock selector and the digital PLL according to a clock state and an operation mode; And a divider for dividing a clock oscillated by the voltage controlled oscillator to provide clocks to be supplied to the outside.

1 is a block diagram illustrating an exemplary ADSL system to which the present invention may be applied;

2 is a detailed block diagram of the ATM-ADSL multiplexer shown in FIG. 1;

3 is a block diagram showing a node synchronization device according to the present invention;

4 is a detailed configuration diagram of the digital PLL shown in FIG. 3.

* Explanation of symbols for main parts of the drawings

102: information provider (ISP) 104: ATM network

110: telephone station device 111: ATM-ADSL multiplexer

113a-113n: ATU-C 115a-115n, 121a-121n: Splitter

120: indoor system 123a ~ 123n: ATU-R

125a-125n: PC 106: Public Telephone Network

202: Selbus 206: control management unit

208: multiplexing unit 210: node synchronization unit

302: dispense and fault detection unit 304: reference clock selector

306: digital PLL 308: voltage controlled oscillator

310: control unit 312: dispensing unit

314: line driver 402: digital phase comparator

404: microprocessor 406: digital-to-analog converter

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of a typical asymmetric digital subscriber network system to which the present invention can be applied. The system includes a telephone station system 110 installed in a telephone company CO and an indoor system 120 installed in a subscriber home. do. And the telephone station system 110 is composed of an ATM-ADSL multiplexer 111, a telephone station ADSL transceiver (ATU-C: 113a ~ 113n), splitters (115a ~ 115n), ATM-ADSL multiplexer 111 is The voice signal, which is connected to the ATM network 104 in the STM-1 manner and separated from the splitters 115a to 115n, is transmitted to the public telephone network (PSTN) 106. The indoor system 120 is composed of splitters 121a to 121n, an ADSL transceiver (ATU-R: 123a to 123n), a personal computer (PC: 125a to 125n), and a general telephone (POTS) through a single telephone line. ) Can be connected to the public telephone network 106, and the computer (PC) can be simultaneously connected to the data network.

The ADSL system is a device for providing a high speed digital transmission function using a two-wire subscriber line installed between a subscriber and a telephone company. However, since the telephone subscriber line used is operated for the Plain Old Telephone Service (POTS), the ADSL transmission signal should be divided in the frequency band so as not to affect the telephony signal at all. That is, since the voice area used in the existing telephone is 4KHz or less, after allocating a high frequency band as a band for data communication, the voice signal and the data signal do not overlap each other by using a modulation technique of DMT or CAP.

In Fig. 1, ADSL Transceiver Unit-Central office end: 113a-113n (ATU-C) is an ADSL transceiver at a telephone station, and ADSL Transceiver Unit-Remote terminal end: 123a-123n (ATU-R) is an ADSL at a subscriber side. It is a transceiver. The splitters 115a to 115n and 121a to 121n are high-pass filters for blocking a voice (POTS) signal and separate the voice signal and the data signal. In addition, the data signal has a full-duplex communication function, but has an asymmetric structure in which the amount of communication in the downward direction is larger than that in the upper direction. For example, the transmission rate of the uplink channel from the subscriber to the network is 32K to 800 Kbps, while the transmission rate of the downlink channel transmitted from the network to the subscriber is 32K to 9 Mbps.

On the other hand, ADSL signal modulation includes CAP (Carrierless AM / PM) and DMT (Discrete Multi Tone). The frequency is arranged at regular intervals of W Hz, each carrier acts as an independent subchannel, and the modulation and detection of the QAM modulation method is performed by data allocated to each carrier. First, b-bit data input during T time is distributed to N / 2 subchannels. At this time, the amount of data allocated to each subchannel is not uniform, and the amount is determined according to the transmission quality index of the corresponding channel. Data allocated to each subchannel is mapped to one QAM symbol value having a complex value according to the QAM modulation scheme. If the QAM symbol value in the k-th subchannel is Xk, each symbol value represents the size and phase of the carrier as a pager of the corresponding QAM transmission signal, which is a frequency component of the ADSL transmission signal at the carrier frequency position. do. A symbol block composed of QAM symbols from each subchannel is transformed into a sample sequence in the time domain through an inverse transform (IFFT) in advance, and this pulse sequence is sequentially transmitted to a transmission path through a transmission filter. The power spectrum of the transmitted signal is uniformly distributed in the designated frequency band by making the average transmission power of the active subchannels all have the same value. This is accomplished by making the square mean values of all Xk equal when placing signal points in QAM modulation. The reception process is the reverse process of the transmission process. The received signals sampled (yi, i = 0 to N) during T time are obtained through the Fourier transform (FFT) to obtain {Yk, k = 0 to N / 2}. This output indicates the representation of the received signal in the frequency domain, which is a block of received QAM symbol values. By determining the corresponding symbol value for each subchannel, the original b-bit data content can be obtained. The entire signal transmitted during T time is called a DMT symbol by dividing it from the QAM symbols of each subchannel. Interference between DMT symbols occurs due to signal distortion of the transmission path during transmission. In order to solve this problem, a real system uses a method of inserting a prefix composed of P QAM symbols in front of the DMT symbol.

FIG. 2 is a detailed block diagram of the ATM-ADSL multiplexer illustrated in FIG. 1, wherein the ATM-ADSL multiplexer 111 is a control management unit (CMU) 206 connected through a cell bus 202 and a multiplexing unit (AMU). (208), which consists of a number of ADSL transceivers (ATU-C: 113a-113n) and a node synchronization unit (NSU: 210) for supplying clocks to each board.

Referring to FIG. 2, the control management unit (CMU) 206 receives an STM-1 signal from a control function including a general management function of a system and receives an STM-1 signal from an ATM switching network, and extracts an ATM cell to a corresponding unit. It performs the sending function and its reverse function. It also provides an operational interface for SNMP communication. The node synchronization unit (NSU) 210 supplies a desired clock in accordance with an input reference clock. The reference input clock is a 19.44 MHz clock extracted from a 2.048 MHz and an STM-1 line input from a DOTS. Telephone station ADSL transceiver (ATU-C: 113a ~ 113n) receives ATM cell from multiplexing unit (AMU: 208) and performs ADSL modem function and its reverse function, and spirit (115a ~ 115n) data signal and voice signal The data signals are transmitted to the ATU-Cs 113a to 113n and the voice signals to the public telephone network PSTN 106, respectively. That is, the splitters 115a to 115n separate or mix the voice band and the ADSL band to transmit data signals and voice signals using one telephone line. At this time, the voice band is 0.2KHz ~ 3.4KHz, ADSL band is 30KHz ~ 1100KHz in the DMT method, 30KHz ~ 1500KHz in the CAP method.

The multiplexing unit (AMU) 208 transmits a cell used in its own self to a subscriber side within a self for a cell transmitted from an ATM network or an upper self, and transmits a cell to a lower self to a lower self. On the contrary, the cell input from the lower shelf and the cell to be transmitted from the inside to the upper are muxed and transmitted to the upper shelf or ATM network. For this purpose, the multiplexing unit 208 receives an STM-1 (155.52 Mbps) frame input through an optical path, converts it into an electrical signal, processes the control signals in the STM-1 frame, extracts an ATM cell, and extracts another unit. To pass.

3 is a block diagram of a node synchronization device according to the present invention, wherein the node synchronization device includes a frequency division and error detection unit 302, a reference clock selection unit 304, a digital PLL 306, a voltage controlled oscillator (VCXO) 308, The control unit 310, the dispensing unit 312, and a line driver 314. At this time, the digital PLL 306 is composed of a digital phase comparator 402, a microprocessor 404, and a digital-to-analog (D / A) converter 406, as shown in FIG.

The node synchronizer of the present invention supplies a desired clock in accordance with an input reference clock, and the reference input clock is a 19.44 MHz clock extracted from a 2.048 MHz and an STM-1 line input from a DOTS. The node synchronous device operates in external synchronous mode and internal synchronous mode according to the state of the input clock, and the 2.048 MHz clock input to the standard synchronization device (DOTS) is used as the primary reference clock and the 19.44 MHz received clock is used as the secondary reference Use it as a clock.

The external synchronization mode refers to a case in which one of the primary reference clock and the secondary reference clock is supplied without a clock failure, and a clock supplied to the outside is synchronized with the reference clock without a failure. First, the primary reference clock is synchronized. If a failure occurs in the primary reference clock, the reference is immediately set to the secondary reference clock. If the primary reference clock is normally input while holding the reference as the secondary reference clock, the clock reference is changed to the primary reference clock immediately. However, if both primary and secondary reference clocks fail, they immediately switch to internal synchronous mode. This is also known as holdover mode, which must be maintained for 24 hours. The fault condition of the external reference clock is defined as the normal clock is not input for 1x10E-3 seconds.

In internal synchronous mode, when the external reference clock fails and there is no reference clock anymore, the internal clock is supplied with information about the internal reference clock within the frequency range of ± 1x10E-8. The internal synchronous mode should be maintained for more than 24 hours, and immediately return to the highest reference clock when the failure of the external reference clock is cleared in this mode.

Referring to FIG. 3, the division and fault detection unit 302 detects a fault with respect to an external clock source and transmits it to the control unit 310, and divides the input reference clock into an internal reference clock of 8 KHz. Clock failure is when normal clock is not supplied for 1x10E-3 hours. 2.048MHz input from the standard synchronization unit (TOTS) toggles every 128 clocks (8 minutes) to divide and generate an 8KHz reference clock for internal use, and a clock input of 19.44 MHz toggles every 2430 clocks. And divide it to generate an 8KHz reference clock to use as the internal reference clock.

The reference clock selector 304 selects a reference clock without an error among the reference clock divided at 2.048 MHz and the 8KHz reference clock divided at 19.44 MHz according to the failure condition of the reference clock detected by the division and fault detection unit 302. Transmit to digital PLL 406.

The digital PLL 306 is composed of a digital phase comparator 402, a microprocessor 404, and a digital-to-analog converter 406, as shown in FIG. 4, which uses a low pass filter (LPF) in an analog PLL. As a PLL controlled by the processor 404, a digital value for controlling the voltage controlled oscillator (VCXO) 308 is generated. At this time, when the reference clock is not supplied due to the failure of the external clock, the microprocessor 404 internally stores the information of the reference clock in the entire state, and based on the information, the clock error is ± 1x10E-8 for 24 hours. The control value of the voltage controlled oscillator (VCXO) 308 is generated to be able to supply the same.

The controller 310 selects a reference clock according to a fault condition received from the division and fault detection unit 302 and a condition of selecting an internal reference clock, and based on the result of the failure of the external reference clock, a digital PLL ( 306). Mark the outcome of the disability as visible or audible.

The divider 312 divides the clock into 38.88 MHz, which is output in synchronization with the selected reference clock, to various desired external clocks, and the line driver 314 transfers the generated clock to a unit requiring an external clock. . At this time, the line driver 314 is implemented as a buffer or a differential amplifier to match the delay time between the fan out and the board.

As described above, the node synchronization device according to the present invention provides a stable clock according to an operation mode divided into an internal operation mode and an external operation mode, and in particular, even if a failure occurs in an external clock using a digital PLL, This has the effect of providing a clock to the system.

Claims (2)

In the asymmetric digital subscriber network system is connected to the subscriber and the telephone line to transmit the data signal to the ATM network, the voice signal to the public telephone network, A frequency division and failure detection unit which receives a reference clock from a network or a standard synchronization device, detects a failure, and generates a predetermined comparison reference clock; A reference clock selection unit for selecting a reference clock according to a fault condition; A digital PLL which generates a control signal by comparing the clock generated by the selected reference clock with a voltage controlled oscillator (VCXO), and generates a control signal with information of a reference clock that has been previously present when a failure occurs in the external reference clock; The voltage controlled oscillator generating a predetermined clock in accordance with a control signal of the digital PLL; A controller controlling the reference clock selector and the digital PLL according to a clock state and an operation mode; And And a divider for dividing a clock generated by the voltage controlled oscillator and providing clocks to be supplied to the outside. The digital PLL of claim 1, wherein the digital PLL comprises: a digital phase comparator for comparing a phase of a reference clock and a generated clock; A microprocessor that receives the output of the digital phase comparator and outputs predetermined control data and outputs previously stored control data in an internal operation mode; And a digital-to-analog converter for converting control data of the microprocessor into an analog signal.