KR20010011162A - Offset compensation circuit of semiconductor device - Google Patents

Abstract

PURPOSE: An offset compensation circuit for semiconductor device is provided to compensate DC offset voltage additionally generated by changes in external environment. CONSTITUTION: An offset compensation circuit comprises a switch circuit(340), a comparator circuit(310), a reset signal generating circuit(320), a combining circuit(330), a counter(350), a digital-analog converter(360) and a voltage-current converting unit(370). The switch circuit transmits the first reference voltage(Vref1) output from an external source to the first and second input terminals of the filter in response to a switch control signal(SCON) during an operation of offset compensation. The comparator circuit outputs the first and second comparison signals(COM1,COM2) as a result of comparison between the second and third reference voltages(Vref2,Vref3) and the first and second amplification signals(VOUTP,VOUTN) during normal operation, and outputs the third and fourth comparison signals(COM3,COM4) as a result of comparison between the first and second amplification signals(VOUTP,VOUTN) in response to the second and third combination signals(COMB2,COMB3) during operation of offset compensation. The reset signal generating circuit generates a reset signal indicative of completion of the offset compensation in response to the third and fourth comparison signals.

Description

OFFSET COMPENSATION CIRCUIT OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an offset compensation circuit for compensating DC offset voltage of a GM-C filter.

A gm-c filter with a differential output is mainly used to filter the signals needed within an integrated circuit (IC). However, in the GM-C filter, a DC current (direct current offset) is generated between a positive output and a negative output by a miss match of each element constituting the filter. The amount can range from a few mV (milli voltage) to tens of mV. Since this soon deteriorates the characteristics of the integrated circuit (IC), the DC offset must always be compensated.

The simplest method of compensating for DC offset is to connect a capacitor to the circuit of the next stage that accepts the output of the filter, and coupling this capacitor to the output of the filter compensates for the DC offset. . However, when the frequency band of the input signal is a low frequency band of several kilohertz (kHz), the coupling capacitor has a capacitor capacity too large to be mounted therein, so that the capacitor is connected to the outside of the integrated circuit (IC). There is a problem that must be done.

Another DC offset compensation method uses a comparator to compare the voltage level of the filter's output signal with a common voltage level to make it a digital signal, and then the logic high of the digital signal. And a logic low is averaged to calculate the average value, and a DC offset is compensated based on the average. However, in order to implement this method in an actual circuit, the system becomes complicated.

Accordingly, it is an object of the present invention to provide an offset compensation circuit of a semiconductor device which compensates during the normal operation of a circuit including a filter additionally a DC offset voltage generated by a change in external environment.

1 is a block diagram of an offset compensation circuit according to the present invention;

2A and 2B are operational waveform diagrams illustrating an operation of the offset compensation circuit of FIG. 1.

* Explanation of symbols on the main parts of the drawings

100: GM-C filter 200: amplifier

310: comparison circuit 320: reset circuit

330: combination circuit 340: switch circuit

350: counter 360: digital-to-analog converter

370: GM cell

(Configuration)

According to one aspect of the present invention for achieving the above object, the semiconductor device according to the present invention includes a filter, an amplifier and an offset compensation means. The filter receives a first input signal and a second input signal complementary to the first input signal through first and second input terminals, and first and second outputs filtering the first and second input signals. Output signals. The amplifier outputs first and second amplified signals that amplify the first and second output signals from the filter. The offset compensating means compares the first and second amplified signals with external second and third reference voltages during an offset compensation operation to compensate for a DC offset voltage included in the first and second amplified signals. Output the first and second offset compensation currents to the filter and after the DC offset voltage included in the first and second amplified signals is compensated, it is disabled. Here, the offset compensation means includes a switch circuit, a comparison circuit, a reset signal generation circuit, a combination circuit, a counter, a digital-analog converter and a voltage-current conversion means. The switch circuit delivers a first reference voltage from the outside to the first and second input terminals of the filter in response to a switch control signal during the offset compensation operation. The comparison circuit outputs first and second comparison signals comparing the second and third reference voltages with the first and second amplified signals during normal operation, and the first and second combinations during the offset compensation operation. And outputs third and fourth comparison signals comparing the first and second amplified signals in response to the signals. The reset signal generation circuit generates a reset signal informing the end of the offset compensation operation in response to the third and fourth comparison signals. The combination circuit stores the first and second comparison signals and combines the first and second comparison signals in response to a clock signal from an external device, the counter control signal and the first and second comparison signals. Output the combined signals. The counter generates a plurality of bits of counting signals corresponding to the first comparison signal in response to the first comparison signal and the counter control signal. The digital-analog converter outputs first and second offset compensation voltages that convert the counting signals into analog voltages. The voltage-current conversion means converts the first and second offset compensation voltages into first and second offset compensation currents. The combination circuit also includes an OR gate, first and second flip flops, first and second end gates, and a NAND gate. The OR gate outputs a first combined signal combining the first and second comparison signals. The first flip flop latches and outputs the first comparison signal. The second flip flop latches the first combined signal and outputs the first combined signal as the switch control signal. The first AND gate outputs the second combined signal obtained by combining the first comparison signal and the first combined signal. The second AND gate outputs the third combined signal obtained by combining the inverted signal of the first comparison signal and the first combined signal. The NAND gate outputs the counter control signal in which the clock signal and the first combined signal are combined.

(Action)

With such a device, when the DC offset voltage included in the output signals from the filter during the normal operation of the filter is above a predetermined voltage level, the DC offset voltage is compensated and automatically disabled after the DC offset voltage is compensated. This compensates for the DC offset voltage of the filter that is additionally generated by changes in the external environment.

(Example)

Hereinafter, reference will be described in detail with reference to FIGS. 1 to 2b according to a preferred embodiment of the present invention.

Referring to FIG. 1, a semiconductor device according to the present invention includes a GM-C filter 100, an amplifier 200, and an offset compensation circuit 300. The offset compensation circuit 300 includes a comparison circuit 310, a reset signal generation circuit 320, a combination circuit 330, a switch circuit 340, a counter 350, a digital analog converter 360, and a GM cell 370. ). The offset compensation circuit 300 detects DC offset voltages included in the first and second amplified signals VOUTP and VOUTN output from the amplifier 200, so that the DC offset voltage is a predetermined voltage level. When exceeding, the first and second offset compensation voltages VOS1 and VOS2 are provided to the filter 100 to compensate the DC offset voltage. When the DC offset voltages included in the first and second amplified signals VOUTP and VOUTN from the amplifier 200 are compensated, the offset compensation circuit 300 is disabled. As such, when the DC offset voltage included in the output currents IOUTP and IOUTN from the filter 100 is equal to or greater than a predetermined voltage level, the offset compensation circuit compensates for the DC offset voltage and after the DC offset voltage is compensated. By automatically disabling, the DC offset voltage of the filter, additionally generated by changes in the external environment, is compensated.

Referring to FIG. 1, a semiconductor device according to an exemplary embodiment of the present invention includes a GM-C filter 100, an amplifier 200, and an offset compensation circuit 300. The GM-C filter 100 filters the first and second input signals VINP and VINN from the outside during normal operation and adjusts gain to adjust the first and second output currents IOUTP, Output IOUTN). The amplifier 200 receives the first and second amplified signals VOUTP and VOUTN that amplify voltage levels of the first and second output currents IOUTP and IOUTN from the GM-C filter 100. Output

The offset compensation circuit 300 includes a comparison circuit 310, a reset signal generation circuit 320, a combination circuit 330, a switch circuit 340, a counter 350, a digital-to-analog converter 360, and a GM cell ( 370). The comparison circuit 310 includes first, second, third and fourth comparators 311, 312, 313, and 314, wherein the second and third reference voltages Vref2, Outputs first and second comparison signals COM1 and COM2 comparing Vref3) and the first and second amplified signals VOUTP and VOUTN, and second and third combination signals COMB2 and COMB3. In response, third and fourth comparison signals COM3 and COM4 comparing the first and second amplified signals VOUTP and VOUTN are output.

The reset signal generation circuit 320 outputs a reset signal RST indicating the end of the offset compensation operation in response to the third and fourth comparison signals COM3 and COM4. The combination circuit 330 includes an OR gate 331, flip flops 332 and 333, AND gates 334 and 335, and a NAND gate 336, and counters the first comparison signal COM1. And a first combined signal COMB1 combining the first and second comparison signals COM1 and COM2 as a switch control signal SCON to the switch circuit 340, and transmitting the first combined signal COMB1 to the switch circuit 340. The first comparison signal COM1, the inversion signal COM1B of the first comparison signal COM1, and the second and third combination signals COMB2 and COMB3 combining the first combination signal COMB1, respectively, are compared. And a fourth combined signal COMB4, which combines the clock signal CLK and the first combined signal COMB1 from the outside, to the counter 340 as a counter control signal.

The switch circuit 340 includes first and second switches 341 and 342, and may be externally controlled by control of the switch control signal SCON from the combination circuit 330 during an offset compensation operation. One reference voltage Vref1 is transferred to the GM-C filter 100. The counter 350 is a multi-bit counting signal counting the first comparison signal COM1 from the combination circuit 330 by the control of the fourth combination signal COMB4 from the combination circuit 330. COUNT0, COUNT1, ..., COUNTn-1, COUNTn, where n is a positive integer. The digital-to-analog converter 360 converts the counting signals COUNT0, COUNT1, ..., COUNTn-1, COUNTn from the counter 350 into an analog signal, and first and second offset compensation voltages. Outputs (VOC1, VOC2). The GM cell 370 converts the first and second offset compensation voltages VOC1 and VOC2 from the digital-to-analog converter 360 into a current to the first and second offset compensation currents IOC1 and IOC2. Is provided to the corresponding output terminals of the GM-C filter 100.

Hereinafter, the operation of the offset compensation circuit of the semiconductor device according to the present invention will be described with reference to FIGS. 1 to 2B.

Referring back to FIGS. 1 and 2B, in the offset compensation circuit of the semiconductor device according to the present invention, the DC offset voltage included in the output currents IOUTP and IOUTN from the GM-C filter 100 may be predetermined. When above the level, the DC offset voltage is compensated and automatically disabled when the DC offset voltage is compensated. The GM-C filter 100 adjusts gains of the first and second input signals VINP and VINN having mutually complementary voltage levels from the outside during normal operation, and controls the first and second input signals. Outputting the first and second output currents IOUTP and IOUTN, which are filtered through the first and second VINPs and VINNs. The amplifier 200 outputs first and second amplified signals VOUTP and VOUTN that amplify the first and second output currents IOUTP and IOUTN from the GM-C filter 100.

However, in the GM-C filter 100, a DC offset voltage is generated between the first and second output currents IOUTP and IOUTN due to a mismatch between the elements configured in the circuit. This DC offset voltage must be compensated because it causes a malfunction of the GM-C filter 100 or interferes with the normal operation of the circuit of the next stage. For example, the DC offset voltage is included in the first and second output currents IOUTP and IOUTN from the GM-C filter 100, and the positive DC offset voltage is included in the first output current IOUTP and Assume that a negative DC offset voltage is included in the second output current IOUTN. The first and second output currents IOUTP and IOUTN from the GM-C filter 100 are amplified by the amplifier 200 and output to the first and second output currents VOUTP and VOUTN. At this time, the DC offset voltage included in the first and second output currents VOUTP and VOUTN is also amplified. At this time, the voltage level of the first amplified signal VOUTP amplified by the amplifier 200 is higher than the second reference voltage Vref2 and the voltage level of the second amplified signal VOUTN is the third reference voltage Vref3. If lower, the offset compensation operation of the offset compensation circuit 300 is started.

When the voltage level of the first amplified signal VOUTP is higher than the second reference voltage Vref2 and the voltage level of the second amplified signal VOUTN is lower than the third reference voltage Vref3, the comparison circuit 310 may be used. The first and second comparators 311 and 312 of FIG. 2A output first and second comparison signals COM1 and COM2 having a logic high level as shown in FIG. 2A. The or gate 331 of the combination circuit 320 outputs a first combination signal COMB1 having a logic high level combining the first and second comparison signals COM1 and COM2. The flip flops 332 and 332 latch the first comparison signal COM1 and the first combination signal COMB1, respectively. In this case, each of the switches 341 and 342 of the switch circuit 340 receives the first reference voltage Vref1 from the outside by controlling the first combination signal COMB1 having a logic high level. Passes to both input terminals of 100.

The first AND gate 334 receives a second combination signal COMB2 having a logic high level by combining the first comparison signal COM1 and the first combination signal COMB1 from the flip flops 332 and 333. Output The second AND gate 335 is the third combination signal COMB3 having a logic low level in which the inversion signal COM1B of the first comparison signal COM1 and the first combination signal COMB1 are combined. ) The NAND gate 336 outputs a fourth combined signal COMB4 in which the first combined signal COMB1 and the external clock signal CLK are combined. The counter 350 is initialized when power is applied, and outputs a center code (for example, 100.000) as a counting signal (COUNT0, COUNT1, ..., COUNTn-1, COUNTn). And the plurality of bit counting signals COUNT0, COUNT1,..., Counting the fourth combined signal COMB4 by the control of the first comparison signal COM1 from the flip-flop 332 of the combining circuit 330. .., COUNTn-1, COUNTn) In this case, when the first comparison signal COM1 is at a logic high level, the counter 350 performs up counting, and when the first comparison signal COM1 is at a logic low level, the counter 350. ) Performs down counting.

The digital-to-analog converter 360 converts the counting signals COUNT0, COUNT1, ..., COUNTn-1, COUNTn from the counter 350 into an analog signal (first and second offset compensation voltages). Outputs VOC1, VOC2). The voltage levels of the first and second offset compensation voltages VOC1 and VOC2 are close to a common voltage level each time the counter 350 performs a counting operation, as shown in FIG. 2A. The GM cell 370 converts the first and second offset compensation voltages VOC1 and VOC2 from the digital-to-analog converter 370 into currents and the first and second offset compensation currents IOC1 and IOC2. ) Are respectively provided to corresponding output terminals of the GM-C filter 100. As a result, the DC offset voltage generated by the GM-C filter 100 is gradually compensated as shown in FIG. 2B.

If the DC offset voltage of the GM-C filter 100 is not compensated until the first and second offset compensation voltages VOC1 and VOC2 match the common voltage VCM level, the second offset The compensation voltage VOC2 level is higher than the first offset compensation voltage VOC1 level. If the offset compensation operation continues as described above and the voltage level of the second output current IOUTN from the GM-C filter 100 becomes higher than the voltage level of the first output current IOUTP, The voltage level of the second amplified signal VOUTN from the amplifier 200 is higher than the voltage level of the first amplified signal VOUTP. At this time, the third comparator 313 of the comparison circuit 310 outputs a third comparison signal COM3 having a logic high level comparing the voltage levels of the first and second amplified signals VOUTP and VOUTN. The fourth comparator 314 outputs a fourth comparison signal COM4 having a logic low level.

In addition, the reset signal generating circuit 320 terminates the offset compensation operation in response to the third and fourth comparison signals COM3 and COM4 from the third and fourth comparators 313 and 314. The alert generates a logic high level reset signal RST. In this case, the first and second comparators 311 and 312 of the comparison circuit 310 output the first and second comparison signals COM1 and COM2 having a logic low level. Flip flops 332 and 333 of the combination circuit 330 latch the first comparison signal COM1 and the first combination signal COMB1 at a logic low level by the control of the reset signal RST, and Output The switches 341 and 342 of the switch circuit 340 are the first reference voltage Vref1 transmitted from the outside to the GM-C filter 100 by the control of the first combination signal COMB1 having a logic low level. To block.

When the supply of the first reference voltage Vref1 to the GM filter 100 is cut off, the GM filter 100 receives the first and second input signals VINP and VINN from the outside. Perform normal gain adjustment and voltage-to-current conversion operations. At this time, the counter 350 is the final combination of the fourth combination signal (COMB4) from the NAND gate 336 of the combination circuit 330 regardless of the voltage level of the clock signal (CLK), so that the final Keep count value. As such, the voltage levels of the first and second offset compensation voltages VOC1, VOC2 from the digital-to-analog converter 360 also maintain final voltage levels. As described above, the offset compensation operation depends on the voltage level of the DC offset voltage and the frequency of the clock signal CLK, but is performed for a short time (eg, about 1 ms; within 1 milli second) so that the GM-C filter ( Does not cause problems for the normal operation of the circuit comprising 100).

As such, when the DC offset voltage included in the output currents IOUTP and IOUTN from the filter 100 is equal to or greater than a predetermined voltage level, the offset compensation circuit 300 compensates for the DC offset voltage and the DC offset voltage. After this is compensated, it is automatically disabled, thereby compensating for the DC offset voltage of the filter which is additionally generated by changes in the external environment.

In the above, although the offset compensation circuit of the semiconductor device according to the present invention is shown in accordance with the above description and drawings, this is merely an example, and various changes and modifications are possible without departing from the spirit of the present invention. .

As described above, when the DC offset voltage included in the output signals from the filter is above a predetermined voltage level, the DC offset voltage is compensated and automatically disabled after the DC offset voltage is compensated, thereby changing the external environment. The DC offset voltage of the filter additionally generated is compensated for.

Claims (2)

A first input signal and a second input signal complementary to the first input signal are received through first and second input terminals, and output first and second output signals filtered through the first and second input signals. A filter; An amplifier for outputting first and second amplified signals that amplify the first and second output signals from the filter; First and second compensation voltages for compensating the DC offset voltage included in the first and second amplified signals by comparing the first and second amplified signals with second and third reference voltages externally during an offset compensation operation; An offset compensating means for outputting second offset compensation currents to the filter and being disabled after the DC offset voltage included in the first and second amplified signals is compensated, The offset compensation means, A switch circuit for transferring a first reference voltage from the outside to the first and second input terminals of the filter in response to the switch control signal; Output first and second comparison signals comparing the second and third reference voltages with the first and second amplified signals during normal operation, and responding to the first and second combination signals during the offset compensation operation; A comparison circuit for outputting third and fourth comparison signals comparing the first and second amplified signals; A reset signal generation circuit for generating a reset signal informing of termination of the offset compensation operation in response to the third and fourth comparison signals; Storing the first and second comparison signals and outputting the switch control signal, the counter control signal and the first and second combination signals combining the first and second comparison signals in response to a clock signal from an external source. Combination circuits, A counter for generating a plurality of bits of counting signals corresponding to the first comparison signal in response to the first comparison signal and the counter control signal; A digital-to-analog converter for outputting first and second offset compensation voltages which convert the counting signals into analog voltages; And voltage-current conversion means for converting the first and second offset compensation voltages into first and second offset compensation currents. The method of claim 1, The combination circuit, An OR gate outputting a first combined signal combining the first and second comparison signals; A first flip flop for latching and outputting the first comparison signal; A second flip flop for latching the first combined signal and outputting the first combined signal as the switch control signal; A first AND gate outputting the second combined signal obtained by combining the first comparison signal and the first combined signal; A second AND gate outputting the third combined signal obtained by combining the inverted signal of the first comparison signal and the first combined signal; And a NAND gate configured to output the counter control signal obtained by combining the clock signal and the first combined signal.