KR20010010475A - Data frame converting circuit from C4 data in AU4 data frame to E4 data - Google Patents

Abstract

PURPOSE: A circuit for converting C4 data of an AU-4 frame into E4 data is provided to minimize size of a jitter generated when the C4 data is converted into the E4 data, so as to prevent a data transmission error and to improve quality of a communication service. CONSTITUTION: A data converter(100) inputs C4 data according to a 19Mbps clock signal, and controls an underflow and an overflow not to be generated, by using a first-in-first-out(FIFO) buffer, then generates data driven by a 17Mbps clock signal to output the data. A data former(200) inputs the data outputted from the data converter(100), and arranges the data with E4 data types according to the 17Mbps clock signal, then outputs arranged E4 data. A phase locked loop(PLL)(300) inputs a signal output from the data converter(100), and compares the signal with a signal outputted from the data former(200), then generates a PLL signal of the E4 data outputted from the data former(200) to output the PLL signal.

Description

Data frame converting circuit from C4 data in AU4 data frame to E4 data}

In the present invention, this 4 (E4, hereinafter referred to as 'E4') data (data) AY 4 (AU4, hereinafter referred to as 'AU4') Seed 4 (C4, 'C4') of the frame (frame) In more detail, in a North American European optical transmission system based on the E4 interface and the AU4 interface as data transmission, the jitter is minimized while minimizing the size of jitter. A circuit for converting E4 data into C4 data.

In general, optical transmission systems used in North America and Europe are used for transmitting data between each exchange and repeater, or for transmitting data from each exchange and repeater to a subscriber network.

The data processed by the transmitter is classified into E4 data and C4 data according to its characteristics. The C4 data has a transmission rate of 155.84 megabits (Mega bps), Mbps, and data of AU4 frame. It is part of the structure.

As shown in FIG. 1, the data structure of the AU4 frame has a V4 including the C4 data D10 and Pass OverHead (POH, hereinafter referred to as 'POH', D20) containing actual information. (VC4, hereinafter referred to as 'VC4') data and a pointer (pointer, POH, D30).

The C4 data is composed of nine subframes, and the structure of each subframe is as shown in FIG. 2, and the portion excluding the POH is one subframe of the C4 data.

That is, in FIG. 2, the portion denoted '96I' is 96 data bits I containing actual information, the portion denoted 'W' is eight information data bits I, and the portion denoted 'Y' is non- Eight fixed stuff bits (R) that are information.

The portion labeled 'X' is composed of one control control bit (C, hereinafter referred to as 'C bit'), five fixed element bits (R), and two overhead bits (O). The part labeled 'Z' consists of six bits of data (I) which are actual information, one selection opportunity bit (S, hereinafter referred to as 'S bit') and one fixed element bit (R). .

As shown in FIG. 2, the C4 data is composed of parts containing E4 data information (I) and other parts necessary for communication, and is transmitted in the form of the C4 data when transmitting between the respective transmitting apparatuses. In the step of transmitting to the subscriber network of the E4 data is converted and transmitted by the data conversion circuit.

On the contrary, when transmitted from each subscriber network to each transmitter and repeater, the data conversion circuit converts E4 data into C4 data and transmits the data.

However, the C4 data is data transmitted at a transmission rate of 155.84 Mbps by a clock of 19 Mbps. As described above, the C4 data includes various non-information parts in addition to pure E4 data information, and only pure E4 data information parts. When calculating the transmission rate of, since there are 20 96 I bits in one subframe, one 'W' of 8 bits, and six I bits in 'Z', it is calculated as in Equation 1 below.

Information data in one subframe = 96 × 20 + 8 + 6 = 1,934

By the way, since one frame of C4 data consists of nine subframes, the information data in one frame becomes 17,406 bits.

Since each bit is transmitted at a rate of 8 Kbps, the transmission rate of one frame is calculated as shown in Equation 2 below, resulting in 139.248 Mbps.

Transmission rate of one frame information data = 17,406 × 8,000 = 139,248,000 bps

As described above, when E4 data is converted to the C4 data format, E4 data is input at a transmission rate of 139.264 Mbps, and C4 data is output at a transmission rate of 139.248 Mbps, so C4 data is higher than E4 data. 16,000bps is lacking.

Unlike the C4 data, the E4 data contains only pure information, and is transmitted at a transmission rate of 139.264 Mbps by a clock of 17 Mbps.

On the other hand, there is an S bit in the portion indicated by the 'Z' in the frame structure of the C4 data, the S bit is an optional bit that may or may not contain information in some cases.

Therefore, 16,000 bits, which is the difference between the E4 data and the C4 data, can be solved by appropriately using the S bits, and C bit data is used for the control.

That is, there are nine S bits in the frame, one for each subframe, of which two S bits contain information and the remaining seven S bits do not contain information. The number of C4 data can be the same.

On the other hand, the frame structure of the E4 data is as shown in Figure 3, the E4 data also includes non-information data including the frame alignment signal in addition to the pure information data, but also in the C4 data frame, Since it is not information data, all data may be processed as data information when converting it into E4 data.

As described above, when converting the C4 data in the AU4 frame into pure E4 data, a first input first out (FIFO) buffer is used, and the C4 data according to a clock of 19 Mbps. The difference between the rate of writing to the buffer and the rate of reading E4 data from the buffer according to a clock of 17 Mbps results in underflow or vice versa. There is a problem such as overflow, a jitter phenomenon, and the like.

If a jitter phenomenon occurs due to the above causes, an error in data transmission may occur, thereby degrading the quality of the overall communication service.

Accordingly, an object of the present invention is to solve the problems of the prior art as described above. In the North American European optical transmission system using the E4 interface and the AU4 interface as the basis for data transmission, the C4 data of the AU4 frame is converted into E4 data. By minimizing the amount of jitter that occurs in the conversion to C, it is possible to provide a circuit for converting C4 data in AU4 frames into E4 data, which can prevent data transmission errors and thereby improve the quality of communication services. have.

1 is a block diagram showing a data structure of an AU4 frame;

FIG. 2 is a block diagram illustrating a subframe structure of one of C4 data in FIG. 1;

3 is a block diagram showing an E4 data frame structure;

4 is a block diagram to which a circuit for converting C4 data of an A4 frame to E4 data according to an embodiment of the present invention is applied;

FIG. 5 is a block diagram to which the data converter of FIG. 4 is applied;

FIG. 6 is a block diagram to which the selection bit processor is applied in FIG. 5;

FIG. 7 is a block diagram to which the data generator of FIG. 5 is applied;

8 is a block diagram to which the parallel signal generator of FIG. 7 is applied;

9 is a block diagram to which the first data parallelization unit is applied in FIG. 8;

FIG. 10 is a block diagram to which a buffer level controller is applied in FIG. 7;

FIG. 11 is a block diagram to which the data forming unit of FIG. 4 is applied;

12 is a block diagram in which the conversion circuit of the present invention is applied to four channels;

13 is a diagram illustrating a concept of a buffer level control operation.

Explanation of symbols on the main parts of the drawings

100: data conversion unit 200: data forming unit

300: phase synchronization control unit 110: frame counter

120: selection bit processing unit 130: data extraction unit

140: data generation unit 121: control bit detection unit

122: control bit setting unit 123: control bit calculating unit

141: selection bit control unit 142: buffer level control unit

143: address assigning unit 144: parallel signal generating unit

145: data output unit 144_1 to 144_256: data parallelization unit

144_1A: comparison unit 144_1B: encoder

144_1C: Retiming part 142_1: First type driving part

142_2: Second type drive unit 142_3: Shape selector

142_4: Level control selector 210: Drive setting unit

220: data output unit 230: synchronization unit

The configuration of the present invention for achieving the above object is made as follows.

In the circuit for converting the seed 4 data of the A4 frame of the optical transmission system to this 4 data,

Data conversion means for receiving C4 data according to a 19 Mbps clock signal to control underflow and overflow using a first-in first-out buffer, and generating and outputting data driven according to a 17 Mbps clock signal;

Data forming means for receiving the data output from the data converting means and arranging the data in the form of E4 data according to a 17 Mbps clock signal;

A phase synchronous control means for receiving a signal output from the data converting means, comparing the signal output from the data forming means, and generating and outputting a phase synchronous control signal of the 4 data output from the data forming means; Characterized in that made.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

As shown in Figs. 4 to 12, the circuit for converting the seed 4 data of the A4 frame into the 4 data according to the embodiment of the present invention is configured as follows.

In the circuit for converting the seed 4 data of the A4 frame of the optical transmission system to this 4 data,

Data conversion unit 100 receives C4 data according to a 19 Mbps clock signal to control underflow and overflow using a first-in first-out buffer, and generates and outputs data driven according to a 17 Mbps clock signal. ;

A data forming unit 200 which receives the data output from the data converting unit 100 and arranges and outputs the data in the form of E4 data according to a clock signal of 17 Mbps;

Receives the signal output from the data converter 100, compares the signal output from the data forming unit 200, generates a phase synchronization control signal of the E4 data output from the data forming unit 200 Characterized in that it comprises a phase synchronization control unit 300 to output.

As shown in FIG. 5, the configuration of the data converter 100 is

A frame counter 110 that receives a 19 Mbps clock signal CK19M, generates and outputs a subframe signal CNT270 and a subframe number signal CNT9 of C4 data;

It operates according to the clock signal CK19M of 19 Mbps, and uses the sub frame signal CNT270 and the sub frame number signal CNT9 outputted from the frame counter 110 to convert the S bits into data or non-data in a frame of C4 data. And a selection bit processing unit 120 for outputting the selection control signal SCTRL for each subframe accordingly.

Non-information except for the S bit in the C4 data DAT19M using the subframe signal CNT270 and the subframe number signal CNT9 outputted from the frame counter 110 by operating according to the clock signal CK19M of 19 Mbps. A data extraction unit 130 for removing the data and outputting the information data DATEXT, generating and outputting a start signal FADEN according to the position of pure E4 data;

Receives data output from the selection bit processor 120 and the data extractor 130, generates data DAT17M aligned with a clock signal of 17 Mbps, and generates and outputs an overflow control signal OBUFEN. The unit 140 is made.

As shown in FIG. 6, the configuration of the selection bit processing unit 120 is

A control bit detector 121 for receiving C4 data DAT19M and detecting and outputting a value stored in a C bit for each subframe;

A control bit setting unit 122 for receiving the C bit value output from the control bit detection unit 121 and setting the value to '1' if the value is high, and setting the value to '-1' if the value is low; ,

The control bit setting unit 122 receives the control bit setting value output from the control bit 122 and calculates each subframe. If the calculated value is greater than 0, the selection bit control signal SCTRL is a logical low value. It consists of a control bit calculation unit 123 for generating and outputting.

As shown in FIG. 7, the configuration of the data generator 140 is

A selection bit control unit 141 which receives the selection bit control signal SCTRL output from the selection bit processing unit 120 and outputs an address control value ADD256 depending on whether the selection bit data is present;

A buffer level control unit which receives the address control value ADD256 output from the selection bit control unit 141 and generates and outputs a corresponding buffer level control signal CTRLBUF according to the current buffer level signal BUFLV input; 142),

An address assigning unit 143 which generates and outputs 256 unique addresses,

The address ADDR output from the address assigning unit 143 is input and corrected according to the address control value ADD256 outputted from the selection bit control unit 141, so that 256 parallel data DATFIFO are stored for each corresponding address. A parallel signal generator 144 for generating and outputting the same;

Receives the parallel data DATFIFO output from the parallel signal generator 144 and maintains the buffer level according to the buffer level control signal CTRLBUF output from the buffer level controller 142 to generate 8-bit C4 data. It consists of a data output unit 145 for outputting.

10, the configuration of the buffer level control unit 142,

A first type driver 142_1 for forming and outputting a clock to generate a logical high state of 241 clocks in the sub frame signal CNT270 output from the frame counter 110;

A second type driver 142_2 for forming and outputting a clock such that a logical high state is generated by 241 clocks in the sub frame signal CNT270 output from the frame counter 110;

A type control signal for receiving a buffer level signal BUFLV output from the data output unit 145 and an address control value ADD256 output from the selection bit control unit 141 and selecting a clock type according to two values. A form selector 142_3 for outputting PATSEL;

The buffer level control is performed by selecting one of the clock signals output from the first shape driver 142_1 and the second shape driver 142_2 by operating according to the shape control signal PATSEL output from the shape selection unit 142_3. And a level control selector 142_4 for outputting the signal CTRLBUF to the data output unit 145.

As shown in FIG. 8, the configuration of the parallel signal generator 144 is

The address ADDR output from the address assigning unit 143 is input and corrected according to the address control value ADD256 outputted from the selection bit control unit 141, so that 256 parallel data DATFIFO are stored for each corresponding address. It consists of 256 data parallelizing units 144_1 to 144_256 that are generated and output.

As shown in FIG. 9, the configuration of the first data parallelization unit 144_1 is

The driving signal and the retiming control signal are generated by using the signal ADDR outputted from the address assigning unit 143 and subtracting the address control value ADD256 outputted from the selection bit control unit 141. A comparator 144_1A to output;

An encoder 144_1B which receives information data DATEXT output from the data extractor 130 and outputs data of a corresponding bit according to a driving signal output from the comparator 144_1A;

When the retiming control signal output from the comparing unit 144_1A has a logical high value, the data output unit 145 matches the data output from the encoding unit 144_1B with the synchronization of the clock signal CK19M of 19 Mbps. It consists of a retiming unit 144_1C to output.

The configuration of the second data parallelizer 144_2 to the 256th data parallelizer 144_256 of the parallel signal generator 144 is the same as that of the first data parallelizer 144_1, and description thereof is omitted to avoid duplication. do.

As illustrated in FIG. 11, the configuration of the data forming unit 200 is

The driving setting unit 210 receives the overflow control signal OBUFEN output from the data converting unit 100, sets the corresponding flip-flop to high according to the value, and generates and outputs a driving control signal. Wow,

When the corresponding driving control signal is logically high according to the driving control signal output from the driving setting unit 210 by receiving the data DAT17M aligned with the 17 Mbps clock signal output from the data conversion unit 100, the data is received. Data output unit 220 for outputting the,

Receives the data output from the data output unit 220 and synchronizes to the clock signal (VCO17IN) of 17 Mbps and outputs the complete E4 data, and generates a synchronous control signal (CNTEN) to output to the phase synchronization controller 300 It is made of a portion 230.

Operation of the embodiment of the present invention made as described above is as follows.

First, the main operation of the present invention will be described. As shown in FIG. 4, the data converter 100 receives the C4 data DAT19M according to the clock signal CK19M of 19 Mbps and uses a first-in first-out buffer. It controls in a range where no underflow or overflow occurs and generates and outputs data synchronized with a clock signal of 17Mbps (VCO17IN).

The data forming unit 200 receives the sorted data DAT17M output from the data converting unit 100 and arranges the data in the form of E4 data according to a 17 Mbps clock signal.

In addition, the phase synchronization controller 300 receives the overflow control signal OBUFEN output from the data converter 100, and compares the synchronous control signal CNTEN output from the data generator 200. A phase synchronous control signal of the E4 data output from the data forming unit 200 is generated and output.

Hereinafter, an operation of the data converter 100 will be described in detail with reference to FIG. 5.

The frame counter 110 of the data converter 100 receives a 19 Mbps clock signal CK19M, generates and outputs a subframe signal CNT270 and a subframe number signal CNT9 of C4 data, and total 2430. It outputs by counting the clock and outputs the whole frame.

The selection bit processing unit 120 operates according to the clock signal CK19M of 19 Mbps, and uses the subframe signal CNT270 and the subframe number signal CNT9 output from the frame counter 110 to perform the C4 data. The S bits are processed as data or non-data in the frame, and accordingly, the selection control signal SCTRL for each subframe is output.

That is, the selection bit processing unit 120 detects five C bits for each subframe, and determines whether the S bits are data according to the value.

The data extracting unit 130 operates according to the clock signal CK19M of 19 Mbps, and uses the subframe signal CNT270 and the subframe number signal CNT9 outputted from the frame counter 110 to generate C4 data ( DAT19M removes the non-information data except for the S bit, outputs the information data DATEXT, and generates and outputs a start signal FADEN according to the position of pure E4 data.

The data generator 140 receives the data output from the selection bit processor 120 and the data extractor 130, generates data DAT17M aligned with a clock signal of 17 Mbps, and overflow control signal OBUFEN. Create and print

Hereinafter, the operation of the selection bit processing unit 120 will be described in detail with reference to FIG. 6.

The control bit detector 121 receives the C4 data DAT19M and detects and outputs a value stored in the C bit for each subframe.

The control bit setting unit 122 receives the C bit value output from the control bit detecting unit 121 and sets the value to '1' if the value is high, and sets the value to '0' if the value is low. do.

In addition, the control bit calculating unit 123 receives the C bit setting value output from the control bit setting unit 122 and operates for each subframe, and if the calculated value is larger than 0, the logical high is smaller than 0. The select bit control signal SCTRL is generated with the value of and is output to the data generator 140.

By doing the above, the selection bit processing unit 120 may determine whether or not the S-bit data according to the value of the C bit of each frame, the method is that three or more C bits of the five C bits in the sub-frame If the value is logical 1, the S bit of the corresponding subframe is processed as data. If the number of C bits having the value 1 is less than or equal to 1, the selection bit control signal SCTRL is performed to non-data process the S bit of the corresponding subframe. )

Hereinafter, a detailed operation of the data generator 140 will be described with reference to FIG. 7.

The selection bit control unit 141 receives the selection bit control signal SCTRL output from the selection bit processing unit 120 and outputs an address control value ADD256 depending on whether the selection bit is data.

The buffer level control unit 142 receives the address control value ADD256 output from the selection bit control unit 141 and corresponds to the buffer level control signal CTRLBUF according to the current buffer level signal BUFLV. Create and print

In addition, the address assigning unit 143 generates and outputs 256 unique addresses, and the parallel signal generating unit 144 receives the address ADDR output from the address assigning unit 143 and receives the selection bit control unit. Correction is performed according to the address control value ADD256 output from 141 to generate and output 256 parallel data DATFIFO for each corresponding address.

The data output unit 145 receives the parallel data DATFIFO output from the parallel signal generation unit 144 and adjusts the buffer level according to the buffer level control signal CTRLBUF output from the buffer level control unit 142. It generates and outputs 8-bit C4 data to the data forming unit 200.

The operation of the buffer level controller 142 is as shown in FIG. 10.

That is, the first type driver 142_1 of the buffer level controller 142 forms and outputs a clock such that a logical high state is generated by 241 clocks in the sub frame signal CNT270 output from the frame counter 110. The form is shown in Equation 3 below.

8181918181918181918181918181918181918181918181918181918181

The second form driver 142_2 forms a clock to generate a logical high state of 241 clocks in the sub frame signal CNT270 output from the frame counter 110, and the form is represented by Equation 4 below. Same as

91819191819191819191819191819191819191819191819191819181

In Equation 3 and Equation 4, a part written as '8' or '9' outputs a clock signal as a logical high value, and a part written as '1' outputs a clock signal as a logical low value. As a result, the jitter caused by the data being pushed to one side can be minimized.

The shape selection unit 142_3 receives a buffer level signal BUFLV output from the data output unit 145 and an address control value ADD256 output from the selection bit control unit 141, and then clocks according to two values. Outputs a form control signal PATSEL for selecting the form.

That is, 5 bits of the buffer level signal BUFLV are made into upper bits, 3 bits are added to '000' as lower bits, thereby making the 8-bit signal subtracted from the address control value ADD256. The result is the current buffer level.

With the above result, the second level clock signal is selected when the buffer level is 160 or more, and the second type clock signal is selected when the buffer level is 160 or more.

The above operation is applied every time the 270 counter value is '00000000', that is, once per subframe.

The level control selector 142_4 operates according to the form control signal PATSEL output from the form selector 142_3 and is output from the first form driver 142_1 and the second form driver 142_2. One of the clock signals is selected to output a buffer level control signal CTRLBUF to the data output unit 145.

Hereinafter, an operation of the parallel signal generator 144 will be described in detail with reference to FIG. 8.

The parallel signal generator 144 includes 256 data parallelizers 144_1 to 144_256 for each address, and each of the data parallelizers 144_1 to 144_256 is an address ADDR output from the address assigning unit 143. ) Is corrected according to the address control value ADD256 output from the selection bit control unit 141 to generate and output 256 parallel data DATFIFO for each address.

Hereinafter, an operation of the first data parallelization unit 144_1 will be described in detail with reference to FIG. 9.

The comparator 144_1B receives the address ADDR output from the address assigning unit 143 and uses the signal obtained by subtracting the address control value ADD256 output from the selection bit control unit 141. Generate and output a timing control signal.

That is, the comparison unit 144_1B subtracts the address control value ADD256 from the address ADDR. The upper three bits are output to the encoding unit 144_1B, and the lower five bits each bit. It is logically negative logic (NOR) and used as a retiming control signal of the retiming unit 144_1C.

The encoder 144_1B receives the information data DATEXT output from the data extractor 130 and outputs data of a corresponding bit according to a driving signal output from the comparator 144_1A. As shown in Table 1.

Driving signal 111 110 101 100 11 10 One 0 DATEXT [7: 0] DATEXT7 DATEXT6 DATEXT5 DATEXT4 DATEXT3 DATEXT2 DATEXT1 DATEXT0

The retiming unit 144_1C synchronizes the data output from the encoder 144_1B with the 19 Mbps clock signal CK19M when the retiming control signal output from the comparing unit 144_1A has a logical high value. In response to the data output unit 145.

The second data parallelizer 144_2 to the 256th data parallelizer 144_256 of the parallel signal generator 144 also output data in the same manner as the first data parallelizer 144_1. You can get parallel data.

On the other hand, as shown in Figure 11, the specific operation of the data forming unit 200 is as follows.

The driving setting unit 210 of the data forming unit 200 receives the overflow control signal OBUFEN output from the data converting unit 100, and sets the corresponding flip-flop to high according to the value. Generate and output the drive control signal.

The data output unit 220 receives data DAT17M aligned with a 17 Mbps clock signal output from the data conversion unit 100 and corresponds to a drive control signal output from the drive setting unit 210. Data is output when the drive control signal is logically high.

In addition, the synchronization unit 230 receives data output from the data output unit 220, synchronizes with the clock signal VCO17IN of 17 Mbps, outputs the complete E4 data, and generates the synchronous control signal CNTEN, thereby providing the phase. The synchronization controller 300 may generate a phase synchronization control signal.

By doing the above, the data conversion unit 100 and the data forming unit 200 converts the C4 data (DAT19M) input at a transmission rate of 19 Mbps to a transmission rate of 17 Mbps, and outputs an overflow or underflow during data conversion. Can be prevented from occurring, and as shown in FIG. 13, C4 data DAT19M is converted into E4 data DAT17M without departing from a predetermined threshold region of the buffer.

By doing the above, the phase synchronization can be appropriately performed at the place of receiving the data output from the present converter.

On the other hand, if configured as shown in Figure 12, the data conversion circuit as described above can process four channels at once.

That is, each data converter 1000, 2000, 3000, 4000 for each channel receives the respective C4 data (DAT19M1, DAT19M2, DAT19M3, DAT19M4) according to the clock signals CK19M1, CK19M2, CK19M3, and CK19M4. Each E4 data (DATOUT1, DATOUT2, DATOUT3, DATOUT4) is output in accordance with a clock signal VCO17IN having a single 17Mbps transmission rate. Thus, 622 data transmission can be performed.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, conversions, and modifications are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

Accordingly, the present invention operating as described above has a magnitude of jitter generated when converting C4 data of an AU4 frame into E4 data in the North American European optical transmission system using the E4 interface and the AU4 interface as a basis for data transmission. It is to provide a circuit for converting the C4 data of the AU4 frame to E4 data that can prevent the error of data transmission, thereby improving the quality of the communication service.

Claims (8)

In the circuit for converting the seed 4 data of the A4 frame of the optical transmission system to this 4 data, Data conversion means for receiving C4 data according to a 19 Mbps clock signal to control underflow and overflow using a first-in first-out buffer, and generating and outputting data driven according to a 17 Mbps clock signal; Data forming means for receiving the data output from the data converting means and arranging the data in the form of E4 data according to a 17 Mbps clock signal; A phase synchronous control means for receiving a signal output from the data converting means, comparing the signal output from the data forming means, and generating and outputting a phase synchronous control signal of the 4 data output from the data forming means; And circuit for converting the seed 4 data of the A4 frame to the 4 data. The method of claim 1, wherein the data conversion means, A frame counter which receives a 19 Mbps clock signal and generates and outputs one subframe signal and a subframe number signal of C4 data; By operating according to the clock signal of 19Mbps, using the sub-frame signal and the sub-frame number signal output from the frame counter, the S-bit is processed as data or non-data in the frame of C4 data, and accordingly the selection control signal for each sub-frame Selection bit processing means for outputting; Operating according to a clock signal of 19 Mbps, by using the sub frame signal and the sub frame number signal output from the frame counter, the non-information data except for the selection bit is removed from the seed 4 data and the information data is output. Data extraction means for generating and outputting a start signal according to the position of the; And a data generating means for receiving the data output from the selection bit processing means and the data extracting means, generating data aligned with a clock signal of 17 Mbps, and generating and outputting an overflow control signal. A circuit that converts seed 4 data of 4 frames into this 4 data. The configuration of the selection bit processing means according to claim 2, Control bit detection means for receiving C4 data and detecting and outputting a value stored in a control bit of a selection bit for each subframe; Control bit setting means for receiving a control bit value output from the control bit detecting means and setting the value to '1' if the value is high, and setting the value to '-1' if the value is low; The control bit operation unit receives the control bit setting value output from the control bit setting unit and operates for each subframe, and generates and outputs a selection bit control signal that is a logical high value when the calculated value is greater than 0 and a logical high value less than 0. A circuit for converting C4 data of an AU4 frame to E4 data, comprising bit calculation means. The method of claim 2, wherein the configuration of the data generating means, Selection bit control means for receiving a selection bit control signal output from the selection bit processing means and outputting an address control value according to whether the selection bit data is present; A buffer level control means for receiving an address control value output from the selection bit control means and generating and outputting a corresponding buffer level control signal according to the current buffer level signal input; Addressing means for generating and outputting 256 unique addresses; Parallel signal generation means for receiving an address output from the address assignment means, correcting according to the address control value output from the selection bit control means, generating and outputting 256 parallel data for each address; It includes a data output means for receiving the parallel data output from the parallel signal generating means to maintain the buffer level in accordance with the buffer level control signal output from the buffer level control means and to generate and output 8-bit C4 data A circuit for converting seed 4 data of an A4 frame to the 4 data. The structure of claim 4, wherein the buffer level control means comprises: First type driving means for forming and outputting a clock such that a logical high state is generated by 241 clocks in the sub frame signal output from the frame counter; A second type driving means for forming and outputting a clock such that a logical high state is generated by 241 clocks in the sub frame signal output from the frame counter; Form selection means for receiving a buffer level signal output from the data output means and an address control value output from the selection bit control means, and outputting a form control signal for selecting a clock form according to two values; A level which operates according to a shape control signal output from the shape selection means, selects one of clock signals output from the first shape driving means and the second shape driving means, and outputs a buffer level control signal to the data output means. And circuit for converting the seed 4 data of the A4 frame to the 4 data, comprising control selecting means. The structure of claim 4, wherein the parallel signal generating means comprises: And 256 data parallelization means for receiving the address outputted from the address assigning means, correcting according to the address control value outputted from the selection bit control means, and generating and outputting 256 parallel data for each address. A circuit for converting seed 4 data of an A4 frame to the 4 data. The structure of claim 6, wherein the first data parallelizing means comprises: Comparison means for receiving an address output from the address assignment means and generating and outputting a driving signal and a retiming control signal using a signal obtained by subtracting an address control value output from the selection bit control means; Encoding means for receiving information data output from the data extraction means and outputting data of a corresponding bit according to a driving signal output from the comparison means; And a retiming means for outputting data output from said encoding means to said data output means in synchronization with a 19 Mbps clock signal when the retiming control signal output from said comparing means has a logical high value. A circuit for converting the seed 4 data of the A4 frame to the 4 data. The structure of claim 1, wherein the data forming means comprises: Drive setting means for receiving an overflow control signal output from the data converting means, generating a drive control signal by setting a corresponding flip-flop high in accordance with the value thereof, and outputting the drive control signal; Data output means for receiving data aligned with a 17 Mbps clock signal output from the data conversion means and outputting data when a corresponding drive control signal is logically high according to a drive control signal output from the drive setting means; And a synchronizing means for receiving the data outputted from the data output means, synchronizing with a clock signal of 17 Mbps, outputting the complete E4 data, generating a synchronous control signal, and outputting the synchronous control signal to the phase synchronous control means. Reason 4 A circuit that converts seed 4 data in a frame to this data.