KR20010008449A - Method for manufacturing isolation layer of semiconductor device - Google Patents

Method for manufacturing isolation layer of semiconductor device Download PDF

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Publication number
KR20010008449A
KR20010008449A KR1019980063691A KR19980063691A KR20010008449A KR 20010008449 A KR20010008449 A KR 20010008449A KR 1019980063691 A KR1019980063691 A KR 1019980063691A KR 19980063691 A KR19980063691 A KR 19980063691A KR 20010008449 A KR20010008449 A KR 20010008449A
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South Korea
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trench
ions
semiconductor device
forming
device isolation
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KR1019980063691A
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Korean (ko)
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KR100386446B1 (en
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서광수
이종수
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for manufacturing an isolation layer of a semiconductor device is provided to prevent a junction leakage current between cells, by intensively implanting ions of a type opposite to a cell type to be formed under a trench part. CONSTITUTION: After a pad oxide layer and a nitride layer are evaporated on a semiconductor substrate(10), a trench part is formed. Ions of a type opposite to a cell type to be formed under the trench part are intensively implanted. After a gap fill oxide layer is thick evaporated on the trench part, a planarization process is performed to expose the pad oxide layer.

Description

반도체장치의 소자격리막 형성방법Device isolation film formation method of semiconductor device

본 발명은 반도체장치의 소자격리막 형성방법에 관한 것으로서, 보다 상세하게는 얕은 트랜치 소자격리막을 적용하는 반도체장치에서 셀간 접합누설전류의 발생을 방지하기 위해 트랜치부의 하부에 이후 형성될 셀 타입과 상대되는 이온을 강하게 주입시켜 셀간의 접합 누설전류를 방지할 수 있도록 한 반도체장치의 소자격리막 형성방법에 관한 것이다.The present invention relates to a method for forming a device isolation film of a semiconductor device, and more particularly, to a cell type to be formed later in a lower portion of a trench to prevent generation of junction leakage current between cells in a semiconductor device using a shallow trench device isolation film. A device isolation film forming method of a semiconductor device in which ions are strongly injected to prevent junction leakage current between cells.

최근의 반도체 기술은 소자의 고집적화 및 저전력화를 달성하기 위해 약 0.25㎛ 정도의 소자 분리 기술까지 요구하고 있다. 그런데 기존의 LOCOS(LOCal Oxidation of Silicon)나, PBLOCOS(Poly Buffered LOCal Oxidation of Silicon)등에 의한 소자격리막의 형성은 0.35㎛이하급으로 가면서는 한계를 보이고 있다.Recent semiconductor technologies require device separation techniques of about 0.25 μm in order to achieve high integration and low power. However, the formation of a device isolation film by the conventional LOCOS (LOCal Oxidation of Silicon) or PBLOCOS (Poly Buffered LOCal Oxidation of Silicon) has been limited to less than 0.35㎛.

이에 반도체 장치는 디바이스의 수행능력과 집적도를 크게 확보하면서 칩의 전체크기를 줄이는 것이 큰 문제로 대두되고 있다.For this reason, the semiconductor device has become a big problem to reduce the overall size of the chip while securing the performance and integration of the device.

얕은 트랜치 소자격리(Shallow Trench Isolation; 이하 "STI"라 한다)공정을 예로 들어 종래기술의 문제점을 설명한다. STI공정은 종래의 로커스(LOCal Oxidation of Silicon; LOCOS)공정에 비해 버즈비크(bird's beak)의 감소 등 많은 장점을 가지고 있기 때문에, 새로운 소자격리공정으로 각광받고 있다.The problem of the prior art will be described taking a shallow trench isolation process (hereinafter referred to as " STI ") as an example. Since the STI process has many advantages, such as a reduction in bird's beak, compared to the conventional LOCal Oxidation of Silicon (LOCOS) process, it has been spotlighted as a new device isolation process.

도 1 내지 도 4는 종래의 반도체장치의 소자격리막 형성방법을 설명하기 위해 반도체장치의 소자격리막 형성공정을 단계적으로 나타낸 단면도들이다.1 to 4 are cross-sectional views illustrating a process of forming a device isolation film of a semiconductor device in order to explain a method of forming a device isolation film of a conventional semiconductor device.

먼저, 도 1과 같이 실리콘기판(10) 상에 패드산화막(20)과 질화막(30)을 차례로 증착한 후 소자격리영역을 노출시킨 필드마스크를 이용한 사진식각공정에 의해 트랜치부(40)를 형성한다.First, as shown in FIG. 1, the trench 40 is sequentially formed by depositing the pad oxide film 20 and the nitride film 30 on the silicon substrate 10, and then forming a trench 40 by a photolithography process using a field mask exposing the device isolation region. do.

이때, 트랜치부(40)를 형성하기 위해 기판(10)을 식각할 때 트랜치부(40) 주변의 실리콘 기판(10)이 손상을 받아 결정결함(42)이 트랜치부(40) 내측면에 형성된다.At this time, when the substrate 10 is etched to form the trench 40, the silicon substrate 10 around the trench 40 is damaged and a crystal defect 42 is formed on the inner surface of the trench 40. do.

그런다음 도 2와 같이 트랜치부(40)의 내측벽에 희생산화막(45)을 형성한 후 도 3과 같이 갭필산화막(50)을 두껍게 증착하고 CMP공정을 진행하여 질화막(30)을 제거하여 평탄화시켜 소자격리막(55)을 형성한다.Then, as shown in FIG. 2, the sacrificial oxide film 45 is formed on the inner wall of the trench 40, and the gap fill oxide film 50 is thickly deposited as shown in FIG. 3, and the CMP process is performed to remove the nitride film 30 and planarize it. The device isolation film 55 is formed.

그리고, 이후 공정으로 도 4와 같이 N-WELL과 P-WELL을 형성하고 그 위로 게이트(G)와 소오스(S), 드레인(D)을 형성하여 PMOS트랜지스터와 NMOS트랜지스터의 셀을 형성하게 된다.Subsequently, as shown in FIG. 4, the N-WELL and the P-WELL are formed, and the gate G, the source S, and the drain D are formed thereon to form a cell of the PMOS transistor and the NMOS transistor.

그런데 위와 같이 방법에 의해 소자격리막을 형성할 때 도 1에서 트랜치부(40)의 내측벽면이 식각시 손상을 입어 발생된 결정결함(42)을 따라 트랜지스터의 소오스(S)와 드레인(D)에 전압이 가해질 때 접합누설전류가 발생되어 리플레쉬 시간을 감소시키고 소자의 전기적 특성 열화 및 신뢰성을 감소시켜 생산 수율을 떨어뜨린다는 문제점이 있다.However, when the device isolation film is formed by the method as described above, the source wall S and the drain D of the transistor are formed along the crystal defect 42 caused by the damage of the inner wall of the trench 40 during etching in FIG. 1. When the voltage is applied, the junction leakage current is generated, which reduces the refresh time, deteriorates the electrical characteristics of the device, and decreases the reliability of the production yield.

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 얕은 트랜치 소자격리막을 적용하는 반도체장치에서 트랜치부의 하부에 이후 형성될 소자의 셀 타입과 상대되는 이온을 강하게 주입시켜 셀간의 접합 누설전류를 방지할 수 있도록 한 반도체장치의 소자격리막 형성방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to inject a strong ion into a lower portion of a trench in a semiconductor device to which a shallow trench device isolation layer is applied, and then to ionize a cell corresponding to a cell type to be formed later. The present invention provides a method for forming a device isolation film of a semiconductor device so as to prevent a junction leakage current therebetween.

도 1 내지 도 4는 종래의 반도체장치의 소자격리막 형성방법을 설명하기 위해 반도체장치의 소자격리막 형성공정을 단계적으로 나타낸 단면도들이다.1 to 4 are cross-sectional views illustrating a process of forming a device isolation film of a semiconductor device in order to explain a method of forming a device isolation film of a conventional semiconductor device.

도 5 내지 도 8은 본 발명에 의한 반도체장치의 소자격리막 형성방법을 설명하기 위해 반도체장치의 소자격리막 형성공정을 단계적으로 나타낸 단면도들이다.5 to 8 are cross-sectional views illustrating a process of forming a device isolation film of a semiconductor device in order to explain a method of forming a device isolation film of a semiconductor device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

10 : 기판 20 : 패드산화막10 substrate 20 pad oxide film

30 : 질화막 40 : 트랜치부30 nitride film 40 trench portion

45 : 희생산화막 50 : 갭필산화막45: sacrificial oxide film 50: gap fill oxide film

55 : 소자격리막55 element isolation film

상기와 같은 목적을 실현하기 위한 본 발명은 반도체기판 상에 패드산화막과 질화막을 증착한 후 트랜치부를 형성하는 단계와, 트랜치부 하부에 이후 형성될 셀 타입과 상대되는 이온을 강하게 주입시키는 단계와, 이온 주입후 트랜치부에 갭필산화막을 두껍게 증착한 후 패드산화막이 노출되도록 평탄화하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for realizing the above object comprises the steps of forming a trench after depositing a pad oxide film and a nitride film on a semiconductor substrate, and strongly implanting ions in the lower portion of the trench relative to the cell type to be formed later; And depositing a gap fill oxide thickly in the trench after ion implantation, and then planarizing the pad oxide film.

위와 같이 이루어진 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention made as described above are as follows.

트랜치부를 형성한 후 트랜치부 하부에 이후 형성될 셀 타입과 상대되는 이온을 강하게 주입시켜 이후 셀을 형성할 때 전자와 정공이 쌍을 이루도록 하여 셀간 접합누설전류가 트랜치부를 형성할 때 발생된 결정결함을 따라 흐르는 것을 방지하게 된다.After the trench is formed, ions corresponding to the cell types to be formed later are strongly implanted into the lower portion of the trench so that electrons and holes are paired when forming cells later, so that a junction leakage current between cells forms a trench. It will prevent the flow along.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

도 5 내지 도 8은 본 발명에 의한 반도체장치의 소자격리막 형성방법을 설명하기 위해 반도체장치의 소자격리막 형성공정을 단계적으로 나타낸 단면도들이다.5 to 8 are cross-sectional views illustrating a process of forming a device isolation film of a semiconductor device in order to explain a method of forming a device isolation film of a semiconductor device according to the present invention.

먼저, 도 5와 같이 실리콘기판(10) 상에 패드산화막(20)과 질화막(30)을 차례로 증착한 후 소자격리영역을 노출시킨 필드마스크를 이용한 사진식각공정에 의해 트랜치부(40)를 형성한다.First, as shown in FIG. 5, the trench 40 is sequentially formed by depositing the pad oxide film 20 and the nitride film 30 on the silicon substrate 10, and then forming a trench 40 by a photolithography process using a field mask exposing the device isolation region. do.

그런다음 도 6과 같이 트랜치부(40)의 내측벽에 희생산화막(45)을 형성한 후 트랜치부(40) 하부에 이후 형성될 셀 타입과 상반되는 이온을 강하게 주입시키게 된다.Then, as shown in FIG. 6, after forming the sacrificial oxide film 45 on the inner wall of the trench 40, ions strongly opposed to the cell types to be formed later are strongly implanted into the trench 40.

즉, 이후 NMOS트랜지스터를 형성하기 위해 P-WELL이 형성되는 부분의 트랜치부(40) 하부에는 0.1㎛ 이하의 깊이로 7×1012∼ 8×1013개/㎠의 농도의 B이온을 강하게 주입시켜 B영역(44)을 형성하고 PMOS트랜지스터를 형성하기 위해 N-WELL이 형성되는 부분의 트랜치부(40) 하부에는 0.1㎛ 이하의 깊이로 7×1012∼ 8×1013개/㎠의 농도의 P이온을 강하게 주입시켜 P영역(46)을 형성한다.That is, in order to form an NMOS transistor, a strong ion of B ions having a concentration of 7 × 10 12 to 8 × 10 13 pieces / cm 2 at a depth of 0.1 μm or less is strongly injected into the lower portion of the trench portion 40 where the P-WELL is formed. To form the B region 44 and the lower portion of the trench portion 40 where the N-WELL is formed to form the PMOS transistor, the concentration of 7 × 10 12 to 8 × 10 13 / cm 2 at a depth of 0.1 μm or less. Of P ions are strongly implanted to form the P region 46.

그런다음 도 7과 같이 갭필산화막(50)을 두껍게 증착하고 CMP공정을 진행하여 질화막(30)을 제거하여 평탄화시켜 소자격리막(55)을 형성한다.Then, as shown in FIG. 7, the gap fill oxide film 50 is thickly deposited and the CMP process is performed to remove the planarized nitride film 30 to form a device isolation film 55.

그리고, 이후 공정으로 도 8과 같이 N-WELL과 P-WELL을 형성하고 그 위로 게이트(G)와 소오스(S), 드레인(D)을 형성하여 PMOS트랜지스터와 NMOS트랜지스터의 셀을 형성하게 된다.Subsequently, as shown in FIG. 8, the N-WELL and the P-WELL are formed, and the gate G, the source S, and the drain D are formed thereon to form cells of the PMOS transistor and the NMOS transistor.

위와 같이 트랜치부(40) 하부에 이후 형성되는 셀 타입과 상대되는 이온을 강하게 주입시켜 형성된 B영역(44)과 P영역(46)이 트랜치부(40) 주변의 결정결함(42) 영역을 포함하기 때문에 소오스(S)와 드레인(D)에 전압이 인가되면 트랜치부(40) 하부에서 전자-정공의 쌍이 형성되기 때문에 셀과 이웃하는 다른 셀간에 접합누설전류의 발생을 방지하게 된다.As described above, the B region 44 and the P region 46 formed by the strong implantation of ions corresponding to the cell type formed later in the trench portion 40 include the crystal defect 42 region around the trench portion 40. Therefore, when a voltage is applied to the source S and the drain D, electron-hole pairs are formed in the lower portion of the trench 40 to prevent the generation of a junction leakage current between the cell and other neighboring cells.

상기한 바와 같이 본 발명은 얕은 트랜치 소자격리막을 적용하는 반도체장치에서 셀간 접합누설전류의 발생을 방지하기 위해 트랜치부의 하부에 이후 형성될 셀 타입과 상대되는 이온을 강하게 주입시켜 이후 형성된 트랜지스터의 소오스와 트랜지스터에 전압이 인가될 때 전자-정공쌍을 이루어 셀간의 접합 누설전류를 방지함으로써 소자의 전기적 특성 및 신뢰성을 향상시킬 수 있다는 이점이 있다.As described above, in order to prevent generation of junction leakage current between cells in a semiconductor device to which a shallow trench device isolation layer is applied, a source of a transistor formed thereafter is formed by strongly implanting ions corresponding to a cell type to be formed later in the lower portion of the trench. When voltage is applied to the transistor, electron-hole pairs are formed to prevent junction leakage between cells, thereby improving the electrical characteristics and reliability of the device.

Claims (3)

반도체기판 상에 패드산화막과 질화막을 증착한 후 트랜치부를 형성하는 단계와,Forming a trench after depositing a pad oxide film and a nitride film on the semiconductor substrate; 상기 트랜치부 하부에 이후 형성될 셀 타입과 상대되는 이온을 강하게 주입시키는 단계와,Strongly implanting ions in the lower portion of the trench, the ions corresponding to cell types to be formed later; 이온 주입후 상기 트랜치부에 갭필산화막을 두껍게 증착한 후 상기 패드산화막이 노출되도록 평탄화하는 단계Depositing a gap fill oxide thickly on the trench after ion implantation, and then planarizing the pad oxide layer to expose the pad oxide layer. 를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 소자격리막 형성방법.Device isolation film forming method of a semiconductor device comprising a. 제 1항에 있어서, 상기 이온주입 단계는The method of claim 1, wherein the ion implantation step B이온이나 P이온을 0.1㎛ 이하의 깊이로 7×1012∼ 8×1013개/㎠의 농도로 주입하는 것을 특징으로 하는 반도체장치의 소자격리막 형성방법.A method for forming a device isolation film of a semiconductor device, comprising injecting B ions or P ions at a concentration of 7 × 10 12 to 8 × 10 13 / cm 2 at a depth of 0.1 μm or less. 제 2항에 있어서, NMOS영역에 B이온을 주입하고, PMOS영역에 P이온을 주입하는 것을 특징으로 하는 반도체장치의 소자격리막 형성방법.The method of claim 2, wherein B ions are implanted into the NMOS region and P ions are implanted into the PMOS region.
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Publication number Priority date Publication date Assignee Title
KR100745056B1 (en) * 2001-06-22 2007-08-01 주식회사 하이닉스반도체 Method for forming the Isolation Layer of Semiconductor Device
US20090159980A1 (en) * 2007-12-24 2009-06-25 Dae Kyeun Kim Semiconductor Device and Method of Fabricating the Same

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KR0150671B1 (en) * 1994-09-28 1998-12-01 김주용 Manufacturing method of semiconductor having a different isolation structure between peripheral circuit area and cell area

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100745056B1 (en) * 2001-06-22 2007-08-01 주식회사 하이닉스반도체 Method for forming the Isolation Layer of Semiconductor Device
US20090159980A1 (en) * 2007-12-24 2009-06-25 Dae Kyeun Kim Semiconductor Device and Method of Fabricating the Same

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