KR20010005453A - Method for packaging memory module having greater number of bandwidth than the number of data output from unit memory - Google Patents

Abstract

PURPOSE: A packaging method is provided to be capable of minimizing the size of a chip and improving the transmission rate of data, by making bigger the transfer width of a bus than the number of data outputted from a unit memory circuit. CONSTITUTION: A packaging method includes combining neighboring memory devices by two to form a pair of memory devices. One of the two memory devices combined into the pair of memory devices is built in a non-rotation type package. The other of the two memory devices combined into the pair of memory devices is built in a rotation-type package having a rotational symmetric structure. The first group of bus lines(BUS1) for carrying the first group of signals is connected to the pin of the non-rotation type package. The second group of bus lines(BUS2) for carrying the second group of signals is connected to the pin of the rotation type package. The third group of bus lines(BUS3) for carrying the third group of signals is commonly connected to the pin of the non-rotation type package and the rotation type package.

Description

Packaging method with greater transfer rate than the number of data output from unit memory {Method for packaging memory module having greater number of bandwidth than the number of data output from unit memory}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of packaging a memory, and more particularly, to a memory packaging method having a wider bandwidth than the number of data output from a unit memory.

Recently, research on computer systems has tended to have high operating speed and high frequency operating performance. Meanwhile, in a computer system, a memory device such as DRAM is used as main memory. These DRAMs use synchronous DRAM (SRAM), double data rate (SDRAM), and Rambus DRAM (hereinafter referred to as 'RDD') to achieve high performance to meet the needs of computer systems. Has been developed.

Rambus DRAMs have the following characteristics: That is, a plurality of Rambus DRAMs are arranged in series on a bus line of a memory system such as a Rambus system. Each of the Rambus DRAMs is controlled by a packet signal sequentially received during a predetermined period. Each of the Rambus DRAMs inputs and outputs data independently of each other. Currently, a Rim (Rambus inline memory module) used as a module of a computer system is composed of Rambus DRAMs. In this case, the Rambus DRAM sequentially outputs 8 consecutive data from one data pin, and the bandwidth is determined by the speed of the data and the number of data pins.

1 is a view showing the configuration of a typical Rambus system. Rims (RiMMs) applied to the Rambus system arrange several Rambus DRAMs (RDDs) on a module at regular intervals and connect pins or balls (which can be expressed differently depending on the package type). In addition, a Rambus DRAM operating based on command signals synchronized with the clock signal is determined.

2 is a diagram illustrating a rim RiMM configured using a memory formed by a conventional packaging method. 2 shows an example in which one x16 x 16 RDD is configured by using two x8 RDDs having 16 data pins (hereinafter, referred to as 'x16'). 3 is an enlarged view of a portion A of FIG. 2.

On the other hand, there are various ways to implement RDD having the same storage capacity and data pins. For example, 16M RDD may be implemented by combining two 8M x16 RDDs, or may be implemented by combining two 16M x8 RDDs. However, in case of x8 RDD, the chip size is increased by about 15% or more compared to the SDRAM, whereas in case of x16 RDD, the chip size is increased by about 25% or more compared to the SDRAM. Therefore, if the data pin or the data capacity is expanded by the conventional packaging method illustrated in FIG. 2, the chip size of the Rambus DRAM is greatly increased. In addition, the increase in Rambus DRAM greatly affects the increase in manufacturing costs and further increases the cost of computer systems.

The chip size of a Rambus DRAM depends largely on the number of data pins. Increasing the chip size of Rambus DRAMs increases manufacturing costs and computer system costs.

It is an object of the present invention to provide a packaging method in which the data rate is maintained or improved while the number of data pins is kept to a minimum. For example, by combining two 16M x8 bit RDD, to provide a packaging method such as implementing a 16M x16 bit RDD.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing the configuration of a typical Rambus system.

2 is a diagram illustrating a rim RiMM configured using a memory formed by a conventional packaging method.

3 is an enlarged view of a portion A of FIG. 2.

4 is a diagram illustrating a rim configured by using a memory formed by the packaging method according to the first embodiment of the present invention.

5 is a diagram illustrating a rim configured by using a memory formed by a packaging method according to a second embodiment of the present invention.

6 is a diagram illustrating a rim formed by using a memory formed by a packaging method according to a third embodiment of the present invention. FIG. 7 is a diagram illustrating a front side and a rear side of a memory formed by the packaging method according to the third exemplary embodiment of FIG. 6.

8 is a diagram illustrating a rim configured by using a memory formed by a packaging method according to a fourth embodiment of the present invention. FIG. 9 is a diagram illustrating a front and a rear surface of a memory formed by the packaging method according to the fourth embodiment of FIG. 8.

One aspect of the present invention for achieving the above object of the present invention is a packaging method of a plurality of memory devices arranged on a bus line of the memory system, each of the plurality of memory devices, input and output data independently of each other In addition, the present invention relates to a packaging method in which an operation is independently controlled by a group of signals sequentially received during a certain period. According to a preferred embodiment of the present invention, a packaging method includes: combining two adjacent memory devices to form a pair of memory devices; Embedding one of the two memory devices coupled to the pair of memory devices in a non-rotating package; And embedding another one of the two memory devices in a rotatable package that is rotationally symmetrical with respect to the non-rotating package; Coupling a first group of bus lines for transmitting a first group of signals to pins of the non-rotating package; Coupling a second group of bus lines for transmitting signals of a second group to pins of the rotatable package; And connecting a third group of bus lines for transmitting signals of a third group to the pins of the non-rotating package and the rotating package in common.

Another aspect of the present invention for achieving the above object of the present invention relates to a packaging method of a plurality of memory devices arranged on the bus line of the memory system. According to another preferred embodiment of the present invention, a packaging method includes combining two adjacent memory devices to form a pair of memory devices; Embedding one of the two memory devices coupled to the pair of memory devices in a non-inverting package; Embedding the other of the two memory devices in an inverted package that is mirror symmetrical with respect to the non-inverted package; Coupling a first group of bus lines for transmitting signals of a first group to pins of said non-inverting package; Coupling a second group of bus lines for transmitting signals of a second group to pins of the inverted package; And connecting the third group of bus lines for transmitting signals of the third group to the pins of the non-inverting package and the inverting package in common. The non-inverting package and the inverting package are paired and installed on the front and rear surfaces of the same printed circuit board (PCB).

According to the packaging method of the present invention, the data rate can be maintained or improved while the number of data pins is kept to a minimum.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

First, prior to describing the embodiments of the present invention, general matters regarding the determination of the impedance of a bus line are described. In a memory system using RDD, the impedance of the channel is, for example, 28 Ω, which is required to be a very low value compared to the conventional general channel impedance of 50 Ω to 80 Ω. And the impedance deviation of all the lines in the channel should be managed within +/- 10% to ensure accurate data transmission. This is very important in a real system and also requires the same conditions in the rim. In general, in designing an impedance in an actual rim, a tab-in part and a tab-out part (or, The part where no RDD is mounted is actually manufactured with 28Ω +/- 10%. However, the part where RDD is mounted is manufactured so as to have an impedance much higher than 28 Ω when manufacturing a printed circuit board (PCB) of a rim. This is so that when the RDD is mounted on the rim, the input capacitance of the RDD and the line impedance are combined so that the actual impedance is 28Ω +/- 10%. That is, the line impedance where RDD is not mounted is determined as √ (L _L / C _L ), and the line impedance after RDD mounting of the line where RDD is mounted is approximated as √ (L _L / (C _L + C _i )). Is calculated. Where L _L is the line inductance itself, C _L is the line itself capacitance, and C _i represents the input capacitance of RDD. Therefore, the impedance of the line on which the RDD is mounted is determined in consideration of the capacity of the input capacitance of the RDD.

Hereinafter, the packaging method of the present invention will be described in detail by explaining preferred embodiments of the present invention with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

In each of the embodiments illustrated in FIGS. 4 to 9, black circles represent data pins for inputting and outputting data of the first group or the second group DQA and DQB, and white circles indicate command pins for receiving a command. And a power pin for receiving power such as a power supply voltage VDD or a ground voltage VSS. In the present specification, for convenience of description, one data pin or command pin is typically connected to an external line, but data pins corresponding to the number of lines of the data line are connected in each package. Command pins corresponding to the number of lines are also connected to each package.

4 is a diagram illustrating a rim configured by using a memory formed by the packaging method according to the first embodiment of the present invention. 4 shows an example of enabling operation of one 16M x16 RDD by using two 16M x8 RDDs.

Referring to FIG. 4, a plurality of Rambus DRAMs are arranged on bus lines BUS1, BUS2, and BUS3 of a memory system. Two adjacent memory circuits (e.g., RDD1, RDD2) are selected as one memory pair. The odd-numbered Rambus DRAMs RD1, RDD3 arranged on the bus lines are packaged by a non-rotating package, i.e., a conventional package. The even-numbered Rambus DRAMs RDD2 and RDD4 arranged on the bus line are packaged by a rotating package, that is, a package in which a conventional package is rotated 180 degrees.

In this case, the first bus line BUS1 transmitting the first group of signals DQA is connected to the pins of the packages of the odd-numbered Rambus DRAMs RDD1 and RDD3 packaged by the non-rotating package. The second bus line BUS2 transmitting the second group of signals DQB is connected to pins of packages of even-numbered Rambus DRAMs RDD2 and RDD4 packaged by the rotary package. Here, the signals DQA and DQB of the first group and the second group represent data.

On the other hand, the third bus line BUS transmitting the third group of signals RQ is commonly connected to the non-rotating package and the rotating package. In other words, the third bus line BUS3 that transmits the signals other than data, that is, the command signal or the power supply voltage VDD, is connected to the pins of all RDDs arranged on the bus line.

Therefore, by the packaging method according to the first embodiment of the present invention, the non-rotating package and the pair of 16M x8 RDDs packaged by the rotating package operate as if they are one 16M x16 RDD.

Therefore, in the case of implementing 16M x16 RDD using two 8M x16 RDDs using a conventional packaging method, the chip size of 8M x16 RDD is increased by about 25% compared to SDRAM, according to the first embodiment of the present invention. Chip size is only about 15% larger than SDRAM.

However, in the case of packaging according to the first embodiment of the present invention, the third bus line BUS3 transmitting the third group of signals RD is connected to all Rambus DRAMs, while the first group and the second group are connected. Bus lines BUS1 and BUS2 of the first and second groups that transmit the signals DQA and DQB are connected one by one. Therefore, the bus lines BUS1 and BUS2 of the first and second groups and the bus lines BUS3 of the third group have difficulty in making impedances different from each other. In addition, physical constraints such as pin pitch of RDD or line width / insulation conditions may occur.

In order to solve this difficulty, a second embodiment of the present invention is presented. 5 is a diagram illustrating a rim configured by using a memory formed by a packaging method according to a second embodiment of the present invention.

As shown in FIG. 5, according to the packaging method according to the second exemplary embodiment of the present invention, bus lines BUS1 and BUS2 of the first group and the second group are also connected to the pins of all RDDs. At this time, the pins of the Rambus DRAMs RDD2 and RDD4 packaged in a rotatable package connected to the bus group BUS1 of the first group are not connected to their internal circuits. In addition, the pins of the Rambus DRAMs RDD1 and RDD3 packaged in the non-rotating package connected to the bus line BUS2 of the second group are not connected to their internal circuits.

Therefore, by the packaging method according to the second embodiment of the present invention, the transmission lines forming the bus lines BUS1 and BUS2 of the first and second groups are also the same as the transmission lines forming the bus lines BUS3 of the third group. It can be implemented as a line having an impedance. And as in the first embodiment, the non-rotating package and the pair of 16M x8 RDDs packaged by the rotating package operate as if they are one 16M x16 RDD.

6 is a diagram illustrating a rim formed by using a memory formed by a packaging method according to a third embodiment of the present invention. FIG. 7 is a diagram illustrating a front side and a rear side of an RDD formed by a packaging method according to the third embodiment of FIG. 6.

Also in the third embodiment of the present invention, an example of enabling operation of one 16M x16 RDD is shown using two 16M x8 RDDs.

Referring to FIG. 6, a plurality of Rambus DRAMs are arranged on bus lines BUS1, BUS2, and BUS3 of a memory system. Two adjacent memory circuits (e.g., RDD1, RDD2) are selected as one memory pair. The odd-numbered Rambus DRAMs RDD1 and RDD3 arranged on the bus line are packaged by a non-inverting package, that is, a conventional package. The even-numbered Rambus DRAMs RDD2 and RDD4 arranged on the bus line are packaged by an inverted package, that is, a package of a mirror symmetrical package of a conventional package. In this case, a pair of non-inverting packages and inverting packages are installed on the front and rear of the same printed board, respectively.

In this case, the first bus line BUS1 transmitting the first group of signals DQA is connected to pins of packages of odd-numbered Rambus DRAMs RDD1 and RDD3 that are packaged by a non-inverting package. The second bus line BUS2 transmitting the second group of signals DQB is connected to pins of packages of even-numbered Rambus DRAMs RDD2 and RDD4 packaged by the inverted package. As described above, the signals DQA and DQB of the first group and the second group represent data.

However, the third bus line BUS transmitting the third group of signals RQ is commonly connected to the non-inverting package and the inverting package. That is, the third bus line BUS3 is connected to the pins of all RDDs arranged on the bus line.

In addition, the RDD formed by the packaging method according to the third embodiment of the present invention has the same principle as in the first embodiment, and a pair of 16M x8 RDDs packaged by the non-inverting package and the inverting package are like one 16M. It works as if it were an x16 RDD.

However, even in the case of packaging according to the third embodiment of the present invention, for the same reasons as in the first embodiment, the bus lines BUS1 and BUS2 of the first and second groups and the bus lines BUS3 of the third group are used. Is difficult to produce different impedances.

In order to solve the difficulties of the third embodiment, a fourth embodiment of the present invention is presented. 8 is a diagram illustrating a rim formed by using a memory formed by a packaging method according to a fourth embodiment of the present invention. 9 is a diagram illustrating a front side and a rear side of an RDD formed by a packaging method according to the fourth embodiment of FIG. 8.

According to the packaging method according to the fourth embodiment of the present invention, the bus lines BUS1 and BUS2 of the first group and the second group are also connected to the pins of all the RDDs. However, similarly to the case of the second embodiment, the pins of Rambus DRAMs RDD2 and RDD4 packaged in the inverted package connected to the bus group BUS1 of the first group are not connected to their internal circuits. In addition, the pins of the Rambus DRAMs RDD1 and RDD3 packaged in the non-inverting package connected to the bus line BUS2 of the second group are not connected to their internal circuits.

Consequently, by the packaging method according to the fourth embodiment of the present invention, the transmission lines forming the bus lines BUS1 and BUS2 of the first and second groups are also the same as the transmission lines forming the bus lines BUS3 of the third group. It can be implemented as a line having an impedance.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

For example, in the present specification, embodiments that enable operation of one x16 16M RDD using two x8 16M RDDs are representatively described. However, the technical idea of the present invention is to provide various integration rates or various data rates (output data). Can also be applied to RDD.

Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the packaging method of the present invention, the transfer width of the bus is larger than the number of data output from the unit memory circuit. For example, by combining two 16M x8 bit RDDs, a 16M x16 bit RDD may be implemented. Therefore, according to the packaging method of the present invention, the data transfer rate is improved while the size of the chip is minimized.

Claims (14)

A packaging method of a plurality of memory devices arranged on a bus line of a memory system, wherein each of the plurality of memory devices inputs and outputs data independently of each other and is operated by a bundle of signals sequentially received during a predetermined period. In an independently controlled packaging method, Combining two adjacent memory devices to form a memory device pair; Embedding one of the two memory devices coupled to the pair of memory devices in a non-rotating package; And Embedding the other of the two memory devices in a rotatable package that is rotationally symmetrical with respect to the non-rotating package; Coupling a first group of bus lines for transmitting a first group of signals to pins of the non-rotating package; Coupling a second group of bus lines for transmitting signals of a second group to pins of the rotatable package; And And connecting a third group of bus lines for transmitting signals of a third group to the pins of the non-rotating package and the rotating package in common. The method of claim 1, wherein the memory device is a Rambus DRAM. According to claim 1, The memory device packaged into the non-rotating package is the memory device arranged odd-numbered in the bus structure, And the memory device packaged into the rotatable package is the memory device arranged evenly on the bus structure. According to claim 1, The first and second groups of signals are data signals, And the third group of signals are command signals. A packaging method of a plurality of memory devices arranged on a bus line of a memory system, wherein each of the plurality of memory devices inputs and outputs data independently of each other and is operated by a bundle of signals sequentially received during a predetermined period. In an independently controlled packaging method, Combining two adjacent memory devices to form a memory device pair; Embedding one of the two memory devices coupled to the pair of memory devices in a non-rotating package; And Embedding the other of the two memory devices in a rotatable package that is rotationally symmetrical with respect to the non-rotating package; Coupling a first group of bus lines for transmitting signals of a first group to pins of the non-rotating package and pins of the rotating package; Coupling a second group of bus lines for transmitting signals of a second group to pins of the non-rotating package and pins of the rotating package; And Connecting the third group of bus lines for transmitting signals of the third group to the pins of the non-rotating package and the rotating package in common; The pins of the rotatable package connected to the bus group of the first group are not connected to the internal circuit of the memory device, and the pins of the non-rotatable package connected to the bus line of the second group are the inside of the memory device. Packaging method characterized in that it is not connected to a circuit. 6. The method of claim 5, wherein the memory device is a Rambus DRAM. The method of claim 5, The memory device packaged into the non-rotating package is the memory device arranged odd-numbered in the bus structure, And the memory device packaged into the rotatable package is the memory device arranged evenly on the bus structure. The method of claim 5, The first and second groups of signals are data signals, And the third group of signals are command signals. A packaging method of a plurality of memory devices arranged on a bus line of a memory system, wherein each of the plurality of memory devices inputs and outputs data independently of each other and is operated by a bundle of signals sequentially received during a predetermined period. In an independently controlled packaging method, Combining two adjacent memory devices to form a memory device pair; Embedding one of the two memory devices coupled to the pair of memory devices in a non-inverting package; Embedding the other of the two memory devices in an inverted package that is mirror symmetrical with respect to the non-inverted package; Coupling a first group of bus lines for transmitting signals of a first group to pins of said non-inverting package; Coupling a second group of bus lines for transmitting signals of a second group to pins of the inverted package; And Connecting a third group of bus lines for transmitting a third group of signals to the pins of the non-inverting package and the inverting package in common; The non-inverting package and the inverting package is a pair, the packaging method characterized in that it is installed on the front and rear of the same printed circuit board (PCB). 10. The method of claim 9, wherein the memory device is a Rambus DRAM. The method of claim 9, The first and second groups of signals are data signals, And the third group of signals are command signals. A packaging method of a plurality of memory devices arranged on a bus line of a memory system, wherein each of the plurality of memory devices inputs and outputs data independently of each other and is operated by a bundle of signals sequentially received during a predetermined period. In an independently controlled packaging method, Combining two adjacent memory devices to form a memory device pair; Embedding one of the two memory devices coupled to the pair of memory devices in a non-inverting package; And Embedding another one of the two memory devices in a rotatable package that is rotationally symmetrical with respect to the non-inverting package; Coupling a first group of bus lines for transmitting signals of a first group to pins of the non-inverting package and pins of the inverting package; Coupling a second group of bus lines for transmitting signals of a second group to pins of the non-inverting package and pins of the inverting package; And Connecting a third group of bus lines for transmitting a third group of signals to the pins of the non-inverting package and the inverting package in common; The non-inverting package and the inverting package are paired and installed on the front and rear of the same printed circuit board (PCB), The pins of the inverted package connected to the bus lines of the first group are not connected to the internal circuit of the memory device, and the pins of the rotatable package connected to the bus lines of the second group are the inside of the memory device. Packaging method characterized in that it is not connected to a circuit. 13. The method of claim 12, wherein the memory device is a Rambus DRAM. The method of claim 12, The first and second groups of signals are data signals, And the third group of signals are command signals.