KR20010005106A - Method for forming plug of semiconductor device capable of preventing mask nitride loss - Google Patents

Method for forming plug of semiconductor device capable of preventing mask nitride loss Download PDF

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Publication number
KR20010005106A
KR20010005106A KR1019990025902A KR19990025902A KR20010005106A KR 20010005106 A KR20010005106 A KR 20010005106A KR 1019990025902 A KR1019990025902 A KR 1019990025902A KR 19990025902 A KR19990025902 A KR 19990025902A KR 20010005106 A KR20010005106 A KR 20010005106A
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South Korea
Prior art keywords
film
oxide film
plug
forming
semiconductor device
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KR1019990025902A
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Korean (ko)
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노용주
오찬권
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김영환
현대전자산업 주식회사
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Priority to KR1019990025902A priority Critical patent/KR20010005106A/en
Publication of KR20010005106A publication Critical patent/KR20010005106A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A plug formation method in semiconductor devices is provided to be capable of effectively preventing loss of a mask nitride film on word lines during the CMP process of an oxide film for flattening. CONSTITUTION: An oxide film is formed having the Si-Si combination as a polishing stop film on the entire structure for which word lines covered with a mask nitride film(24) and a nitride spacer(25). Then, an oxide film for planarizing is deposited . Next, the oxide film is treated by CMP process using ceria-base slurry having a high polishing selective ratio of the oxide film for the oxide film having the Si-Si combination.

Description

마스크 질화막의 손실을 방지할 수 있는 반도체 소자의 플러그 형성 방법{METHOD FOR FORMING PLUG OF SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING MASK NITRIDE LOSS}TECHNICAL FIELD FOR FORMING PLUG OF SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING MASK NITRIDE LOSS

본 발명은 반도체 메모리 소자 제조 분야에 관한 것으로, 특히 반도체 소자의 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method for forming a plug of a semiconductor device.

종래 반도체 소자의 플러그 형성 방법을 도1a 내지 도1c를 참조하여 설명한다.A method of forming a plug of a conventional semiconductor device will be described with reference to FIGS. 1A to 1C.

먼저, 도1a에 도시한 바와 같이 실리콘 기판(10) 상에 폴리실리콘막(11), 장벽금속막(12) 및 텅스텐막(13)의 적층 구조로 이루어지는 워드라인을 형성하고, 워드라인 상에 마스크 질화막(14), 워드라인 측벽에 질화막 스페이서(15)를 형성한 다음, 전체 구조 상에 장벽 질화막(16)을 형성하고, BPSG(borophopho-silicate glass) 등으로 평탄화를 위한 제1 산화막(17)을 형성한다.First, as shown in FIG. 1A, a word line having a stacked structure of a polysilicon film 11, a barrier metal film 12, and a tungsten film 13 is formed on a silicon substrate 10, and then on the word line. After forming the nitride film spacer 15 on the mask nitride film 14 and the word line sidewalls, the barrier nitride film 16 is formed on the entire structure, and the first oxide film 17 for planarization using borophopho-silicate glass (BPSG) or the like. ).

다음으로, 도1b에 도시한 바와 같이 실리카계 슬러리(silica base slurry)를 이용하여 제1 산화막(17)을 화학기계적연마(chemical mechanical polishing, 이하 CMP라 함) 공정으로 평탄화시키면서 마스크 질화막(14)을 노출시킨다. 도1b에서 도면부호 'S1'은 이상적인 CMP 공정 후의 표면을 나타내고, S2'는 실제 CMP 공정 후의 표면을 나타낸다.Next, as illustrated in FIG. 1B, the mask nitride film 14 is planarized by using a silica base slurry to planarize the first oxide film 17 by a chemical mechanical polishing (CMP) process. Expose In FIG. 1B, reference numeral 'S1' denotes the surface after the ideal CMP process, and S2 'denotes the surface after the actual CMP process.

이와 같이 평탄화가 완료된 전체 구조 상에 도1c에 도시한 바와 같이 제2 산화막(18)을 형성하고, 제2 산화막(18) 및 제1 산화막(17)을 선택적으로 식각하여 플러그 형성 영역을 노출시킨 다음, 플러그를 이룰 폴리실리콘막(19)을 형성한다.As shown in FIG. 1C, the second oxide film 18 is formed on the entire planarized structure, and the second oxide film 18 and the first oxide film 17 are selectively etched to expose the plug formation region. Next, a polysilicon film 19 for forming a plug is formed.

전술한 바와 같은 종래의 플러그 형성 과정에서는 제1 산화막(17)을 연마하기 위하여 실리카계 슬러리를 이용하는데, 실리카계 슬러리를 이용한 CMP 공정에서 산화막과 질화막 사이의 연마 선택비가 크지 않다. 한편, 웨이퍼 부분 별로 연마 속도가 크게 차이가 나고 연마 속도가 빠른 부분에서는 마스크 질화막(14)까지 연마되거나 심할 경우 그 하부의 텅스텐막(13)까지 연마된다. 이와 같이 마스크 질화막(14)이 심하게 손실될 경우에는 플러그 형성을 위한 자기정렬콘택 식각(self align contact etch) 공정에서 워드라인과 플러그 사이에 단락 불량이 발생하는 문제점이 있다.In the conventional plug formation process as described above, a silica slurry is used to polish the first oxide layer 17. In the CMP process using the silica slurry, the polishing selectivity between the oxide layer and the nitride layer is not large. On the other hand, in the portion where the polishing rate is significantly different for each wafer portion, and the polishing rate is high, the mask nitride layer 14 is polished or, if severely, the tungsten film 13 in the lower portion thereof. As such, when the mask nitride layer 14 is severely lost, there is a problem in that a short circuit defect occurs between the word line and the plug in a self align contact etch process for forming the plug.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 평탄화를 위한 산화막 CMP 공정에서 워드라인 상의 마스크 절연막의 손실을 효과적으로 방지할 수 있는 반도체 소자의 플러그 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention devised to solve the above problems is to provide a method for forming a plug of a semiconductor device which can effectively prevent the loss of the mask insulating film on the word line in the oxide film CMP process for planarization.

도1a 내지 도1c는 종래 기술에 따른 플러그 형성 공정 단면도,1A to 1C are cross-sectional views of a plug forming process according to the prior art;

도2a 내지 도2c는 본 발명의 일실시예에 따른 플러그 형성 공정 단면도.Figures 2a to 2c is a cross-sectional view of the plug forming process according to an embodiment of the present invention.

*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *

21: 폴리실리콘막 22: 확산방지막21: polysilicon film 22: diffusion barrier film

23: 텅스텐막 24: 마스크 질화막23: tungsten film 24: mask nitride film

25: 질화막 스페이서 26: 장벽 질화막25 nitride film spacer 26 barrier nitride film

27: 실리콘-리치 산화막 28: 제1 산화막27 silicon-rich oxide film 28 first oxide film

상기와 같은 목적을 달성하기 위한 본 발명은 제1 전도막 패턴, 상기 제1 전도막 패턴 상에 위치하는 마스크 질화막 및 상기 제1 전도막 패턴 측벽에 위치하는 절연막 스페이서 형성이 완료된 반도체 기판 상에 장벽절연막을 형성하는 제1 단계; 상기 장벽절연막 상에 실리콘-실리콘 결합을 갖는 제1 산화막을 형성하는 제2 단계; 상기 제2 단계가 완료된 전체 구조 상에 제2 산화막을 형성하고, 상기 제1 산화막을 연마정지막으로 이용하여 상기 제2 산화막을 연마하는 제3 단계; 상기 제3 단계가 완료된 전체 구조 상에 제3 산화막을 형성하는 제4 단계; 상기 제3 산화막, 상기 제2 산화막, 상기 제1 산화막 및 상기 장벽절연막을 선택적으로 식각하여 플러그 형성 영역을 노출시키는 제5 단계; 상기 제5 단계가 완료된 전체 구조 상에 플러그를 이룰 제2 전도막을 형성하는 제6 단계; 및 상기 제2 전도막을 선택적으로 제거하여 플러그를 형성하는 제7 단계를 포함하는 반도체 소자의 플러그 형성 방법을 제공한다.According to an aspect of the present invention, a barrier layer is formed on a semiconductor substrate on which a first conductive layer pattern, a mask nitride layer positioned on the first conductive layer pattern, and an insulating layer spacer formed on sidewalls of the first conductive layer pattern are completed. A first step of forming an insulating film; Forming a first oxide film having a silicon-silicon bond on the barrier insulating film; A third step of forming a second oxide film on the entire structure in which the second step is completed, and polishing the second oxide film using the first oxide film as a polishing stop film; A fourth step of forming a third oxide film on the entire structure in which the third step is completed; A fifth step of selectively etching the third oxide film, the second oxide film, the first oxide film, and the barrier insulating film to expose a plug formation region; A sixth step of forming a second conductive film to form a plug on the entire structure in which the fifth step is completed; And a seventh step of selectively removing the second conductive film to form a plug.

본 발명은 마스크 질화막 및 질화막 스페이서로 덮인 워드라인 형성이 완료된 전체 구조 상에 Si-Si 결합을 갖는 산화막(이하, 실리콘-리치(silicon-rich) 산화막이라 함)을 연마정지막으로서 형성하고, 평탄화를 위한 산화막을 증착한 다음, Si-Si 결합을 갖는 산화막에 대한 산화막의 연마 선택비가 높은 세리아계 슬러리(ceria base slurry)로 산화막을 CMP하여 워드라인 상의 마스크 질화막이 손실되는 것을 방지하는데 그 특징이 있다.According to the present invention, an oxide film having a Si-Si bond (hereinafter referred to as a silicon-rich oxide film) is formed as an abrasive stop film on the entire structure where the word line formation covered by the mask nitride film and the nitride film spacer is completed. After the deposition of the oxide film for the oxide, the oxide film to the oxide film having a Si-Si bond Ceria oxide (ceria base slurry) with a high polishing selectivity (ceria base slurry) to prevent the loss of the mask nitride film on the word line by CMP have.

이하, 본 발명의 일실시예에 따른 반도체 소자의 플러그 형성 방법을 도2a 내지 도2c를 참조하여 설명한다.Hereinafter, a method of forming a plug of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2C.

먼저, 도2a에 도시한 바와 같이 실리콘 기판(20) 상에 폴리실리콘막(21), 장벽금속막(22) 및 텅스텐막(23)의 적층 구조로 이루어지는 워드라인을 형성하고, 워드라인 상에 마스크 질화막(24), 워드라인 측벽에 질화막 스페이서(25)를 형성한 다음, 전체 구조 상에 50 Å 내지 600 Å 두께의 장벽 질화막(26), 50 Å 내지 600 Å 두께의 실리콘-리치 산화막(27) 및 BPSG 등으로 평탄화를 위한 제1 산화막(28)을 3000 Å 내지 800 Å 두께로 형성한다.First, as shown in FIG. 2A, a word line formed of a laminated structure of a polysilicon film 21, a barrier metal film 22, and a tungsten film 23 is formed on a silicon substrate 20, and then on the word line. After the nitride film spacer 25 is formed on the sidewalls of the mask nitride film 24 and the word line, the barrier nitride film 26 having a thickness of 50 kHz to 600 kHz and the silicon-rich oxide film 27 having a thickness of 50 kHz to 600 kHz are formed on the entire structure. ) And BPSG, etc., to form a first oxide film 28 to have a thickness of 3000 kPa to 800 kPa.

상기 마스크질화막(24)은 800 Å 내지 2500 Å 두께로 형성하고, 상기 질화막 스페이서(25)를 50 Å 내지 600 Å 두께로 형성한다.The mask nitride film 24 is formed to have a thickness of 800 2500 to 2500 Å, and the nitride film spacer 25 is formed to have a thickness of 50 Å to 600 Å.

상기 제1 산화막(28)은 HDP 산화막(high density plasma oxide), BPSG(borophospho-silicate glass), PSG(phospho-silicate glass), FSG(fluoro-silicate glass) 등으로 형성한다.The first oxide layer 28 is formed of HDP oxide (high density plasma oxide), borophospho-silicate glass (BPSG), phospho-silicate glass (PSG), fluoro-silicate glass (FSG), or the like.

다음으로, 도2b에 도시한 바와 같이 수소 이온농도(pH)가 6 내지 9이며 크기가 50 nm 내지 400 nm인 세리아(CeO2) 계열 슬러리를 100 ㎖/분 내지 400 ㎖/분의 속도로 주입하면서 제1 산화막(27)을 CMP하여 평탄화시킨다. 이와 같이 세리아계 슬러리를 이용한 CMP 공정은 실리콘-리치 산화막에 대한 산화막의 연마 선택비가 높기 때문에 웨이퍼 부분 별로 연마 속도가 차이나도 질화막까지 연마되지 않으며, 실리콘-리치 산화막(27)이 연마정지막으로 작용하여 마스크 질화막(24) 상에 장벽 질화막(26)이 잔류하게 된다. 따라서, 워드라인 상의 질화막 손실을 효과적으로 방지할 수 있다.Next, as illustrated in FIG. 2B, a ceria (CeO 2 ) -based slurry having a hydrogen ion concentration (pH) of 6 to 9 and a size of 50 nm to 400 nm is injected at a rate of 100 ml / min to 400 ml / min. While the first oxide film 27 is CMP planarized. As described above, in the CMP process using the ceria-based slurry, the polishing selectivity of the oxide film to the silicon-rich oxide film is high, so that even if the polishing rate is different for each wafer portion, the polishing film is not polished to the nitride film. As a result, the barrier nitride film 26 remains on the mask nitride film 24. Therefore, nitride film loss on the word line can be effectively prevented.

이와 같이 평탄화가 완료된 전체 구조 상에 도2c에 도시한 바와 같이 제2 산화막(29)을 형성하고, 제2 산화막(29), 제1 산화막(28), 실리콘-리치 산화막(27) 및 장벽질화막(16)을 선택적으로 습식 또는 건식각하여 플러그 형성 영역을 노출시킨 다음, 플러그를 이룰 폴리실리콘막(30)을 형성한다.Thus, as shown in FIG. 2C, the second oxide film 29, the first oxide film 28, the silicon-rich oxide film 27, and the barrier nitride film are formed on the entire structure of the planarization completed. (16) is selectively wet or dry etched to expose the plug forming region, and then a polysilicon film 30 for forming a plug is formed.

상기 플러그 형성 영역을 노출시키기 위한 식각 과정에서, 플러그 형성 영역으로 I형 또는 T형으로 노출시키는 식각마스크를 이용한다.In the etching process for exposing the plug forming region, an etching mask exposing the plug forming region to an I-type or T-type is used.

이후, 연마 또는 식각 공정 등을 실시하여 폴리실리콘막 플러그를 형성한다.Thereafter, a polishing or etching process is performed to form a polysilicon film plug.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은, 실리콘-리치 산화막을 연마정지막으로 이용하고 세리아계 슬러리를 사용하여 산화막을 연마함으로써 워드라인 상의 질화막이 손실되는 것을 억제하여 워드라인과 플러그 간의 단락 발생을 효과적으로 방지할 수 있다. 또한, 질화막이 직접 연마되지 않기 때문에 질화막의 특성 저하를 최소화할 수 있다. 따라서, 후속 공정에서 장벽금속막, 마스크 질화막 사이의 계면 결합력 약화를 방지할 수 있어 반도체 소자의 전기적 특성을 향상시킬 수 있다.According to the present invention, the silicon-rich oxide film is used as the polishing stop film and the oxide film is polished by using a ceria-based slurry to suppress the loss of the nitride film on the word line, thereby effectively preventing a short circuit between the word line and the plug. Can be. In addition, since the nitride film is not directly polished, deterioration of the characteristics of the nitride film can be minimized. Therefore, the weakening of the interfacial bond between the barrier metal film and the mask nitride film can be prevented in a subsequent process, thereby improving the electrical characteristics of the semiconductor device.

Claims (5)

반도체 소자의 플러그 형성 방법에 있어서,In the plug formation method of a semiconductor element, 제1 전도막 패턴, 상기 제1 전도막 패턴 상에 위치하는 마스크 질화막 및 상기 제1 전도막 패턴 측벽에 위치하는 절연막 스페이서 형성이 완료된 반도체 기판 상에 장벽절연막을 형성하는 제1 단계;Forming a barrier insulating film on a semiconductor substrate on which a first conductive film pattern, a mask nitride film disposed on the first conductive film pattern, and an insulating film spacer formed on the sidewalls of the first conductive film pattern are completed; 상기 장벽절연막 상에 실리콘-실리콘 결합을 갖는 제1 산화막을 형성하는 제2 단계;Forming a first oxide film having a silicon-silicon bond on the barrier insulating film; 상기 제2 단계가 완료된 전체 구조 상에 제2 산화막을 형성하고, 상기 제1 산화막을 연마정지막으로 이용하여 상기 제2 산화막을 연마하는 제3 단계;A third step of forming a second oxide film on the entire structure in which the second step is completed, and polishing the second oxide film using the first oxide film as a polishing stop film; 상기 제3 단계가 완료된 전체 구조 상에 제3 산화막을 형성하는 제4 단계;A fourth step of forming a third oxide film on the entire structure in which the third step is completed; 상기 제3 산화막, 상기 제2 산화막, 상기 제1 산화막 및 상기 장벽절연막을 선택적으로 식각하여 플러그 형성 영역을 노출시키는 제5 단계;A fifth step of selectively etching the third oxide film, the second oxide film, the first oxide film, and the barrier insulating film to expose a plug formation region; 상기 제5 단계가 완료된 전체 구조 상에 플러그를 이룰 제2 전도막을 형성하는 제6 단계; 및A sixth step of forming a second conductive film to form a plug on the entire structure in which the fifth step is completed; And 상기 제2 전도막을 선택적으로 제거하여 플러그를 형성하는 제7 단계A seventh step of selectively removing the second conductive film to form a plug 를 포함하는 반도체 소자의 플러그 형성 방법.Plug formation method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제3 단계에서,In the third step, CeO2계 슬러리를 이용하여 화학기계적연마 공정을 실시하는 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.A method for forming a plug of a semiconductor device, comprising performing a chemical mechanical polishing process using a CeO 2 slurry. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 절연막 스페이서 및 상기 장벽 절연막 각각을 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.And each of the insulating film spacer and the barrier insulating film is formed of a nitride film. 제 3 항에 있어서,The method of claim 3, wherein 상기 제1 전도막 패턴은,The first conductive film pattern is, 폴리실리콘막, 장벽금속막 및 텅스텐막이 적층되어 이루어지는 워드라인인 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.A method for forming a plug of a semiconductor device, comprising: a word line formed by laminating a polysilicon film, a barrier metal film, and a tungsten film. 제 2 항에 있어서,The method of claim 2, 상기 제3 단계에서,In the third step, 수소 이온농도(pH)가 6 내지 9이며 크기가 50 nm 내지 400 nm인 상기 CeO2계열 슬러리를 100 ㎖/분 내지 400 ㎖/분의 속도로 주입하면서 화학기계적 연마 공정을 실시하는 것을 특징으로 하는 반도체 소자의 플러그 형성 방법.A chemical mechanical polishing process is carried out while injecting the CeO 2 series slurry having a hydrogen ion concentration (pH) of 6 to 9 and a size of 50 nm to 400 nm at a rate of 100 ml / min to 400 ml / min. Plug formation method of a semiconductor device.
KR1019990025902A 1999-06-30 1999-06-30 Method for forming plug of semiconductor device capable of preventing mask nitride loss KR20010005106A (en)

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