KR20010004335A - High-speed data storage apparatus pipelined in semiconductor device - Google Patents

Abstract

PURPOSE: A data storing apparatus of a pipe line structure operating in a high speed in a semiconductor memory device is provided which operates in a high frequency by performing the data storing operation without clearing the previously stored data. CONSTITUTION: The device reads data stored in a cell during a read operation and then stores the read data for a random time and then outputs the data by a pipe line method. The data storing apparatus includes: the first and the second switching unit(NM1,NM2) to transfer the first and the second read data to the first and the second node in response to the first control signal; a precharge unit(100) to precharge the first and the second node to a power source voltage level in response to the first control signal; a data storing unit to store the first and the second read data transferred from the switching units into the first and the second input stage; the first output driving unit(131) pull-up/pull-down driving the first final output signal in response to the second control signal and the first output node level of the data storing unit; and the second output driving unit(132) pull-up/pull-down driving the second final output signal in response to the second control signal and the second output node level of the data storing unit. The first control signal controls the switching unit to transfer the first and the second read data to the first and the second storing node during the read operation, and the second control signal controls the output of the first and the second output node of the data storing unit.

Description

High-speed data storage apparatus pipelined in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device of a pipeline structure that operates at a high speed in a semiconductor memory device. In particular, the present invention relates to a pipe for storing read data in a synchronous DRAM (SDRAM) and then outputting data in a pipelined manner. It's about a pipe-register.

In general, SDRAM does not directly output read data to a data output pin during data read operation, but stores the data in a temporary storage device and sends the data out to the data output pin in synchronization with an external clock signal. The device is collectively called the pipe-register.

FIG. 1 is a circuit diagram schematically illustrating a conventional pipe-register, and FIG. 2 is a timing diagram illustrating an exemplary operation of the conventional pipe-register of FIG. 1. 1 and 2, a conventional pipe-register is described.

First, the signal shown in FIG. 1 and FIG. 2 is demonstrated. The "rdo" and "rdoz" signals are read data signals that read data stored in a memory cell. The "rdo" and "rdoz" signals are always kept at a "high" level and are either one of the two depending on the level of the cell data during the read operation. Only the "low" level. The "read" signal is a signal that is "high" enabled during the read operation of the SDRAM, and becomes "low" when the read operation is not performed to bring the two storage nodes (id and idz) of the pipe-register to the "low" level. Make. Then, the "pfetchz" signal is at a "low" level when the "read" signal is "high", that is, only during the read operation of the SDRAM, and the read data signals "rdo" and "rdoz" signals are stored in the storage node (id and idz). The "pocnt" signal is a signal for controlling the output of the data stored in the storage node (id, idz), and becomes a "high" level when outputting the data. That is, in response to the "high" level "pocnt" signal, data stored in the storage node (id, idz) is transferred to the output of the pipe-register (pu, pd). Finally, the "reset" signal is a pulse signal that is at the "high" level in synchronization with the falling edge of the "pfetchz" signal, which clears previous data stored in the register before the read data is stored in the pipe-register. Is a control signal. That is, all of the storage nodes id and idz are reset to "low" by the "reset" signal.

In Figure 2, the pulse width of the "pfetchz" signal and the "pocnt" signal is equal to one period of "CLOCK". Accordingly, when the frequency of the "CLOCK" signal is high (that is, the period of the "CLOCK" signal becomes short), the pulse width of "pfetchz" becomes small, and the "reset" signal and Since the "rdo / rdoz" signal must be generated, the pulse widths of the "reset" signal and "rdo / rdoz" must also be reduced. However, because "rdo / rdoz" is connected to the Global Data Bus Line, which has a large load, the transition slope of "rdo / rdoz" is gentle, so "rdo / rdoz" It is difficult to reduce the pulse width of and thus the pulse width of "reset" should be reduced accordingly. However, if the pulse width of "reset" is reduced, the levels of "id" and "idz" cannot be completely reset (that is, to a "low" level), which causes a malfunction.

In addition, when generating the "reset", "rdo" and "rdoz" signals with the original pulse width within the pulse width of the "pfetchz" signal, the PMOS transistor and the NMOS transistor at the input of the pipe-register are simultaneously turned on to short the circuit. Short current is generated.

As a result, the conventional pipe-registers as described above have a risk of malfunction at high frequencies, causing unnecessary current consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the data storage of a pipeline structure operating at a high speed in a semiconductor memory device capable of operating at a high frequency by performing a data storage operation without an operation of clearing previously stored data is possible. The purpose is to provide a device.

1 is a circuit diagram of a conventional pipe-register.

FIG. 2 is an operation timing diagram for explaining the conventional pipe-register of FIG.

3 is a circuit diagram of one embodiment of a pipe-register according to the present invention;

4 is an exemplary operation timing diagram for explaining the pipe-register of FIG. 3 according to the present invention.

* Description of the main parts of the drawing

100: precharge driving unit 110: high level driving unit

120: flip-flop unit 130: output driver

According to an aspect of the present invention, there is provided a data storage device for reading data stored in a cell during a read operation in a semiconductor memory device, storing the data for a predetermined time, and then outputting the data in a pipelined manner. First and second switching means for forwarding the first and second read data to the first and second nodes in response; Precharge means for precharging the first and second nodes to a power supply voltage level in response to the first control signal; Data storage means for receiving and storing the first and second read data received from the first and second switching means through first and second input terminals; First output drive means for pulling up and pulling down a first final output signal in response to a second control signal and a first output node level of the data storage means; And second output driving means for pull-up and pull-down driving a second final output signal in response to the second control signal and the second output node level of the data storage means, wherein the first control signal is generated during the read operation. A signal for controlling the switching means to deliver first and second read data to the first and second storage nodes, wherein the second control signal is for outputting at the first and second output node levels of the data storage means. Signal to control.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a circuit diagram of one embodiment of a pipe-register according to the present invention.

As shown in the figure, the pipe-register of the present invention receives the read data signal rdo / rdoz in response to the inverter INV1 and the inverted " pfetchz " signal from the inverter INV1. Precharge driver 100 precharges the node nrdo / nrdoz in response to the inverted " pfetchz " signal from the two switching transistors NM1 and NM2 and the inverter INV1 for delivering the signal to the node nrdo / nrdoz. ), The high level driver 110 for driving the node (nrdo / nrdoz) to the "high" level in response to the node (nrdo / nrdoz) level, the input terminal is connected to the node (nrdo / nrdoz), and the output terminal is the node ( An output driver for driving the output (pd / pu) of the pipe-resistor in response to the flip-flop unit 120, the " pocnt " signal of the NAND structure connected to the npd / npu, and the level of the node npd / npu. 130) and an inverter INV2 that receives the "pocnt" signal and inverts it.

Specifically, the precharge driver 100 is connected between the power supply voltage terminal and the node nrdo, and receives the PMOS transistor PM1 and the power supply voltage terminal and the node that receive the inverted "pfetchz" signal from the inverter INV1 to the gate. and a PMOS transistor PM2 connected between nrdoz and receiving an inverted " pfetchz " signal from the inverter INV1 to the gate.

The high level driver 110 is connected between the power supply voltage terminal and the node nrdo, and is connected between the PMOS transistor PM3 and the power supply voltage terminal and the node nrdoz to which the node nrdoz is connected to the gate. nrdo consists of a PMOS transistor PM4 connected to the gate.

The output driver 130 is sequentially connected between the power supply voltage terminal and the ground power supply terminal in series, and has a node PNP transistor PM5 connected to the gate, and a PMOS transistor PM6 receiving the inverted "pocnt" signal as a gate. and an NMOS transistor NM3 that receives a “pocnt” signal as a gate and an NMOS transistor NM4 having a node npd connected to the gate, so that a first output signal pd is connected to the PMOS transistor PM6 and the NMOS. PMOS transistor PM7 having a node npu connected in series with the first output unit 131 outputted from the common drain terminal of transistor NM3 and the power supply voltage terminal and the ground power supply terminal in series, and the inverted " a second output including a PMOS transistor PM8 that receives a “pocnt” signal as a gate, an NMOS transistor NM5 that receives a “pocnt” signal as a gate, and an NMOS transistor NM6 to which a node npu is connected to a gate; The signal pu is the PMOS transistor Emitter comprises a (PM8) and a second output unit 132 outputted from the common drain terminal of the NMOS transistor (NM5).

For reference, the read data signals rdo / rdoz are stored in the output nodes npu and npd of the flip-flop unit 120.

The "pfetchz" signal becomes a "low" level during the read operation, and transmits the read data signal rdo / rdoz to the node nrdo / nrdoz and controls to latch the data in the flip-flop unit 120. The "high" level of the "pfetchz" signal enables the precharge driver 100 to precharge the node (nrdo / nrdoz) to a "high" level to maintain the latched data of the flip-flop unit 120. give.

In addition, the "high" level "pocnt" signal drives the data npu and npd latched in the flip-flop unit 120 as the first and second output signals pu and pd.

On the other hand, due to the noise that may appear when the read data signal rdo / rdoz is input to the pipe-register, the level of the nodes nrdo and nrodz, which should be kept at the "high" level, may be shaken. This may make the latch operation of the flip-flop unit 120 unstable. Therefore, to prevent this, the high level driver 110 is provided.

FIG. 4 is an exemplary operation timing diagram for explaining the pipe-register of FIG. 3 according to the present invention. Referring to FIGS. 3 and 4, an exemplary operation of the pipe-register according to the present invention will be described.

First, the "high" level "pfetchz" signal is input and the PMOS transistors PM1 and PM2 of the precharge driver 100 are turned on so that the nodes nrdo and nrdoz are precharged to the "Vcc" level. In this case, the flip-flop unit 120 maintains previously stored data.

Next, during a read operation, a “pfetchz” signal having a “low” level is synchronously inputted to the falling edge of the clock signal CLOCK to turn off the PMOS transistors PM1 and PM2 of the precharge driver 100, thereby turning off the NMOS transistor ( By turning on the NM1 and NM2, the read data signals rdo and rdoz are transmitted to the nodes nrdo and nrdoz, respectively, and the nodes nrdo and nrdoz have the same level as the read data signals rdo and rdoz. In the embodiment of Fig. 4, the read data signal rdo is at the "high" level, and the other read data signal rdoz is at the "low" level within the pulse width of "pfetchz". Accordingly, the flip-flop unit 120 signals "low" to node npd and "high" level to node npu according to the node nrdo level of "high" and the node nrdoz level of "low". Latch.

Next, when the "pocnt" signal for controlling the output of the pipe-register is enabled as "high", the first output unit () by the node (npd) level of "low" and the node (npu) level of "high" The pull-up means PM5 and PM6 of 131 and the pull-down means NM5 and NM6 of the second output unit 132 are turned on, respectively, so that the first output signal pd of the "high" level and the second of the "low" level are turned on. Output the output signal pu.

The operation of the present invention as described above is equally applicable to the case where the read data signal rdo is at the "low" level and the other read data signal rdoz is at the "high" level, and thus a detailed description thereof will be omitted. However, the data levels stored in the flip-flop unit 120 are opposite to each other.

The pipe-register operation of the present invention as described above is the same as the operation of the conventional pipe-register, since there is no problem in operation even if the pulse width of the "pfetchz" signal is almost the pulse width of the read data signal (rdo / rdoz). Operation is possible at higher clock frequencies than conventional pipe-registers.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, unlike the prior art in which the previous data stored must be cleared before the current read data signal is stored using the reset signal and the read signal, the read data signal can be directly read without the clear operation of the previous data. By storing, there is an effect that the operating frequency can be increased compared to the conventional one, and the circuit realization can be simplified, thereby reducing the implementation area.

Claims (8)

A data storage device for reading data stored in a cell during a read operation in a semiconductor memory device and storing the data for a predetermined time and then outputting the data in a pipelined manner. First and second switching means for transferring the first and second read data to the first and second nodes in response to the first control signal; Precharge means for precharging the first and second nodes to a power supply voltage level in response to the first control signal; Data storage means for receiving and storing the first and second read data received from the first and second switching means through first and second input terminals; First output drive means for pulling up and pulling down a first final output signal in response to a second control signal and a first output node level of the data storage means; And Second output drive means for pull-up and pull-down driving a second final output signal in response to the second control signal and a second output node level of the data storage means, The first control signal is a signal for controlling the switching means to transfer the first and second read data to the first and second storage nodes during a read operation, The second control signal is a signal for controlling the output of the first and second output node levels of the data storage means. Pipeline data storage device that operates at a high speed in a semiconductor memory device. The method of claim 1, Power supply voltage level driving means for stabilizing unstable power supply voltage levels of the first and second nodes due to noise The data storage device of the pipeline structure that operates at a high speed in the semiconductor memory device further comprises. The method according to claim 1 or 2, The first switching means, A first transistor connected between an input terminal receiving the first read data and the first node and receiving the first control signal through a gate; The second switching means, A second transistor connected between an input terminal receiving the second read data and the second node and receiving the first control signal through a gate; Pipeline data storage device that operates at a high speed in a semiconductor memory device. The method according to claim 1 or 2, The precharge means, A first transistor connected between a power supply voltage terminal and the first node and receiving the first control signal through a gate; And A second transistor connected between a power supply voltage terminal and the second node and receiving the first control signal through a gate; Pipeline structure data storage device that operates at a high speed in the semiconductor memory device comprising a. The method of claim 2, The power supply voltage level driving means, A first transistor connected between a power supply voltage terminal and the first node and having a gate terminal connected to the second node; And A second transistor connected between a power supply voltage terminal and the second node and having a gate terminal connected to the first node; Pipeline structure data storage device that operates at a high speed in the semiconductor memory device comprising a. The method according to claim 1 or 2, wherein the first output drive means, It is connected in series between the power voltage terminal and the ground power terminal in sequence, A first transistor having a gate terminal coupled to the first output node of the data storage means; Second and third transistors receiving the second control signal through a gate terminal, respectively; And A fourth transistor having a gate terminal connected to the first output node of the data storage means, The first final output signal is output from a common drain terminal of the second and third transistors. Pipeline data storage device that operates at a high speed in a semiconductor memory device. The method of claim 1 or 2, wherein the second output drive means, It is connected in series between the power voltage terminal and the ground power terminal in sequence, A first transistor having a gate terminal connected to a second output node of the data storage means; Second and third transistors receiving the second control signal through a gate terminal, respectively; And A fourth transistor having a gate terminal connected to a second output node of the data storage means, The second final output signal is output from a common drain terminal of the second and third transistors. Pipeline data storage device that operates at a high speed in a semiconductor memory device. The method according to claim 1 or 2, The data storage means, An input terminal is connected to the first node and the second output node storing a previous data level, an output terminal is connected to the first output node, and is configured to perform negative logic multiplication of the first node level and the previous data level. 1 negative logical means; And An input terminal is connected to the first output node storing the second node and a previous data level, an output terminal is connected to the second output node, and is configured to perform negative logical multiplication of the second node level and the previous data level. 2 negative logical means Pipeline data storage device that operates at a high speed in the semiconductor memory device comprising a.