KR20010004034A - structure of ESD protection in semiconductor device - Google Patents

Abstract

PURPOSE: An electrostatic discharge prevention structure of a semiconductor device is to prevent an electrostatic fail from generating at a drain contact part adjacent to a pad. CONSTITUTION: An active region(201) is formed on a semiconductor substrate. At least one gate electrode line(203) is arranged in the same interval on the active region to cross the active region. A source and drain region(S,D) are formed at the active region on the both sides of the gate electrode line. A pad(207) is arranged on one side of the active region. A metal interconnection(209) connects the pad and the drain region, and includes the drain region and a plurality of contact parts(CT1-CTn). The plurality of contact parts is formed so that contact resistance within the contact parts are gradually reduced when they become more distant from the pad. The plurality of contact parts are formed so that their sizes are increased when they become more distant from the pad.

Description

Structure of ESD protection in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antistatic structure of a semiconductor device, and more particularly, to an antistatic structure of a semiconductor device capable of preventing an electrostatic fail occurring in a drain contact portion adjacent to a pad among drain regions contacted with the pad. .

In general, electrostatic discharge (ElectroStatic Discharge) is one of the factors that determine the reliability of the semiconductor chip, and occurs when handling the semiconductor chip or when mounted in the system, damage the chip. Therefore, in order to protect the semiconductor device from static electricity in the peripheral region of the semiconductor device, an antistatic circuit should be provided.

Here, general electrostatic modeling methods include a charge device model (CDM), a human body model (HBM), a machine model (MM), and the like.

The CDM method is a modeling method for testing the effect on the device when an electric charge that has been charged in a chip directly or indirectly outside the device is discharged through the device's outer lead pin at a moment, and the HBM method is applied to a human body. Modeling method for testing the effect of static electricity generated by the device on the device during the instant discharge through the device, MM method is the effect of static electricity generated by a charged work table or a device on the device during the instant discharge through the device Modeling method for testing

In general, the antistatic structure is integrated into the substrate as shown in FIG.

That is, referring to FIG. 1, the active region 101 is defined by local oxidation in a predetermined portion of the semiconductor substrate 100. The active region 101 may be, for example, a P well region, in which a MOS transistor is formed. At least one gate electrode line 103 is disposed on the active region 101 at equal intervals so as to traverse the active region 101. At this time, these gate electrode lines 103 are composed of a doped polysilicon film as is known.

Impurities are ion-implanted in both active regions 101 of the gate electrode line 103 to form a source and a drain region.

Meanwhile, a well pick-up line 105 through which a ground signal flows is disposed at one end of the active region 101, and a pad 107 is disposed at the other end of the active region 101.

At this time, the well pickup line 105 is electrically connected to one end of the adjacent gate electrode line 103, and the pad 107 is also contacted with the drain region by the metal wiring 107a. Here, reference numeral ct denotes a contact portion.

However, the conventional antistatic device has the following problems.

In general, antistatic circuits should be arranged symmetrically with each other to evenly distribute high currents generated by high voltage static electricity. However, according to FIG. 1, since the pad 107 is disposed on one side of the active region 101, the pad 107 is not exactly symmetrical in terms of signal transmission.

That is, when the antistatic circuit is arranged asymmetrically, there is a predetermined signal delay due to the difference in resistance between the A and B portions of FIG. As a result, the signal input from the pad 107 is delayed for a predetermined time while flowing to the contact part farthest from the pad, during which the signal is continuously applied to the contact part disposed adjacent to the pad 107. Since the contact portion disposed adjacent to the pad 107 has a high risk of failing due to static electricity.

Accordingly, an object of the present invention is to provide an antistatic structure of a semiconductor device capable of preventing the electrostatic fail generated in the drain contact portion adjacent to the pad among the drain regions in contact with the pad.

1 is a plan view in which an antistatic circuit of a conventional semiconductor element is disposed on a semiconductor substrate.

Figure 2 is a plan view showing a structure for preventing static electricity of the semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view of FIG. 2 taken along line III-III '.

(Explanation of symbols for the main parts of the drawing)

200-device isolation layer 201-active region

203-Gate electrode line 205-Well pickup line

206-Interlayer Insulator 207-Pad

208-Ti film 209-Metal wiring

In order to achieve the above object of the present invention, according to an embodiment of the present invention, a semiconductor substrate; An active region formed in a predetermined region of the semiconductor substrate; At least one gate electrode line disposed to cross the active region; Source and drain formed in active regions on both sides of the gate electrode line; A pad disposed on one side of the active area; And a metal wire having a drain region and a plurality of contact portions while connecting between the pad and the drain region, wherein the contact portion gradually decreases as the contact resistance in the contact portion increases with distance from the pad.

It is preferable that the size of the contact portion increases as the distance from the pad increases.

The contact portion may further include a contact resistance mitigating layer at each of the contact interfaces between the metal wiring and the drain region, and the thickness of the contact resistance mitigating layer is thicker as it is farther from the pad. At this time, the contact resistance relaxation layer is a silicide film.

In the antistatic circuit portion, the size of the contact portion for contacting the drain region and the metal wiring for electrically connecting the drain region and the pad is formed to gradually increase as the distance from the pad increases.

As a result, the contact portion close to the pad relatively increases the contact resistance, thereby dispersing and mitigating the signal concentrated from the pad. On the other hand, in the contact portion far from the pad, the contact resistance is relatively lowered to reduce the signal delay.

Therefore, during the electrostatic zapping, due to the asymmetry of the antistatic structure, it is possible to prevent the phenomenon in which the static electricity is concentrated to one place, it is possible to prevent the failure due to static electricity.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating a structure for preventing static electricity of a semiconductor device according to the present invention, and FIG. 3 is a cross-sectional view of FIG. 2 taken along line III-III '.

First, referring to FIG. 3, an isolation layer 200 is formed on a semiconductor substrate (not shown), thereby defining a rectangular active region 201. In this case, the active region 201 may be a P well region.

At least one gate electrode line 203 is disposed parallel to each other at equal intervals so as to cross the active region 201 on the active region 201.

One side of the gate electrode sign 203 is commonly tied by the well pickup line 205.

Impurities are implanted in each of the active regions 201 on both sides of the gate electrode line 203, so that source and drain regions S and D are formed.

The pad 207 is disposed on one side of the active area 201. The pad 207 and the drain region D are in contact with the metal wiring 209. Here, reference numeral CT1-CTn denotes a contact portion between the metal wiring and the drain region D. FIG. In this case, the contact parts CT1-CTn may be formed so as to be far from the pad 207 in order to reduce the signal delay difference between the area close to the pad 207 and the area far from the pad 207. The size is formed to increase sequentially. Then, since the contact hole size and the resistance value are proportional to each other, the portion of the contact spaced away from the pad 207 decreases the signal delay due to the low contact resistance, and the contact resistance increases to the portion adjacent to the pad 207, thereby intensively applying the pad. Signal is relaxed.

This will be described in more detail with reference to FIG. 3.

That is, referring to FIG. 3, a predetermined impurity is implanted into the active region 201 defined by the device isolation layer 200 to form a drain region D. Referring to FIG. Next, an interlayer insulating film 202 is formed over the active region 201. Thereafter, a predetermined portion of the interlayer insulating layer 206 is patterned so that a predetermined portion of the drain region D is exposed to form a contact hole h1-hn. At this time, the contact hole h1-hn is gradually larger in size as it moves away from the pad 207. Thereafter, in order to improve the adhesion property with the metal wiring film to be formed later, a Ti film 208 is formed as a barrier metal film on the inner wall of the contact hole h1-hn and the interlayer insulating film 206. At this time, the Ti film 208 is preferably formed thicker away from the pad 207. In this manner, the silicide film 206 is formed at the contact portion between the Ti film 208 and the drain region D. Since the silicide film 206 serves to lower the contact resistance, as is known, the thickness thereof is increased. The thicker the better the contact resistance. At this time, as the distance from the pad 207 increases, the thickness of the Ti film becomes thicker. Thus, the silicide film 206 in a portion far from the pad 207 is formed into a relatively thick film, and the contact resistance in the portion is improved.

Thereafter, a metal wiring 209 is formed over the Ti film 208. At this time, a tungsten film is used as the metal wiring 209f.

As described in detail above, according to the present invention, in the antistatic circuit portion, the size of the contact portion that contacts the drain region and the metal wiring for electrically connecting the drain region and the pad gradually increases as the distance from the pad increases. To form.

As a result, the contact portion close to the pad relatively increases the contact resistance, thereby dispersing and mitigating the signal concentrated from the pad. On the other hand, in the contact portion far from the pad, the contact resistance is relatively lowered to reduce the signal delay.

Therefore, during the electrostatic zapping, due to the asymmetry of the antistatic structure, it is possible to prevent the phenomenon in which the static electricity is concentrated to one place, it is possible to prevent the failure due to static electricity.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (4)

Semiconductor substrates; An active region formed in a predetermined region of the semiconductor substrate; At least one gate electrode line disposed to cross the active region; Source and drain formed in active regions on both sides of the gate electrode line; A pad disposed on one side of the active area; And A metal wiring having a drain region and a plurality of contact portions while connecting between the pad and the drain region, And the contact portion of the contact portion gradually decreases as the contact portion moves away from the pad. The semiconductor device of claim 1, wherein a size of the contact portion increases as the distance from the pad increases. The method of claim 1, wherein in the contact portion, a contact resistance alleviation layer is further provided at each of the contact interfaces between the metal wiring and the drain region, and the thickness of the contact resistance alleviation layer is thicker as the distance from the pad increases. An antistatic structure of a semiconductor device. 4. The antistatic structure of a semiconductor device according to claim 3, wherein the contact resistance alleviating layer is a silicide film.