KR20010003874A - circuit for preventing kickback voltage of LCD - Google Patents
circuit for preventing kickback voltage of LCD Download PDFInfo
- Publication number
- KR20010003874A KR20010003874A KR1019990024361A KR19990024361A KR20010003874A KR 20010003874 A KR20010003874 A KR 20010003874A KR 1019990024361 A KR1019990024361 A KR 1019990024361A KR 19990024361 A KR19990024361 A KR 19990024361A KR 20010003874 A KR20010003874 A KR 20010003874A
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- South Korea
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- voltage
- liquid crystal
- gate
- capacitor
- crystal display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
본 발명은 액정 디스플레이의 킥백 전압 방지 회로에 관한 것으로, 보다 상세하게는 액정 디스플레이 구동시 박막 트랜지스터의 게이트와 소오스 간의 기생 캐패시턴스에 의하여 야기되는 킥백전압을 제거할 수 있도록 한 액정 디스플레이의 킥백 전압 방지 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a kickback voltage prevention circuit of a liquid crystal display, and more particularly, to a kickback voltage prevention circuit of a liquid crystal display to eliminate a kickback voltage caused by parasitic capacitance between a gate and a source of a thin film transistor when driving a liquid crystal display. It is about.
종래의 액정 디스플레이는 도 1 에 도시한 바와같이 박막 트랜지스터의 게이트전압이 온된 상태에서 신호선을 통해서 박막트랜지스터의 데이타 전극에 인가된 신호전압은 소오스 전극을 통해 액정 캐패시터 및 저장 캐패시터에 인가된다.In a conventional liquid crystal display, as shown in FIG. 1, a signal voltage applied to a data electrode of a thin film transistor through a signal line while a gate voltage of a thin film transistor is turned on is applied to a liquid crystal capacitor and a storage capacitor through a source electrode.
이때 게이트 펄스와 함께 인가된 신호전압은 게이트 전압이 오프된 후에도 계속 유지된다.At this time, the signal voltage applied with the gate pulse is maintained even after the gate voltage is turned off.
그러나 게이트와 소오스사이의 기생 캐패시턴스(Cgs)때문에 화소전압은 도 2 에 도시한 바와같이 전압변화(ΔV)만큼의 변화가 발생하면서 전압쉬프트가 생기게 되고, 이때 전압쉬프트를 킥백전압이라고 하며, 이 킥백전압은 아래식에 의하여 나타낼 수 있게 된다.However, due to the parasitic capacitance (Cgs) between the gate and the source, the pixel voltage changes as much as the voltage change (ΔV), as shown in FIG. 2, resulting in a voltage shift, and the voltage shift is called a kickback voltage. The voltage can be expressed by the following equation.
ΔV = Cgs/(Cgs+Clc+Cst)*ΔVgΔV = Cgs / (Cgs + Clc + Cst) * ΔVg
여기서 ΔV 는 게이트 고전압(Vg high) - 게이트 저전압(Vg low), Clc 는 액정캐패시터, 그리고 Cst 는 저장 캐패시터를 나타낸다.Where ΔV is a gate high voltage (Vg high)-gate low voltage (Vg low), Clc is a liquid crystal capacitor, and Cst is a storage capacitor.
그러므로 상기 킥백전압에 의하여 액정의 신뢰성을 저하시키게 된다.Therefore, the kickback voltage reduces the reliability of the liquid crystal.
따라서 상기 액정의 신뢰성을 개선하고자 하는 측면에서 교류전압이 인가되게 되는데, 킥백전압(ΔV)에 의하여 정-부 극성의 비대칭에 의해 직류성분이 남게 되어 플리커(flicker), 잔상등과 같은 판넬 특성의 불량을 유발하게 되는 문제점을 가지게 되었다.Therefore, the AC voltage is applied in terms of improving the reliability of the liquid crystal, and the DC component remains due to the asymmetry of the positive-negative polarity due to the kickback voltage ΔV, so that the panel characteristics such as flicker, afterimage, etc. It has a problem that causes a defect.
본 발명의 목적은 액정 디스플레이에서 구동시 박막 트랜지스터의 게이트와 소오스간에 기생 캐패시턴스를 보상하여 상기 기생 캐패시턴스로 인한 킥백 전압 발생을 방지하고자 하는데 있다.An object of the present invention is to compensate for parasitic capacitance between a gate and a source of a thin film transistor when driving in a liquid crystal display to prevent kickback voltage generation due to the parasitic capacitance.
도 1 은 종래 액정 디스플레이의 단위 화소 등가 회로도1 is a unit pixel equivalent circuit diagram of a conventional liquid crystal display
도 2 는 종래 액정 디스플레이의 단위 화소 입출력 파형도2 is a unit pixel input and output waveform diagram of a conventional liquid crystal display
도 3 은 본 발명 액정 디스플레이의 단위 화소 등가 회로도3 is a unit pixel equivalent circuit diagram of the liquid crystal display of the present invention.
도 4 는 본 발명 액정 디스플레이의 단위 화소 입출력 파형도4 is a unit pixel input and output waveform diagram of the liquid crystal display of the present invention;
상기의 목적을 실현하기 위하여 본 발명은 액정 디스플레이에서 게이트전압과 데이타전압 간에 접속되어 있는 박막 트랜지스터의 소오스전극에 캐패시터를 접속하고 역전압이 인가되도록 구성한 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that a capacitor is connected to a source electrode of a thin film transistor connected between a gate voltage and a data voltage in a liquid crystal display, and a reverse voltage is applied.
따라서 본 발명에 의하면, 액정 디스플레이의 게이트전극과 데이타전극 간에 접속되어 있는 박막 트랜지스터의 게이트전극에 순차적으로 펄스를 인가하고, 해당 소오스 전극에 신호 전압을 인가하여 패널의 모든 화소를 구동할 때 상기 게이트와 소오스간에 기생 캐패시턴스에 의하여 야기되는 킥백전압에 대하여 소오스에 접속된 캐패시터로 전압 강하시켜 주게 되는 것이다.Therefore, according to the present invention, pulses are sequentially applied to a gate electrode of a thin film transistor connected between a gate electrode and a data electrode of a liquid crystal display, and a signal voltage is applied to the corresponding source electrode to drive all the pixels of the panel. The voltage drop is caused by the capacitor connected to the source against the kickback voltage caused by the parasitic capacitance between the source and the source.
이하 본 발명의 바람직한 실시예를 첨부되는 도면에 의거 상세히 설명하면 다음과 같다.Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention.
도 3 은 본 발명 액정 디스플레이의 단위 화소 등가 회로도 로서, 박막 트랜지스터 소자의 게이트 전극(G)에는 게이트 전압(Vg)을 접속하고 드레인 전극(D)에는 데이타전압(Vd)을 접속하고, 상기 소오스 전극(S)에는 액정(LC)를 접속한 화소에 있어서, 상기 소오스 전극(S)에 캐패스터(Cgs)를 접속하되, 이 캐패시터(Cgs)에는 게이트역전압9(-Vg)을 접속하여서 된 것이다.Fig. 3 is a unit pixel equivalent circuit diagram of the liquid crystal display of the present invention, in which a gate voltage Vg is connected to a gate electrode G of a thin film transistor element, and a data voltage Vd is connected to a drain electrode D. In (S), in the pixel to which the liquid crystal LC is connected, a capacitor Cgs is connected to the source electrode S, and a gate reverse voltage 9 (-Vg) is connected to the capacitor Cgs. will be.
이와같이 구성된 본 발명은 박막 트랜지스터 액정 디스플레이의 게이트전극에 순차적으로 펄스를 인가하고, 해당 소오스 전극에 신호 전압을 인가하면, 상기 게이트전압이 온된 상태에서 신호선을 통해서 박막트랜지스터의 데이타 전극에 인가된 신호전압은 소오스 전극을 통해 액정 캐패시터 및 저장 캐패시터에 인가된다.According to the present invention configured as described above, when a pulse is sequentially applied to a gate electrode of a thin film transistor liquid crystal display and a signal voltage is applied to the corresponding source electrode, the signal voltage applied to the data electrode of the thin film transistor through a signal line while the gate voltage is turned on. Is applied to the liquid crystal capacitor and the storage capacitor through the source electrode.
이때 게이트 펄스와 함께 인가된 신호전압은 게이트 전압이 오프된 후에도 계속 유지되고, 상기 게이트와 소오스사이의 기생 캐패시턴스(Cgs)때문에 화소전압에 전압변화(ΔV)가 발생되게 되지만, 상기 소오스 전극에 접속된 캐패시터(Cgs)와 이 캐패시터(Cgs)에 인가되는 역전압(-Vg)에 의하여 상기 기생 캐패시턴스에 전압강하되게 되므로 도 4 에 도시한 바와같이 기생 캐패시턴스(Cgs)에 의한 전압쉬프트가 발생되지 않게 되는 것이다.At this time, the signal voltage applied with the gate pulse is maintained even after the gate voltage is turned off, and a voltage change ΔV is generated in the pixel voltage due to the parasitic capacitance Cgs between the gate and the source, but is connected to the source electrode. Since the voltage drop is caused to the parasitic capacitance by the capacitor Cgs and the reverse voltage (-Vg) applied to the capacitor Cgs, the voltage shift due to the parasitic capacitance Cgs does not occur as shown in FIG. Will be.
이상에서 설명한 바와같이 본 발명은 액정 디스플레이에서 게이트전극과 데이타전극 간에 접속되어 있는 박막 트랜지스터의 소오스전극에 캐패시터를 접속하고 역전압이 인가되도록 구성하여 상기 박막 트랜지스터의 게이트전극과 소오스 전극에 신호 전압을 인가되어 패널의 모든 화소를 구동할 때 상기 게이트와 소오스간에 기생 캐패시턴스에 의하여 야기되는 킥백전압에 대하여 소오스에 접속된 캐패시터로 전압 강하시켜 줌으로써, 상기 기생 캐패시턴스에 의한 킥백전압을 플리커, 잔상등과 같은 판넬 특성의 불량요인을 해소할 수 있는 효과를 제공하게 되는 것이다.As described above, the present invention is configured such that a capacitor is connected to a source electrode of a thin film transistor connected between a gate electrode and a data electrode in a liquid crystal display so that a reverse voltage is applied, thereby providing a signal voltage to the gate electrode and the source electrode of the thin film transistor. When applied to drive all the pixels of the panel, the voltage is dropped to the capacitor connected to the source against the kickback voltage caused by the parasitic capacitance between the gate and the source. It is to provide an effect that can solve the bad factors of the panel characteristics.
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KR1019990024361A KR20010003874A (en) | 1999-06-25 | 1999-06-25 | circuit for preventing kickback voltage of LCD |
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KR1019990024361A KR20010003874A (en) | 1999-06-25 | 1999-06-25 | circuit for preventing kickback voltage of LCD |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101232164B1 (en) * | 2006-06-27 | 2013-02-12 | 엘지디스플레이 주식회사 | Liquid Crystal Display and Driving Method thereof |
US11222941B2 (en) | 2019-02-12 | 2022-01-11 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same for providing consistent display quality |
-
1999
- 1999-06-25 KR KR1019990024361A patent/KR20010003874A/en not_active Application Discontinuation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101232164B1 (en) * | 2006-06-27 | 2013-02-12 | 엘지디스플레이 주식회사 | Liquid Crystal Display and Driving Method thereof |
US11222941B2 (en) | 2019-02-12 | 2022-01-11 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same for providing consistent display quality |
US11605700B2 (en) | 2019-02-12 | 2023-03-14 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
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