KR20010003842A - Apparatus for storing digital broadcasting signal - Google Patents

Abstract

PURPOSE: An apparatus for storing digital broadcasting signal is provided to minimize data loss and a deterioration of image quality by storing the digital broadcasting signal during a constant period. CONSTITUTION: The apparatus for storing digital broadcasting signal includes following units. A receiving unit(30) receives a ground wave signal, a satellite signal and a cable signal. A TP(Transport) data demultiplexer(TP DEMUX)(32) selects a user's desired information and data from a transport signal transmitted by the receiving unit(30). A signal processing unit(38) is to store the selected information and data from the TP DEMUX(32) or IEEE1394 link layer chip(34B) to a hard disk(36). A PCI/IDE interface(46) prepares a signal transmission interface between the hard disk(36) and the signal processing unit(38). A MUX(40) provides any one signal among the output signals of the signal processing unit(38) and the receiving unit(30) to the TP DEMUX(32).

Description

Apparatus For Storing Digital Broadcasting Signal

The present invention relates to a digital broadcast signal storage device for storing a digital broadcast signal for a predetermined period and outputting the same at a time desired by a user.

In a conventional analog broadcast receiver, if necessary, a video tape recorder (VTR) is used for recording. In addition, the analog broadcast signal is compressed by the MPEG-2 (Moving Picture Experts Group 2: hereinafter referred to as "MPEG2") Main Level / Main Profile (hereinafter referred to as "ML / MP") method and the hard disk ( Hard disk). On the other hand, recently developed digital television (hereinafter referred to as "DTV") has not been developed a technology for storing / recording the received digital signals. Unlike conventional analog broadcasting systems, the DTV system uses MPEG2 Main Level / High Profile (hereinafter referred to as “ML / HP”) method as a compression method of broadcast signals. In addition, unlike an analog broadcasting system, the DTV system has a function of providing additional data. In the DTV system, the received high frequency signal is demodulated to extract digitized video, audio, and additional data signals.

1 shows a conventional broadcast signal storage / display apparatus for storing and displaying analog broadcast signals. The device shown in the figure is a device developed by the US broadcast service company "Tivo".

Referring to FIG. 1, a conventional broadcast signal storage / display apparatus includes a tuner 4 and an analog to digital converter connected in series between an antenna 2 and a hard disk 10. 6 and MPEG2 encoder 8, MPEG2 decoder 12 connected to hard disk 10, and multiplexer connected in common to tuner 4 and MPEG2 decoder 12: 14, a display unit 16 connected to an output terminal of the MUX 14, and a central processing unit for controlling the MPEG2 encoder 8 and the MPEG2 decoder 12: (Hereinafter referred to as "CPU") 18 is provided. The analog broadcast signal received from the antenna 2 is frequency-tuned for each channel by the tuner 4 and is commonly supplied to the A / D converter 6 and the MUX 14. The MPEG2 encoder 8 codes the signal converted into the digital form by the A / D converter 6 in the MPEG2 ML / MP method and stores the signal on the hard disk 10. In order to reproduce the digital signal stored in the hard disk 10, it is necessary to decode and output the coded digital signal. Accordingly, the MPEG2 decoder 12 is required as shown in FIG.

However, a method of storing a digital broadcast signal using a storage / display device as shown in FIG. 1 is an 8-bit digital signal when demodulating a radio frequency (RF) of the received digital broadcast signal. Considering the characteristics of the digital broadcast signal to be converted is a very inefficient method. Furthermore, in order to implement the analog broadcast signal storage device as shown in FIG. 1 in the DTV system, a separate MPEG2 ML / HP encoder should be installed. When a conventional MPEG2 ML / MP encoder is used, the image quality is degraded during signal reproduction. In addition, since the conventional encoder does not have a function of processing an On Screen Display (OSD), there is a problem in that service data provided by a DTV system cannot be used.

Accordingly, an object of the present invention is to provide a digital broadcast signal storage device capable of storing a digital broadcast signal while minimizing degradation of image quality or loss of data.

1 is a view showing a conventional broadcast signal storage / display device for storing and displaying analog broadcast signals.

2 is a diagram illustrating a digital broadcast signal storage device according to an exemplary embodiment of the present invention.

3 is a view illustrating in detail the signal processor shown in FIG.

4 is a detailed view of the PCI bridge shown in FIG.

<Description of the code | symbol about the principal part of drawing>

2: antenna 4: tuner

6: analog / digital converter 8: MPEG2 encoder

10,36: Hard Disk 12: MPEG2 Decoder

14,40: Multiplexer (MUX) 16,48: Display

18: central processing unit (CPU) 30: receiver

32: Transport Data Demultiplexer (TP DEMUX)

34A: IEEE1394 Physical Layer Chip 34B: IEEE1394 Link Layer Chip

38: signal processor 42: decoder / graphic processor

44: 1394 port 46: PCI / IDE interface

60: CPU interface 62: MUX control signal generator

64: PCI bridge 66: direction control unit

68: 8-bit TP generator 70: Serial TP / internal bus converter

72: 8-bit TP / internal bus converter 74: IEEE1394 interface

80A, 80B: first and second input buffers 82A, 82B: first and second output buffers

84: DMA control unit

In order to achieve the above object, the digital broadcast signal storage device of the present invention, the memory means for storing the digital broadcast signal, and converts the transport data of the digital broadcast signal into a signal form suitable for the memory means and transmits to the memory means And signal converting means for converting the data supplied from the memory means into a transport data form and outputting the data, and control means for controlling the speed at which the data is stored in the memory means and the speed output from the memory means.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 4.

Referring to FIG. 2, information and data desired by a user are selected from a receiver 30 for receiving terrestrial signals, satellite signals, and cable signals, and a transmission signal transmitted from the receiver (hereinafter referred to as “TP”). The TP data demultiplexer (TP Demultiplexer hereinafter referred to as " TP DEMUX ") 32 and the information and data selected from the TP DEMUX 32 or IEEE1394 Link layer chip 34B can be used as a hard disk. A signal processor 38 for storing in 36, a PCI / IDE interface 46 for providing a signal transmission interface between the hard disk 36 and the signal processor 38, and an output signal from the signal processor 38 And a digital broadcast signal storage device according to an embodiment of the present invention having a MUX 40 for supplying one of the output signals of the receiver 30 to the TP DEMUX 32.

When the digital terrestrial signal, satellite signal, and cable broadcast signal are input, the receiver 30 selects a frequency corresponding to the channel number, and then demodulates and outputs 8-bit TP data. Here, the receiver 30 demodulates the terrestrial signal by 8 VSB, the satellite signal by QPSK, and the cable broadcast signal by the QUAM method. The MUX 40 selects either the 8-bit TP data from the receiver 30 or the 8-bit parallel TP data from the signal processor 38 in response to the MUX control signal transmitted from the signal processor 38 to perform the TP DEMUX. It is supplied to 32. The TP DEMUX 32 selects image information, sound information, and user data desired by the user according to a packet identification signal (hereinafter, referred to as "PI"). If the TP DEMUX 32 does not need to store the selection data in the IEEE1394 link layer chip 34B or the hard disk 36, the TP DEMUX 32 supplies the selection data to the decoder / graphics processing unit 42. In addition, when the selection data is stored in the IEEE1394 link layer chip 34B or the hard disk 36, the TP DEMUX 32 transmits the selection data (video, audio, additional data, etc.) selected by the user to the signal processor 38. Will be supplied.

The decoder / graphics processor 42 decodes and reproduces the input image information and decodes and reproduces the sound information. In addition, the decoder / graphics processor 42 may generate subtitles, stock prices, news, weather forecasts, and program guides desired by the user using the user data. That is, the user can select the kind of data (video, sound, additional data, etc.) desired. The IEEE 1394 link layer chip 34B serves to convert the data packet supplied from the IEEE 1394 physical layer chip 34A into a regular standard and supply it to the signal processor 38. The IEEE 1394 physical layer chip 34A adds identification information about data supplied from the 1394 port 44 and supplies the IEEE 1394 link layer chip 34B with a predetermined packet size.

As shown in FIG. 3, the signal processor 38 includes a CPU interface 60, a MUX control signal generator 62, and a programmable communication interface (hereinafter, referred to as “PCI”) bridge (Bridge or Master) 64. ), A direction controller 66, an 8-bit TP generator 68, a serial TP / internal bus converter 70, an 8-bit TP / internal bus converter 72, and an IEEE1394 interface 74. The CPU interface 60 is responsible for the interface of the CPU address, data bus and other control lines. The MUX control signal generator 62 adjusts an input / output pin of the MUX 40 that can be arbitrarily used by a user by generating a MUX control signal. The 8-bit TP generating unit 68 converts 32-bit or 64-bit data from the PCI bridge 64 into 8-bit TP data and supplies it to the input terminal of the MUX 40. The serial TP / internal bus converting unit 70 and the 8-bit TP / internal bus converting unit 72 may convert a user-selected TP signal or all TP signals (serial TP, 8 bit TP) supplied from the TP DEMUX 32. The data is converted into a form suitable for the size and data format of the internal bus of (38) and supplied to the PCI bridge 64. The IEEE 1394 interface 74 serves to interface the isochronous data supplied from the direction control unit 66 to the IEEE 1394 link layer chip 34B.

The PCI bridge 64 is responsible for converting the CPU bus, internal bus and TP data into PCI signals. To this end, the PCI bridge 64, as shown in Figure 4, the first input buffer 80A, the second input buffer 80B, the first output buffer 82A, the second output buffer 82B, direct memory access (Direct Memory Access: hereinafter referred to as "DMA") A control unit 84 is provided. The first and second input buffers 80A and 80B and the first and second output buffers 82A and 82B are FIFO (First In First Out) buffers and are input by the control of the DMA controller 84. If the data is saved at a certain level, the stored data is output regardless of the CUP. That is, the first and second input buffers 80A and 80B store the stored data when the data inputted from the hard disk via the PCI / IDE interface 46 is greater than or equal to a predetermined data amount. The control is supplied to the 8-bit TP generating unit 68. These data are converted into 8-bit TP form by the 8-bit TP generating unit 68 and supplied to the MUX 40. Similarly, the first and second output buffers 82A and 82B have data input via the serial TP / internal bus converter 70 and the 8-bit TP / internal bus converter 72 more than a predetermined data amount. Then, the stored data is supplied to the PCI / IDE interface 46 under the control of the DMA controller 84. These data are stored in the hard disk 36 via the PCI / IDE interface 46. Since the buffers 80A, 80B, 82A, and 82B are allocated to one sector in the hard disk 36, the buffers 80A, 80B, 82A, and 82B are set to a size of 512 bytes so that data can be stored or output in units of sectors.

On the other hand, when the data stream of digital broadcasting is airwaves, it is transmitted at a transmission rate of 19.8 Mbps. In this case, a bus speed capable of receiving airwaves and storing them in the hard disk 36 and transferring the stored data back to the TP DEMUX 32 and time for controlling them must be satisfied. To this end, the present invention stores data in one buffer while outputting data stored in one buffer.

The data stored in the hard disk 36 is stored in the first and second input buffers 80A and 80B as follows. While the data stored in the hard disk 36 is stored in the first input buffer 80A at a transmission rate of up to 132.8 Mbps via the PCI / IDE interface 46, the data stored in the second input buffer 80B is 2.475 The 8-bit TP generator 68 is supplied in synchronization with a clock signal of MHz. When 512 bytes of data are stored in the first input buffer 80A, the data starts to be stored in the second input buffer 80B under the control of the DMA controller 84, and the first input buffer 80A. The data stored in starts to be supplied to the 8-bit TP generating unit 68. Similarly, when 512 bytes of data are stored in the second input buffer 80B, the data starts to be stored in the first input buffer 80A and the data stored in the second input buffer 80B is 8-bit TP. It is supplied to the generating part 68. Data input to the 8-bit TP generator 68 is converted into 8-bit TP and transmitted to the MUX 40.

The TP data is stored in the first and second output buffers 82A and 82B and the data stored in the first and second output buffers 82A and 82B are stored in the hard disk 36 as follows. . While the TP data selected by the TP DEMUX 32 is stored in the first output buffer 82A via the serial TP / internal bus converter 70 or the 8-bit TP / internal bus converter 72, The data stored in the two output buffers 82B is supplied to the hard disk 36 via the PCI / IDE interface 46. When 512 bytes of data are stored in the first output buffer 82A, the data starts to be stored in the second output buffer 82B under the control of the DMA controller 84 and the first output buffer 82A. The data stored in the is supplied to the hard disk 36 via the PCI / IDE interface 46. Similarly, when 512 bytes of data are stored in the second output buffer 82B, the selected TP data starts to be stored in the first output buffer 82A, and the data stored in the second output buffer 82B is stored. The hard disk 36 is supplied via the PCI / IDE interface 46.

On the other hand, when the data stored in the hard disk 36 is to be output, the data transmission speed between the hard disk 36 and the input buffers 80A and 80B maintains a speed of 19.8 Mbps which is the same as the airwave transmission speed of digital broadcasting. To be controlled. For this purpose, it is preferable to use a 32-bit 27 MHz or higher CPU as the internal bus control CPU, and clock synchronization must be strictly observed.

As described above, the digital broadcast signal storage device according to the present invention converts the TP data into a PCI signal and stores the digital broadcast signal while minimizing deterioration of image quality or data loss.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

An apparatus for storing a digital broadcast signal in real time, Memory means for storing the digital broadcast signal; Signal conversion means for converting the transport data of the digital broadcast signal into a signal form suitable for the memory means and transmitting the converted data to the memory means, and converting and outputting data supplied from the memory means into the transport data form; And control means for controlling a speed at which said data is stored in said memory means and a speed output from said memory means. The method of claim 1, The signal converting means comprises: a first buffer for temporarily storing a predetermined capacity of the transport data and transmitting the same to the memory means in an input order; A second buffer which alternately stores the transport data with the first buffer and transmits the transport data to the memory means in an input order; A third buffer for temporarily storing a predetermined amount of data supplied from the memory means and outputting the predetermined amount of data in an input order; And a fourth buffer configured to alternately store the data and output the data in the order of input. The method of claim 2, The signal converting means further comprises a buffer control unit for controlling the first and second buffers alternately and the third and fourth buffers alternately. Storage. The method of claim 1, A transport data demultiplexer for selecting the transport data and supplying the transport data to the signal conversion means; And a multiplexer for outputting any one of said digital broadcast signal and said transport data supplied from said signal converting means under control of said signal converting means.