KR20000067103A - Delay compensation circuit providing various and precious delay time - Google Patents

Abstract

PURPOSE: A delay compensation circuit is provided which can offer various and minute delay time. CONSTITUTION: In a delay synchronization loop providing a delayed advanced clock signal through a delay compensation circuit(20) by inputting a reference clock signal and according the phases of the reference clock signal and the advanced clock signal, the delay compensation circuit(20) comprises a number of delay stages(21,23,25,27) where at least above two delay devices are connected each other in parallel, and a number of switching parts(22,24,26,28) dividing the delay time by selecting one of the delay devices between the delay stages. The delay devices have different delay times respectively, and the delay time is determined by selecting the connection of the delay devices.

Description

Delay compensation circuit providing various and precious delay time

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to a delay compensation circuit that provides various fine delay times in a delay synchronization loop.

The delay locked loop is used to provide a clock signal having a shift of a certain time with respect to the reference clock signal. Although the clock signal provided by the delay lock loop circuit is delayed with respect to the reference clock, it is often phased ahead of the reference clock. Thus, in the present specification, for convenience of description, the signal generated by the delay synchronization loop is called an advanced clock signal.

In general, situations requiring a pre-clock signal are relatively high, such as Merged Memory with Logic (MML), Rambus DRAM (RDRAM), and Double Data Rate Synchronous DRAM (DDR). It occurs in an integrated circuit (IC) circuit having a high degree of integration. The reference clock signal is input to one pin and distributed throughout the device. The reference clock signal arriving at a portion relatively far from the input pin may be significantly delayed relative to the reference clock signal in the portion immediately adjacent to the input pin. This delay makes it difficult to maintain synchronization between parts of the IC.

To compensate for this problem, a delayed synchronization loop circuit can be included on the IC. The delay locked loop circuit is typically located close to the input pin for inputting the reference clock signal. This delay synchronization loop circuit receives a reference clock signal and generates a preceding clock signal. This preceding clock signal is generally similar to the reference clock signal. The reference clock signal is used continuously near the input pin of the reference clock signal, while the preceding clock signal is transmitted further away from the IC mentioned above in alignment with the original reference clock signal. In this way, a synchronized clock signal is received at every part of the IC, which operates the synchronized operation of the IC even at very high speeds.

However, the phase advances by approximately the same amount of time required for the preceding clock signal to reach far from parts of the integrated circuit where the clock is relatively close to the reference clock input pin. Therefore, it is essential to match the phase between the reference clock signal and the preceding clock signal, and the phases are matched by adjusting the delay time determined by the delay compensation circuit in the delay synchronization loop circuit.

Therefore, in order to increase the resolution of the delay synchronization loop circuit, a delay compensation circuit capable of providing various delay time and minute delay time is required.

An object of the present invention is to provide a delay compensation circuit that can provide a variety of fine delay time.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a delay synchronization loop circuit employing a delay compensation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating another embodiment of the delay compensation circuit of FIG. 1.

3 is a diagram illustrating a comparative example of the delay compensation circuit of FIG. 1.

In order to achieve the above object, the present invention provides a preceding clock signal which is delayed for a predetermined time through a delay compensation circuit by inputting a reference clock signal, and in a delay synchronous loop for matching a phase between the reference clock signal and the preceding clock signal, The compensation circuit includes a plurality of delay stages in which at least two delay elements are connected in parallel to each other, and a switching unit that selects one of delay elements between the delay stages and divides a delay time.

According to the delay compensation circuit of the present invention as described above, the delay time that can be selected is various and minute delay time can be realized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements. In this specification, a delay synchronization loop for inputting a reference clock signal to provide a preceding clock signal delayed for a predetermined time through a delay compensation circuit and matching a phase between the reference clock signal and the preceding clock signal is described.

First embodiment

1 is a diagram illustrating a delay synchronization loop circuit employing a delay compensation circuit according to an embodiment of the present invention. Referring to this, the delay synchronization loop circuit 10 includes a delay compensating circuit 20, a phase comparator 30, and a switch controller 40, and has a predetermined time delay with respect to the reference clock signal CLK. Generates (d_clk). The delay compensation circuit 20 includes a plurality of delay stages 21, 23, 25, and 27 and a plurality of switching units 22, 24, 26, and 28. Each of the delay stages 21, 23, 25, 27 consists of a simple delay element, a flip-flop or another switching element composed of an inverter chain, and delay elements T _Di , i = 1,3 having different delay times. , 5,7). In this embodiment, for convenience of explanation, an example in which one delay element T _Di , i = 1, 3, 5, 7 is connected to each of the delay stages 21, 23, 25, and 27 is described. At least two delay elements T _Di , i = 1 to 6 may be connected in parallel to each of the delay stages 21, 23, 25, and 27.

In the delay compensation circuit 20, one end of the first delay element T _D1 having the delay time τ is connected to the reference clock signal CLK, and the other end of the first delay stage 21 is connected to the first switching unit ( 22) is connected to the transmission gate (TG1). The reference clock signal CLK is also connected to the first delay element T _D1 , but is also connected to the transmission gate TG2 in the first switching unit 22. In the second delay stage 23, one end of the second delay element T _D3 having a delay time 2τ is connected to the output of the first switching unit 22, and the other end thereof is transmitted in the second switching unit 24. It is connected to the gate TG3. The output of the first switching unit 22 is also connected to the second delay element T _D3 , but is also connected to the transmission gate TG4 in the second switching unit 24. In the third delay stage 25, one end of the third delay element T _D5 having a delay time 4τ is connected to the output of the second switching unit 24, and the other end thereof is transmitted in the third switching unit 26. It is connected to the gate TG5. The output of the second switching unit 24 is also connected to the third delay element T _D5 , but is also connected to the transmission gate TG6 in the third switching unit 26. In the fourth delay stage 27, one end of the fourth delay element T _D7 having a delay time 8τ is connected to the output of the third switching unit 26, and the other end thereof is transmitted in the fourth switching unit 28. It is connected to the gate TG5. The output of the third switching unit 26 is also connected to the fourth delay element T _D7 , but is also connected to the transmission gate TG8 in the fourth switching unit 28. The output of the fourth switching unit 28 becomes the preceding clock signal d_clk. Therefore, the delay compensation circuit 20 is composed of delay paths in which the delay stages 21, 23, 25, 27 and the switching units 22, 24, 26, 28 are connected in series.

The phase comparator 30 compares the preceding clock signal d_clk and the reference clock signal CLK outputted from the delay compensation circuit 20 and according to the result, the phase comparison value of the up signal or the down signal. (p1) occurs. If the phase of the preceding clock signal d_clk is earlier than the phase of the reference clock signal CLK, an up signal is generated. If the phase of the preceding clock signal d_clk is behind the phase of the reference clock signal CLK, the signal is down. ) Generates a signal. The detected phase comparison value p1 is input to the switch controller 40, which will be described later, to switch the switches 22, 24 and 26 to divide the delay time of the delay compensation circuit 20. i = 1 ~ 4).

The switch controller 40 receives the phase comparison value p1 to generate the switch signals swi, i = 1 to 4, and delays the delay compensation circuit 20 by the up signal of the phase comparison value p1. The switch signals swi, i = 1 to 4 are generated to increase the time, and the switch signals swi, i = 1 to 4 are reduced to decrease the delay time of the delay compensation circuit 20 by the down signal of the phase comparison value p1. 4) occurs. The switch controller 40 is composed of a shift register or a counter circuit.

The operation of the delayed synchronization loop circuit 10 is as follows.

The delay compensation circuit 20 inputs the reference clock signal CLK and is controlled by the initial switch signals swi, i = 1 to 4 of the switch controller 40 to delay the reference clock signal CLK by a predetermined time, leading clock. Generate a signal d_clk. The delay time for the reference clock signal CLK passing through the delay compensation circuit 20 depends on whether the delay elements T _Di , i = 1, 3, 5, 7 in the delay compensation circuit 20 are operated. Different. The preceding clock signal d_clk is fed back and compared with the phase of the reference clock signal CLK input to the phase comparator 30. At this time, when the phase of the preceding clock signal d_clk is ahead of the phase of the reference clock signal CLK, the switch controller 40 switches the switch signal Swi of the "low level" according to the up signal generated by the phase comparator 30. i = 1 ~ 4) optionally occur. Accordingly, the "low level" switch signal swi, i = 1 to 4 turns the transfer gates TGi, i = 1,3,5,7 in the switching units 22, 24, 26, and 28 to turn. On "and the transfer gates TGi, i = 2,4,6,8 are " turned off " so that the delay elements T _Di , i = 1,3,5,7 in the delay compensation circuit 20 are turned on. ) Is activated selectively. Thus, the delay time of the delay compensation circuit 20 is increased so that the reference clock signal CLK is generated when the delay compensation circuit 20 passes through the delay elements T _Di , i = 1, 3, 5, 7. The phase of the preceding clock signal d_clk and the reference clock signal CLK are coincident with each other.

On the other hand, when the phase of the preceding clock signal d_clk falls behind the phase of the reference clock signal CLK, the switch controller 30 switches the switch signal Swi of the “high level” according to the down signal generated by the phase comparator 30. i = 1 ~ 4). The switch signal Swi, i = 1 to 4 of the "high level""turns-on" the transmission gates TGi, i = 2, 4, 6, and 8 in the switching units 22, 24, 26 and 28. And the transfer gates TGi, i = 1,3,5,7 are " turned off " so that the delay elements T _Di , i = 1,3,5,7 Shut off or short the operation. Thus, the delay time of the delay compensation circuit 20 is shortened so that the phase of the reference clock signal d_clk and the reference clock signal CLK generated when the reference clock signal CLK passes through the delay compensation circuit 20 is matched. .

Therefore, the delay synchronization loop circuit 10 of the present embodiment adjusts the delay time in the delay compensation circuit 20 to match the phase of the reference clock signal CLK and the preceding clock signal d_clk. τ, 2τ, 3τ,... 15 delay times, such as 15? This is advantageous in that the delay time that can be selected for the comparative example to be described later varies.

Second embodiment

FIG. 2 is a diagram illustrating another embodiment of the delay compensation circuit 20 of FIG. 1. Referring to this, the delay compensation circuit 120 is almost identical in operation to the delay compensation circuit 20 of FIG. 1. However, there is a difference in that the delay elements T _Di , i = 1 to 8 in the delay stages 121, 123, 125, and 127 are connected in parallel in pairs.

The delay compensation circuit 120 simply connects the delay elements T _Di , i = 1 to 8 in the delay stages 121, 123, 125, and 127 in response to the switch signals swi, i = 1 to 4, thereby providing a predetermined delay. Take time. This delay time can be adjusted in 0.1τ intervals between 4τ to 5.5τ. Thus, the fine delay time can be implemented to match the phase of the reference clock signal CLK and the preceding clock signal d_clk.

Comparative example

3 is a diagram illustrating a comparative example of the delay compensation circuits 20 and 120 of FIGS. 1 and 2. In general, delay elements 221, 223, 225, and 227 having the same delay time τ are connected to the delay compensation circuit 220 in series between the reference clock signal CLK and the preceding clock signal d_clk. The delay elements 221, 223, 225, 227 are arranged between the delay elements 221, 223, 225, 227 and connected or shorted to each other by the switching units 222, 224, 226, 228 in response to the switch signals swi, i = 1 to 4. Thus, the delay compensation circuit 220 generates a preceding clock signal d_clk having a predetermined delay time with respect to the reference clock signal CLK. In the delay compensation circuit 220, the reference clock signal CLK and the preceding clock are generated. The delay time that can be adjusted to match the phase with the signal d_clk is selected from four delay times such as τ, 2τ, 3τ, and 4τ.

However, the delay compensation circuit 220 of the present comparative example is not purely determined by the delay elements 221, 223, 225, 227, and the switching units 222, 224, 226, 228 connected to the preceding clock signal d_clk line in addition to the delay elements 221, 223, 225, 227. Since the delay time is determined due to the additional delay factor caused by the load of), there is a problem in implementing the correct delay time.

In addition, the delay compensation circuit 220 of the present comparative example implements 15 delay times using four delay elements T _Di , i = 1,3,5,7 of FIG. 1. ) Equally implements only four delay times with four delay elements (221, 223, 225, 227). This may be advantageous in that the delay time selectable by the delay compensation circuit 20 of FIG. 1 varies.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention described above, the delay time that can be selected in the delay compensation circuit is various and minute delay time is realized.

Claims (3)

A delay synchronous loop for inputting a reference clock signal to provide a preceding clock signal delayed for a predetermined time through a delay compensation circuit and matching a phase between the reference clock signal and the preceding clock signal. A plurality of delay stages in which at least two delay elements are connected in parallel with each other; And a switching unit for selecting one of the delay elements and dividing the delay time between the delay stages. The method of claim 1, wherein the delay stage Delay compensation circuit characterized in that the delay elements have a different delay time. The method of claim 2, wherein the delay stage And the delay elements are selectively connected or shorted to determine the delay time.