KR20000065606A - A Semiconductor Processing Chamber Improved in a Lower Structure - Google Patents

A Semiconductor Processing Chamber Improved in a Lower Structure Download PDF

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Publication number
KR20000065606A
KR20000065606A KR1019990012032A KR19990012032A KR20000065606A KR 20000065606 A KR20000065606 A KR 20000065606A KR 1019990012032 A KR1019990012032 A KR 1019990012032A KR 19990012032 A KR19990012032 A KR 19990012032A KR 20000065606 A KR20000065606 A KR 20000065606A
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South Korea
Prior art keywords
edge ring
wafer
chuck
processing chamber
semiconductor processing
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KR1019990012032A
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Korean (ko)
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원종식
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윤종용
삼성전자 주식회사
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Priority to KR1019990012032A priority Critical patent/KR20000065606A/en
Publication of KR20000065606A publication Critical patent/KR20000065606A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A chamber for treating semiconductor is provided to get a uniform result about treating wafer by arraying a wafer on a chuck exactly and to discharge pollutant on the corner of an edge ring easily. CONSTITUTION: In a chamber for treating semiconductor, an internal upper corner of an edge ring(3') faced with a chuck(1) is treated roundly or is inclined. Even if wafer(11) weren't arrayed on the chuck exactly, a corner of wafer wouldn't be hung over the edge ring and a wafer would slide down according to a corner of the edge ring treated roundly. Consequently, the wafer is placed on the chuck(1) precisely. Pollutant on the corner of edge ring or between the chuck and the edge ring is inhaled into outlet(9) easily by pumping of an exhaust pump. In case of turning the edge ring during the process, the pollutant also is discharged to the outside by only centrifugal force.

Description

하부구조가 개선된 반도체 처리 챔버{A Semiconductor Processing Chamber Improved in a Lower Structure}A semiconductor processing chamber improved in a lower structure

본 발명은 반도체 처리 챔버에 관한 것으로 특히 그 하부구조의 개선에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor processing chambers and in particular to improvements in their substructure.

통상 반도체 웨이퍼에 대한 식각이나 증착 등의 여러 공정은 각각의 처리 챔버 내에서 이루어진다. 이러한 반도체 처리 챔버에는 여러 장의 웨이퍼를 동시에 처리하는 배치 타입(batch type)과 웨이퍼 한 장 단위로 처리하는 싱글 타입(single type)이 있는데, 본 발명은 이중 싱글 타입 처리 챔버의 하부구조 개선에 관한 것이다.In general, various processes such as etching and deposition of semiconductor wafers are performed in respective processing chambers. Such a semiconductor processing chamber has a batch type for processing several wafers simultaneously and a single type for processing a single wafer, and the present invention relates to improving the infrastructure of a dual single type processing chamber. .

통상의 싱글 타입 반도체 처리 챔버의 하부구조는 도 1에 도시된 바와 같이, 웨이퍼가 놓이게 되는 척(chuck)(1), 척(1)의 둘레에 링의 형태로 웨이퍼를 안내하여 웨이퍼가 척(1) 위에 정확하게 놓이게 하는 에지 링(edge ring)(3), 에지 링(3)의 둘레에 역시 링의 형태로 이루어지고 플라즈마 등을 웨이퍼 쪽으로 집중시키는 포커스 링(focus ring)(5)을 구비한다. 도 1에서 참조부호 7은 처리 챔버의 벽이고, 9는 배기펌프(미도시) 등에 연결되어 처리 부산물이나 가스 등을 배출하기 위해 처리 챔버의 바닥에 형성된 배출구이다.As shown in FIG. 1, the substructure of a conventional single type semiconductor processing chamber is a chuck 1 on which a wafer is placed, and guides the wafer in the form of a ring around the chuck 1 so that the wafer is chucked ( 1) It is provided with an edge ring 3 to be placed on top of it, and a focus ring 5 around the edge ring 3 which is also in the form of a ring and focuses plasma and the like toward the wafer. . In FIG. 1, reference numeral 7 denotes a wall of the treatment chamber, and 9 denotes an outlet formed at the bottom of the treatment chamber to be connected to an exhaust pump (not shown) or the like to discharge treatment by-products or gases.

한편, 도 1의 2-2선 확대단면도인 도 2를 보면, 에지 링(3)이 척(1)에 비해 그 높이가 약간 높게 되어 있음을 알 수 있다. 또한, 척(1), 에지 링(3) 및 포커스 링(5)의 사이에는 약간의 간격이 있어, 웨이퍼(11)를 척(1) 위에 놓을 때 에지 링(3)이 약간 유동할 수 있도록 되어 있다. 그런데, 도 2에 도시된 바와 같이, 종래의 처리 챔버는 그 에지 링(3)의 모서리가 직각으로 이루어져 있어 웨이퍼(11)가 정확히 척(1) 위에 놓이지 않으면 에지 링(3) 위에 걸쳐서, 이렇게 부정확하게 정렬된 웨이퍼에 식각이나 증착 등의 처리를 하게 되면 식각이나 증착 등의 결과가 불균일하게 되거나 척(1)에서 벗어난 웨이퍼(11)의 주변부에는 처리가 되지 않는 불량을 초래할 수 있다. 또한, 에지 링(3) 표면이나 척(1)과 에지 링(3)의 사이에는 처리가스나 부산물 등이 부착하여 오염원이 되는데, 이러한 오염 물질은 처리 중에 배기펌프를 이용하여 배출구(9)로 배출하고, 또한 소정 수의 웨이퍼를 처리한 다음 정기적으로 챔버 내부를 청소하여 제거하고 있다. 그러나, 도 2에 도시된 바와 같이 에지 링(3)의 모서리가 직각을 이루고 있기 때문에, 에지 링(3)의 모서리에 부착된 오염 물질이 배기펌프에 의해서는 쉽게 배출되지 못하게 된다. 따라서 챔버 청소 주기가 짧아지게 되고 그만큼 생산성이 떨어지게 된다.On the other hand, referring to FIG. 2, which is an enlarged cross-sectional view of the line 2-2 of FIG. 1, it can be seen that the edge ring 3 is slightly higher in height than the chuck 1. In addition, there is a slight gap between the chuck 1, the edge ring 3 and the focus ring 5 so that the edge ring 3 can flow slightly when the wafer 11 is placed on the chuck 1. It is. By the way, as shown in FIG. 2, the conventional processing chamber has an edge of the edge ring 3 at a right angle so that the wafer 11 is not placed exactly on the chuck 1 and thus over the edge ring 3. If an incorrectly aligned wafer is subjected to etching or deposition, the result of etching or deposition may be non-uniform, or may cause a defect that is not processed on the peripheral portion of the wafer 11 that is out of the chuck 1. In addition, a process gas or by-products, etc. adhere to the surface of the edge ring 3 or between the chuck 1 and the edge ring 3 to become a source of contamination. It is discharged, and a predetermined number of wafers are processed, and then the inside of the chamber is periodically cleaned and removed. However, since the edges of the edge ring 3 are at right angles as shown in FIG. 2, the contaminants attached to the edges of the edge ring 3 are not easily discharged by the exhaust pump. Therefore, the chamber cleaning cycle is shortened and the productivity decreases accordingly.

본 발명은 상기의 문제점을 해결하기 위한 것으로, 웨이퍼가 척 위에 정확하게 정렬될 수 있도록 하고 오염 물질의 배출이 용이한 구조의 반도체 처리 챔버를 제공하는 데에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor processing chamber having a structure that allows a wafer to be accurately aligned on a chuck and facilitates the discharge of contaminants.

도 1은 통상의 반도체 처리 챔버의 하부를 도시한 평면도이다.1 is a plan view showing a lower portion of a conventional semiconductor processing chamber.

도 2는 종래의 처리 챔버에 대한 도 1의 2-2선 확대단면도이다.2 is an enlarged cross-sectional view taken along line 2-2 of FIG. 1 for a conventional processing chamber.

도 3은 본 발명의 일실시예에 따른 처리 챔버에 대한 도 1의 2-2선 확대단면도이다.3 is an enlarged cross-sectional view taken along line 2-2 of FIG. 1 for a processing chamber in accordance with one embodiment of the present invention.

도 4는 본 발명의 다른 실시예에 따른 처리 챔버에 대한 도 1의 2-2선 확대단면도이다.4 is an enlarged cross-sectional view taken along line 2-2 of FIG. 1 for a processing chamber according to another embodiment of the present invention.

상기의 목적을 달성하기 위하여 본 발명의 반도체 처리 챔버는, 웨이퍼가 놓이는 척과, 이 척의 둘레에 링 형태로 설치되어 웨이퍼를 안내하는 에지 링을 가지는 반도체 처리 챔버로서, 상기 척과 면하는 상기 에지 링의 안쪽 상부 모서리가 둥글게 라운드 처리된 것을 특징으로 한다.In order to achieve the above object, the semiconductor processing chamber of the present invention is a semiconductor processing chamber having a chuck on which a wafer is placed and an edge ring installed around the chuck in a ring shape to guide the wafer. Inner upper corner is rounded.

또한, 상기 에지 링의 안쪽 상부 모서리는 라운드 처리 대신에 소정 각도로 깎아서 경사지게 할 수도 있다.In addition, the inner upper edge of the edge ring may be inclined at an angle instead of rounding.

이렇듯 본 발명에 따른 반도체 처리 챔버의 에지 링은 그 모서리가 수직하게 이루어졌던 종래와는 달리 둥글게 라운드 처리되거나 소정 각도로 경사지게 됨으로써, 웨이퍼가 척 위에 정확하게 정렬될 수 있고 오염 물질의 제거가 용이하게 된다.As described above, the edge ring of the semiconductor processing chamber according to the present invention is rounded or inclined at a predetermined angle, unlike the conventional case in which the edge is vertical, so that the wafer can be accurately aligned on the chuck and removal of contaminants is easy. .

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 따른 반도체 처리 챔버에 대하여 상세히 설명한다. 이하에서 본 발명의 특징부인 에지 링을 제외한 나머지 구성요소에 대해서는 종래의 처리 챔버에서와 동일하므로 그 상세한 설명을 생략한다. 또한, 에지 링의 구조를 제외한, 에지 링이나 나머지 구성요소의 재질 등도 역시 종래의 처리 챔버에서와 동일하므로 그 상세한 설명을 생략한다.Hereinafter, a semiconductor processing chamber according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following, the rest of the components except for the edge ring, which is a feature of the present invention, are the same as in the conventional processing chamber, and thus detailed description thereof is omitted. In addition, except for the structure of the edge ring, the material of the edge ring, the remaining components, etc. are also the same as in the conventional processing chamber, and thus detailed description thereof is omitted.

도 3은 본 발명의 일실시예에 따른 하부구조가 개선된 반도체 처리 챔버의 도 1에서의 2-2선 단면도이다.3 is a cross-sectional view taken along line 2-2 in FIG. 1 of a semiconductor processing chamber having an improved underlying structure in accordance with one embodiment of the present invention.

도 3을 참조하면, 본 실시예의 처리 챔버의 하부구조는 종래와 마찬가지로 기본적으로 척(1), 에지 링(3'), 포커스 링(5)을 구비한다. 그런데, 본 실시예에서의 에지 링(3')은 종래와 달리 척(1)과 면하는 안쪽 상부 모서리가 둥글게 라운드 처리되어 있다.Referring to FIG. 3, the substructure of the processing chamber of the present embodiment basically includes a chuck 1, an edge ring 3 'and a focus ring 5 as in the prior art. By the way, the edge ring 3 'in this embodiment has a rounded inner top edge facing the chuck 1, unlike the prior art.

따라서, 설령 웨이퍼(11)가 척(1) 위에 정확히 정렬되어 놓이지 않더라도 에지 링(3')에 그 모서리가 걸치는 일이 없고, 라운드 처리된 에지 링(3')의 모서리를 따라 미끄러져 내려가므로 척(1) 위에 정확히 안착할 수 있다. 또한, 척(1)과 에지 링(3')의 사이나 에지 링(3')의 모서리에 부착되는 오염 물질도, 에지 링(3')의 모서리가 수직이 아니라 둥글게 되어 있으므로, 배기펌프의 펌핑작용에 의해 쉽게 배출구(9)로 빨려 들어가게 된다. 그리고, 처리 중에 (척(1)을 포함하여) 에지 링(3')을 회전시키는 경우에도 오염 물질이 원심력 만으로도 쉽게 바깥 방향으로 배출될 수 있게 된다.Therefore, even if the wafer 11 is not exactly aligned on the chuck 1, the edge does not extend to the edge ring 3 ′ and slides down along the edge of the rounded edge ring 3 ′. It can be seated exactly on the chuck 1. In addition, the contaminants adhering between the chuck 1 and the edge ring 3 'or at the edge of the edge ring 3' also have rounded corners of the edge ring 3 'rather than vertically. It is easily sucked into the outlet 9 by the pumping action. In addition, even when the edge ring 3 '(including the chuck 1) is rotated during processing, the contaminants can be easily discharged outward only by the centrifugal force.

한편, 이러한 본 실시예에 따른 반도체 처리 챔버의 효과는, 도 3의 에지 링(3')처럼 그 모서리가 반드시 둥글게 라운드 처리되어 있어야 얻어지는 것은 아니다. 즉, 도 4에 도시된 본 발명의 다른 실시예에 따른 반도체 처리 챔버처럼, 에지 링(3")의 안쪽 상부 모서리를 소정의 각도로 깎아서 경사지게 하더라도 얻어질 수 있다. 이때, 경사진 각도는 30°내지 60°안팎의 범위에서 웨이퍼가 미끄러져 내려올 수 있으면서 오염 물질이 에지 링(3")의 바깥 방향으로 배출될 수 있도록 적절하게 조절할 수 있다.On the other hand, the effect of the semiconductor processing chamber according to the present embodiment is not obtained by rounding the corners like the edge ring 3 'of FIG. That is, like the semiconductor processing chamber according to another embodiment of the present invention shown in Fig. 4, it can be obtained even if the inner upper edge of the edge ring 3 "is shaved and inclined at a predetermined angle. In this case, the inclined angle is 30 The wafer can slide down within a range of between < RTI ID = 0.0 > 60 < / RTI >

이상 상술한 바와 같이 본 발명의 반도체 처리 챔버에 의하면, 그 에지 링의 안쪽 상부 모서리를 라운드 처리하거나 소정 각도로 경사지게 함으로써, 웨이퍼가 척 위에 정확히 안착하게 할 수 있고, 에지 링의 모서리 부분에 부착하는 오염 물질의 배출을 용이하게 할 수 있다. 따라서, 웨이퍼에 대한 식각이나 증착 등의 공정 결과가 균일하게 되고, 처리 챔버의 청소 주기를 길게 할 수 있어 생산성이 향상되는 효과가 있다.As described above, according to the semiconductor processing chamber of the present invention, the inner upper edge of the edge ring is rounded or inclined at a predetermined angle so that the wafer can be accurately seated on the chuck, It can facilitate the discharge of pollutants. Therefore, the process result, such as etching or vapor deposition to a wafer, becomes uniform, and the cleaning period of a process chamber can be lengthened and productivity improves.

Claims (2)

웨이퍼가 놓이는 척과, 이 척의 둘레에 링 형태로 설치되어 웨이퍼를 안내하는 에지 링을 가지는 반도체 처리 챔버에 있어서,A semiconductor processing chamber having a chuck on which a wafer is placed and an edge ring disposed around the chuck in a ring shape to guide the wafer. 상기 척과 면하는 상기 에지 링의 안쪽 상부 모서리가 둥글게 라운드 처리되거나 소정의 각도로 깎여서 경사진 것을 특징으로 하는 반도체 처리 챔버.And the inner upper edge of the edge ring facing the chuck is rounded or inclined at a predetermined angle. 제1항에 있어서, 상기 에지 링의 안쪽 상부 모서리가 소정의 각도로 깎여서 경사진 경우, 상기 소정의 각도는 30°내지 60°인 것을 특징으로 하는 반도체 처리 챔버.The semiconductor processing chamber of claim 1, wherein when the inner upper edge of the edge ring is inclined at a predetermined angle, the predetermined angle is 30 ° to 60 °.
KR1019990012032A 1999-04-07 1999-04-07 A Semiconductor Processing Chamber Improved in a Lower Structure KR20000065606A (en)

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KR1019990012032A KR20000065606A (en) 1999-04-07 1999-04-07 A Semiconductor Processing Chamber Improved in a Lower Structure

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8419891B2 (en) 2006-02-16 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor development apparatus and method using same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8419891B2 (en) 2006-02-16 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor development apparatus and method using same
US8834672B2 (en) 2006-02-16 2014-09-16 Samsung Electronics Co., Ltd. Semiconductor development apparatus and method using same

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