KR20000062252A - Semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

A plug electrode 11 made of titanium nitride is provided on the active region or the gate electrode of the semiconductor substrate, the opening of the accumulation electrode 15 of the capacitor formed by stacking is reduced, and the line width of the wiring electrode 13 is reduced. By reducing the size, the margin with the wiring electrode 11 is secured at the connecting portion of the storage electrode 15, and the required area of the memory cell is reduced. In addition, the plug electrodes are commonly used in the CMISFET section of the peripheral circuit and the memory cell of the static RAM to make each layout compact.

Description

Semiconductor memory device and manufacturing method therefor {SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

For example, a dynamic random access memory (hereinafter referred to as a dynamic RAM) is a unit of a charge storage capacitor for storing information and a memory cell in which a write read switch transistor is connected to the capacitor. As such, since the number of elements of one memory cell is small, it is generally widely used as a main memory device of a computer device requiring a large capacity.

In order to increase the storage capacity of such a dynamic RAM, it is necessary to miniaturize the memory cell area to improve the density of the memory cells.

In this process, however, as the area of the memory cell decreases, the effective area of the charge storage capacitor of the memory cell decreases, and the storage capacity decreases, so that the information of the memory cell generated by the decrease of the S / N ratio or the α-ray irradiation is generated. A so-called soft error phenomenon, called inversion, appears, which is a big problem in reliability.

For this reason, several methods have been devised so far as a memory cell structure in which a large storage capacity is obtained without increasing the memory cell occupation area. One of them is a memory cell having a stacked (stacked) capacitor consisting of a three-dimensional capacitor using a vertical surface with a capacitor electrode, such as a crown-type capacitor. Memory cells of this kind are disclosed in, for example, Japanese Patent Laid-Open Nos. 62-48062 and 62-128168.

In addition, memory cells of 1 Gigabit dynamic RAM are described in IEEE Int., Electron Devices Meeting, Technical Digest, pp. 927-929, Dec. (1994).

45 shows a dynamic RAM considered by the inventors and the like from the memory cell structure disclosed in the above-mentioned document. Hereinafter, the configuration of the dynamic RAM and its problems will be described with reference to FIG.

In Fig. 45, the switching transistor of the memory cell (hereinafter, the most common MISFET is used) is composed of a gate insulating film 403, a gate electrode 404, and high concentration n-type impurity regions 407 and 408 serving as a source or a drain. Polycrystalline silicon plugs 410 penetrating the silicon oxide film 409 are formed in the high concentration n-type impurity regions 407 and 408. In addition, an opening is formed in the insulating film 412 on the polycrystalline silicon plug 410, and the data line (wiring electrode) 413 formed on the insulating film 412 through the polycrystalline silicon plug 410 has a high concentration n-type impurity region ( 407 is electrically connected. The insulating film 412 on the polycrystalline silicon plug 410 formed on the high concentration n-type impurity region 408 in the gap between the data line (wiring electrode) 413 and the word line (gate electrode) 404, and the insulating film 412. A common opening is formed in the silicon oxide film 414 on the upper surface of the silicon oxide film 414, and the storage electrode 415 of the crown capacitor formed of the polycrystalline silicon through the opening and the polycrystalline silicon plug 410 has a high concentration n-type impurity region 408. Is electrically connected).

In addition, a capacitor dielectric film 416 is deposited on the storage electrode 415, and a plate electrode 417 is provided thereon. An aluminum wiring 419 is formed on the silicon oxide film 418 on the memory cell, and is used as a cell selection line or word bus.

However, in a memory cell having a capacitor provided on the data line as described above, particularly in a highly integrated memory cell, the connection portion of the data line (wiring electrode) 413 and the capacitor electrode 415 is disposed very close to each other. Therefore, it is difficult to ensure sufficient electrical insulation between the data line and the capacitor electrode by the mask alignment shift during manufacture and the dimensional shift (side etching) in the dry etching for forming the openings in the insulating film 414. . In addition, it is difficult to secure a margin enough for the data lines to cover the openings even in the overlapping portions of the data lines with the openings of the insulating film 412. As a result of the mask alignment shift or the dimensional shift during dry etching (side etching), The dry etching of the wiring electrode 413 serving as the data line causes a problem that the polycrystalline silicon plug 410 is exposed in the opening, and the polycrystalline silicon plug is deeply etched.

In addition, the peripheral circuits directly connected to the memory cell array, such as the sense amplifier, also need to be arranged at the same or twice the repetition pitch as the memory cells. The area occupied by the circuits also needed to be reduced. However, also in the peripheral circuit, there is a problem similar to the above-described memory cell in order to reduce the occupied area of the MISFET constituting the peripheral circuit and to increase the density of the wiring.

In addition, since a three-dimensional capacitor having a high height is used for the memory cell, when the large elevation difference generated in the memory cell portion and the peripheral circuit portion is flattened, the contact hole in the peripheral circuit portion becomes deep and the wiring of the peripheral circuit is disconnected. Occurs.

In order to solve this problem, it is effective to use the same polycrystalline silicon plug as the memory cell for the contact portion of the peripheral circuit. Conventionally, doped polysilicon is used to form the polycrystalline silicon plug, and a polycrystalline silicon plug made of the doped polysilicon may be used for a memory cell formed of a single conductive transistor.

However, in general, a polycrystalline silicon plug using polysilicon doped with a single conductivity type cannot be applied to a peripheral circuit in which another conductivity type transistor is used, and it is difficult to reduce the area of the peripheral circuit.

On the other hand, as the plug material described above, tungsten deposited by chemical vapor deposition (CVD) is also known. In this case, since tungsten serves as a diffusion barrier for impurities, it can be used for peripheral circuits of other conductive types, but tungsten is heat resistant. The problem of this low and heat-reacting with silicon by 600 degreeC or more became clear.

In addition, even in a static random access memory cell (hereinafter, referred to as a static RAM) cell composed of other conductive transistors formed on the main surface of a silicon substrate, the memory cell area can be reduced by the local wiring technique. It did not reach until the wiring layer was constructed.

In addition, in a logic mixed system LSI (semiconductor integrated circuit device) using a high-density dynamic RAM as a core, it is essential to make the memory cell portion and the logic portion as common as possible.

The present invention relates to a semiconductor memory device, for example, a dynamic random access memory or a static random access memory having a three-dimensional capacitor suitable for high integration, and a logical mixed system LSI including these memories as a core.

1 is a cross-sectional view of a semiconductor memory device of the first embodiment of the present invention.

Fig. 2 is a plan view of the semiconductor memory device of the first embodiment of the present invention.

Fig. 3 is an equivalent circuit diagram of the semiconductor memory device of the first embodiment of the present invention.

4 to 10 are cross-sectional views for explaining the manufacturing steps of the semiconductor memory device of the first embodiment of the present invention.

Fig. 11 is a sectional view of the semiconductor memory device of the second embodiment of the present invention.

Fig. 12 is a sectional view of a semiconductor memory device of the second embodiment of the present invention.

Fig. 13 is a sectional view of the semiconductor memory device of the third embodiment of the present invention.

14 to 17 are cross-sectional views for explaining the manufacturing steps of the semiconductor memory device of the third embodiment of the present invention.

Fig. 18 is a sectional view of the semiconductor memory device of the fourth embodiment of the present invention.

19 to 24 are cross-sectional views for explaining the manufacturing steps of the semiconductor memory device of the fourth embodiment of the present invention.

Fig. 25 is a sectional view of a semiconductor memory device according to the fifth embodiment of the present invention.

26 to 31 are cross-sectional views for explaining the manufacturing steps of the semiconductor memory device of the fifth embodiment of the present invention.

32 is an equivalent circuit diagram of a semiconductor memory device of a sixth embodiment of the present invention;

Fig. 33 is a plan view of a semiconductor memory device of the sixth embodiment of the present invention.

Fig. 34 is a plan view of a semiconductor memory device according to the sixth embodiment of the present invention.

Fig. 35 is a sectional view of the semiconductor memory device of the sixth embodiment of the present invention.

Fig. 36 is a plan view of a semiconductor memory device of the seventh embodiment of the present invention.

Fig. 37 is a plan view of a semiconductor memory device of the seventh embodiment of the present invention.

38 is a cross sectional view of a semiconductor memory device according to the seventh embodiment of the present invention;

39 is a plan view of a semiconductor memory device of Embodiment 8 of the present invention;

Fig. 40 is a sectional view of a semiconductor memory device according to the eighth embodiment of the present invention.

Fig. 41 is a plan view of a semiconductor memory device of the ninth embodiment of the present invention.

Fig. 42 is a plan view of a semiconductor memory device of the ninth embodiment of the present invention.

43 is a cross sectional view of a semiconductor memory device considered in accordance with the present invention prior to the present invention.

Fig. 44 is a sectional view of the semiconductor memory device of the first embodiment of the present invention.

45 is a cross sectional view of a semiconductor memory device of the first embodiment of the present invention;

One object of the present invention is to provide a semiconductor memory device having high integration and high reliability, including a memory cell and a peripheral circuit thereof.

Another object of the present invention is to provide a semiconductor memory device having high integration and high reliability, including a memory cell and a complementary transistor constituting a sense amplifier or a logic circuit.

Another object of the present invention is to provide a dynamic RAM having a high-density, static capacitor which can increase the storage capacity.

Another object of the present invention is to provide a static RAM which can reduce the memory cell area.

An object of the present invention is to provide a semiconductor memory device capable of reducing costs by simplifying the manufacturing process.

According to the present invention, in a semiconductor memory device having a memory cell and its peripheral circuits, transistors constituting these memory cells and their peripheral circuits are provided on a main surface of the semiconductor substrate, and a first insulating film is provided on these transistors. A plurality of first conductors (plug electrodes) made of titanium nitride having good covering property penetrating through the insulating film are provided, and a first wiring is provided on a main surface of the first insulating film, and the first wiring and the transistor are connected to each other. It connects using said 1st conductor, It is characterized by the above-mentioned.

According to the present invention, a capacitor and a transistor formed on a main surface of a second insulating film on a first insulating film in a memory cell region are connected by using a second conductor provided to penetrate the first conductor and the second insulating film. It is to be done.

According to the present invention, the diameter of the circumferential portion of the second conductor is smaller than that of the circumferential portion of the first conductor.

According to the present invention, the line width of the first wiring is made thinner than the diameter of the circumferential portion of the first conductor.

Further, according to the present invention, the n-channel transistor and the p-channel transistor constituting the complementary transistor are electrically connected through the first conductor.

According to the present invention, the first conductor made of titanium nitride is effective as an etching stopper for dry etching of the first wiring because the difference in the etching ratio of both can be effectively utilized by using a material suitable for the first wiring. It works.

Therefore, even if the first wiring connected to the first conductor is disposed without completely covering the first conductor exposed on the first insulating film main surface, the first conductor is not deeply etched during the dry etching of the first wiring. .

In addition, since the diameter of the circumferential portion of the second conductor and the line width of the first wiring are narrow, the second conductor and the first wiring do not contact each other.

Therefore, even if the area of the memory cell is reduced, the capacitor and the data line do not short-circuit. Furthermore, since the capacitor is located above the data line, the required area of the capacitor can be maximized in the memory cell.

In addition, since the titanium nitride is a barrier against the diffusion of impurities, the first conductor is used to connect the n-channel transistor and the p-channel transistor in a peripheral circuit element composed of a complementary transistor or a static RAM cell. Therefore, the required area of the peripheral circuit or the memory cell can be reduced.

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail using an Example.

<Example 1>

An embodiment of a dynamic RAM according to the present invention will be described with reference to FIGS. 1 to 10. 1 is a cross-sectional view of a memory cell and a cross-sectional view of a MISFET portion of a peripheral circuit on the same drawing, and FIG. 2 is a plan view of the memory cell. The cross section of the memory cell portion of FIG. 1 corresponds to a part of the cross section along the line X-X 'in FIG.

In Fig. 1, the MISFET in the memory cell is composed of the gate insulating film 3, the gate electrode 4, and the high concentration n-type impurity regions 7 and 8 of the source and drain, and the MISFET in the peripheral circuit includes the gate insulating film 3, The gate electrode 4 and the high concentration p-type impurity region 9 of the source and drain are formed. Usually, complementary MISFETs (CMISFETs, more specifically CMOSFETs) are used for peripheral circuits. The present invention is also described on the premise of n-channel and p-channel transistors as peripheral circuit elements, but the portions of the p-channel transistors will be described.

Plug electrodes 11 made of titanium nitride are commonly provided on the high concentration n-type impurity regions 7 and 8 of the memory cell and the high concentration p-type impurity region 9 of the peripheral circuit. The wiring electrode 13 is connected as a data line to a plug electrode on the high concentration n-type impurity region 7 of the memory cell, and a storage electrode (lower electrode) 15 of a capacitor having a crown shape is provided thereon. The storage electrode 15 is connected to the plug electrode 11 on the high concentration n-type impurity region 8 and electrically connected to the MISFET. An opening smaller than the diameter of the plug electrode 11 is formed in the silicon oxide film 14 serving as the interlayer insulating film, and the accumulation electrode 15 and the plug electrode 11 are connected through the opening. In addition, a capacitor dielectric film 16 is deposited on the storage electrode 15, and a plate electrode 17 of the capacitor is provided on the capacitor dielectric film 16 to form a crown capacitor.

On the other hand, in the peripheral circuit, the plug electrode 11 is formed on both the high concentration p-type impurity region 9 and the gate electrode 4 of the source / drain of the MISFET. In addition, as shown in FIG. 1, a common plug electrode 11 may be provided on the gate electrode 4 and the high concentration p-type impurity region 9. In addition, as described above, the MISFET may be an n channel or a p channel, and the conductivity type of the gate electrode may be an n type or a p type. Moreover, the wiring electrode 13 can also be connected to the plug electrode 11 of the said peripheral circuit, and can be used as wiring of a peripheral circuit.

Next, as a plan view of the memory cell shown in FIG. 2, the planar positional relationship of MISFETs and capacitors in the memory cell will be described. In the same figure, the word line 21 is composed of the common gate electrode 4 (FIG. 1) of the MISFET, and the data line 23 is composed of the wiring electrode 13 (FIG. 1). The word line 21 is arranged in the Y direction and the data line 23 is arranged in the X direction, and a crown-shaped capacitor 25 (accumulation electrode 15) is formed above these word lines and data lines. The capacitor 25 is connected to the plug electrode 11 on the active region (T-type region) 20 in the gap between these word lines and the data line through the opening 24. Here, the data line 23 does not have to be provided with a redundancy in the opening 22, and as shown in Fig. 2, the data line 23 has a so-called dog bone shape.

The structure without the dog bone shape described above can be exactly the same in the peripheral circuit. For example, although a latch type sense amplifier of a dynamic RAM is shown in FIG. 3, the present invention shown in FIG. 1 also applies to a flip-flop circuit or the like formed by cross-connecting an inverter composed of a pair of CMISFETs used in the sense amplifier. Can be used effectively. In the same figure, the sense amplifier represents a repeating unit, and data pairs connected to adjacent memory cells are divided into data pairs D1 and D1B and data pairs D2 and D2B, and each data pair is a data pair select line. ISO1 and ISO2 are separated. Here, the flip-flop circuit is connected to the data pair line and amplifies the signal sensed by the data line by driving the common source line SNL to ground potential and SPL to a power supply voltage. In addition, a switch transistor connected to the input / output signal line I / O is connected to the data pair line, and the input / output of the signal is controlled by the column select line YL.

Next, this Example is demonstrated in more detail using sectional drawing of the manufacturing process shown in FIGS. 4 to 10, the memory cell region and the peripheral circuit region are shown in the same drawing as in FIG. 1.

First, as shown in FIG. 4, isolation (field oxide film) 2 is selectively formed on a silicon substrate 1 having a (100) crystal plane by a known technique. In the active region partitioned by the isolation 2, a MISFET comprising the gate electrode 4, the high concentration n-type impurity regions 7 and 8 and the high concentration P-type impurity region 9 is formed by a known method. The gate length of the MISFET is 0.2 mu m. As isolation, a selective oxidation method (LOCOS), a trench isolation in which a silicon oxide film is embedded in a shallow groove of a silicon substrate can be used. In addition, although n channel is used for the polarity of MISFET here, p channel may be sufficient. In addition, a lightly doped drain (LDD) structure can be used to reduce device degradation due to hot carriers. In addition, in order to use a self-aligned contact here, as shown in the same figure, the silicon nitride films 5 and 6 are provided by the well-known method in the side wall or upper part of the gate electrode 4 as an insulating film.

Subsequently, as shown in FIG. 5, the silicon oxide film 10 containing boron and phosphorus is deposited by a well-known CVD method, and the surface of the silicon oxide film 10 is smoothed by annealing at a temperature of about 800 ° C. . The silicon oxide film 10 can also be planarized by a known chemical mechanical polishing (CMP) method. Next, by photolithography and dry etching of the silicon oxide film, the openings 39 and 40 having a diameter of about 0.2 μm are formed in the silicon oxide film 10. Here, photolithography using an excimer laser is used as photolithography. In addition, it is preferable to provide the silicon nitride film which becomes an etching stopper at the lower part of the silicon oxide film 10 at the time of dry etching, and to form the said opening part by self-alignment with respect to an isolation region. In addition, it is preferable to use separate photolithography and dry etching for the opening 40 including the gate electrode. Moreover, when using the said etching stopper, both the dry etching of a silicon oxide film and the dry etching of a silicon nitride film are used.

Subsequently, as illustrated in FIG. 6, the titanium nitride film TiN is deposited to a thickness of about 300 nm by a known CVD technique, and the openings 39 and 40 are etched back by anisotropic dry etching. ), A plug electrode (titanium nitride plug) 11 made of titanium nitride (TiN) is formed. In this case, the titanium nitride film and the silicon oxide film 10 may be polished by the CMP technique to simultaneously planarize and form the plug electrode. In addition to titanium nitride, a heat resistant barrier material such as titanium tungsten (W) can also be used.

Subsequently, as shown in FIG. 7, a silicon nitride film 12 having a thickness of about 50 nm is deposited by the LPCV method, and the openings 22 (FIG. 2) are formed by photolithography and dry etching, and the CVD method is used. As a wiring electrode 13, tungsten is deposited to a thickness of about 100 nm, and patterned by photolithography and dry etching. As the material of the wiring electrode 13, a composite film of a high melting point metal other than tungsten, a silicide film of a high melting point metal, and a polycrystalline silicon film can also be used.

Subsequently, as shown in FIG. 8, the silicon oxide film 14 having a thickness of about 0.5 to 1 m is deposited at a temperature of about 400 ° C. by a CVD method using a known TEOS (tetra ethoxy silane) gas. Is planarized using a known CMP method. In addition, an opening 25 is formed in the silicon oxide film 14 and the silicon nitride film 12 using lithography and dry etching by electron beam. Here, the diameter of the opening is usually about 0.1 mu m.

Subsequently, as shown in Fig. 9, a first polycrystalline silicon film to which n-type impurities are added at a high concentration is deposited to a thickness of about 100 nm by a known LPCVD method (not shown). At this time, the polycrystalline silicon film is also embedded in the opening 25. Although not shown in the figure, a silicon oxide film having a thickness of about 500 nm is deposited and patterned into a pattern of the accumulation electrode by photolithography and dry etching, and further, the second polycrystalline silicon film is deposited with good step coverage by LPCVD. The first and second polycrystalline silicon films are etched by anisotropic dry etching, the silicon oxide film having a thickness of about 500 nm is removed, and a crown-shaped accumulation electrode 15 is formed. Moreover, when removing the said silicon oxide film, it is preferable to provide a silicon nitride film under the silicon oxide film.

Subsequently, as shown in FIG. 10, a capacitor dielectric film 16 having a higher relative dielectric constant than a silicon oxide film such as a tantalum pentoxide (Ta ₂ O ₅ ) film is deposited. At this time, as the deposition method, a CVD method having good step coverage is used. In addition, the oxide film conversion film thickness of the capacitor dielectric film is preferably 3 nm or less in a large-capacity dynamic RAM of 1 gigabit class. Although a polycrystalline silicon film is used here as the storage electrode 15, a high melting point metal film such as tungsten or titanium nitride film may be used. In this case, the influence of the natural oxide film on the surface of the polycrystalline silicon film can be eliminated, and the thickness of the oxide converted film of the capacitor dielectric film can be reduced. As the material of the capacitor dielectric film, in addition to the composite film of silicon nitride and silicon oxide film, a well-known high-k dielectric film such as an SrTiO ₃ film, a (Ba, Sr) TiO ₃ film (BST film), or a ferroelectric film such as a PZT film is used. It can also be used. Subsequently, a high melting point metal film such as tungsten or titanium nitride, which is about 300 nm thick, is deposited, and the plate electrode 17 (upper electrode) of the capacitor is formed by photolithography and dry etching. As the deposition method of the plate electrode material, the CVD method having good step coverage is preferable.

Subsequently, a silicon oxide film 18 having a thickness of about 200 nm is deposited as an interlayer insulating film, and openings are formed in the silicon oxide films 14 and 18 on the metal wiring 13 of the peripheral circuit portion, and then the metal wiring 19 is formed. The semiconductor device of the present invention shown in Fig. 1 is completed. The metal wiring 19 is preferably a low resistance metal such as aluminum, and can be used as the wiring in the memory cell array as shown in FIG. In addition, when forming the metal wiring 21, a well-known plug technique or CMP method can also be applied for planarization of an interlayer insulation film.

In addition, by making the surface of the polycrystalline silicon, which is the storage electrode 15 of the above embodiment, an uneven shape, the surface area of the storage electrode can be increased to obtain a larger storage capacity. In this embodiment, titanium nitride is used as the plug electrode, but titanium tungsten (TiW) may be used, and a material having a low etching rate with respect to dry etching of the wiring electrode 13 and a material serving as a diffusion barrier of impurities. You can also use other ingredients.

In addition, as shown in FIG. 44, titanium (Ti) 146 is laid on the lower portion of the plug electrode 11, and titanium silicide (TiSi ₂ ; 147) is formed at the interface with the silicon substrate to form a high concentration impurity region (7, It is possible to prevent an increase in contact resistance with 8 and 9).

In addition, as shown in FIG. 45, a polycrystalline silicon plug 248 may be used on the heavily doped impurity region 8 of the storage node to which the capacitor is connected. In this case, since titanium nitride and titanium silicide do not directly contact a high concentration impurity region of the storage node, the junction leakage current can be reduced.

According to the present embodiment, since the plug electrode connecting the data line and the high concentration n-type impurity region is made of titanium nitride, it is not etched even when the base plug electrode is exposed when dry etching the data line material. The covering allowance of the opening for connecting the line and the data line can be reduced.

In addition, since the accumulation electrode of the capacitor passes through the plug electrode once without directly connecting to the silicon substrate, at the time of forming the opening for connecting the accumulation electrode, the etching amount of the dry etching is small, and the side etching due to the dry etching is caused by the side etching. The expansion of the opening can be reduced. As a result, the short margin between the storage electrode and the data line increases. In addition, in the portion of the plug electrode to which the accumulation electrode is connected, the diameter of the opening for connecting the accumulation electrode is smaller than the diameter of the plug electrode, so that the short margin of the accumulation electrode and the data line becomes larger.

In addition, since the plug electrode can be used not only for the n-channel MISFET of the memory cell or the peripheral circuit but also for the p-channel MISFET, the required area of the peripheral circuit such as the sense amplifier can be reduced without increasing the manufacturing process.

Further, as stated above, when dry etching the data line material, even if the underlying plug electrode is exposed, it is not etched, so there is no problem even if the line width of the data line is reduced. Therefore, in order to connect a data line and a storage electrode by this, the short margin of an opening part can be enlarged. Specifically, a photoresist is provided on the wiring electrode 13 in the peripheral circuit portion, and the wiring electrode 13 in the memory cell region is side etched by isotropic dry etching. As a result, the film thickness of the wiring electrode 13 of the memory cell can be made thin at the same time, and the film thickness of the wiring electrode 13 of the peripheral circuit portion can be made thick, so that the depth of the opening of the storage electrode in the memory cell can be made shallow. It can be made easily. Moreover, you may reduce the dimension of the mask itself of dry etching to below a minimum process dimension by side etching the mask material used when dry-etching the wiring electrode 13.

<Example 2>

This embodiment uses a capacitor having a structure different from that of the first embodiment with respect to the dynamic RAM in the first embodiment with reference to FIGS. 11 and 12.

First, FIG. 11 is a sectional view of the dynamic RAM according to the present embodiment. In the same figure, the accumulation electrode 26 (lower electrode) of the capacitor is formed of a thick polycrystalline silicon film whose film thickness is usually 500 nm. In other words, the accumulation electrode was only patterned in the shape of the accumulation electrode after the polycrystalline silicon film was deposited. According to the present embodiment, the thickness of the polycrystalline silicon is increased to increase the storage capacity by using the vertical component of the sidewalls of the polycrystalline silicon, which has the same effect as the crown capacitor described in the first embodiment.

The structure other than the storage electrode is the same as that of the first embodiment, and the storage electrode 26 is made of titanium nitride formed on the high concentration n-type impurity region 8 of the MISFET through the opening of the silicon oxide film 14. It is connected to the plug electrode 11. In the capacitor dielectric film 27, a high dielectric film such as tantar pentoxide and the like is used as in the first embodiment.

12 is a cross-sectional view of a dynamic RAM different from FIG. 11. In the same figure, the accumulation electrode 30 is usually formed of a platinum film having a thickness of 100 nm. Further, a capacitor dielectric film 31 composed of a (Ba, Sr) TiO ₃ film having a thickness of about 30 nm is formed on the storage electrode 30. In addition, a plug electrode 29 penetrating the silicon oxide film 14 is formed in the silicon oxide film 14 on the wiring electrode 13. Therefore, the accumulation electrode 30 is connected to the plug electrode 11 and electrically connected to the MISFET once through the plug electrode 29. When the accumulation electrode is formed, the accumulation electrode 30 may be deposited by a CVD method having good step coverage. Unusable electrode materials can also be used.

In the present embodiment, titanium nitride is preferably used as the material of the plug electrode 29 in the same way as the plug electrode 11, so that even if an accumulation electrode made of platinum is connected to the upper portion, reaction occurs between them. There will be no.

In this embodiment, since a capacitor dielectric film having a high dielectric constant is used, a sufficient storage capacity can be ensured even without forming a three-dimensional capacitor using the sidewalls of the storage electrodes as described above.

In addition, since the thickness of the storage electrode is thin, the sputtering method can be used to form the capacitor dielectric film 31, and the dielectric film can be easily manufactured.

As described above, the structure of the capacitors described in the two embodiments is simpler than the crown capacitor of the first embodiment. Thus, it can be seen that the present invention can be applied regardless of the structure of the capacitor.

In addition, in the above-described high dielectric constant capacitor dielectric film, high temperature annealing of about 750 ° C is required for crystallization, but in the present invention, since the connection to the substrate silicon uses a plug electrode made of titanium nitride, the connection portion There is no such thing as reaction with silicon.

In addition, the structure of the plug electrode 29 shown in FIG. 12 of this embodiment is applicable also to the crown capacitor of Example 1, or another Example.

<Example 3>

This embodiment relates to a method of connecting the dynamic RAM, in particular the accumulation electrode, in the first embodiment. FIG. 13 is a cross-sectional view of the dynamic RAM of the present embodiment, which shows a method of reducing the opening of the silicon oxide film 14 when the capacitor accumulation electrode 15 is connected to the plug electrode 11. In the same figure, except that the opening of the silicon oxide film 14 is the same as that of Fig. 1 of the first embodiment, a plug electrode of titanium nitride is provided on the high concentration n-type impurity of the MISFET formed on the silicon substrate, and on top of the data line A crown capacitor is formed through the silicon oxide film 14. In the opening formed in the silicon oxide film 14, the size of the opening is reduced by the spacer insulating film 33 on the sidewall of the opening. The accumulating electrode 16 of the capacitor is connected to the plug electrode 11 through the opening in which the opening is reduced in this way.

Next, the manufacturing process of this embodiment is demonstrated using FIGS. 14-17.

First, as shown in FIG. 14, the steps up to forming the MISFET and the data line on the silicon substrate are the same as those in FIG. Subsequently, a silicon oxide film 14 is deposited on the wiring electrode 13, and an opening having a diameter of about 0.2 μm is formed in the silicon oxide film 14 by photolithography and dry etching. 0.2 μm is the minimum processing dimension of photolithography.

Subsequently, as shown in FIG. 16, a silicon nitride film having a thickness of about 50 nm is deposited by LPCVD, and a silicon nitride film is formed on the sidewall of the opening with good coating properties. Then, the spacer insulating film 33 is formed on the sidewall of the silicon oxide film 14 in the opening by etching back the flat portion of the silicon nitride film deposited by the anisotropic dry etching. After the spacer insulating film 33 is formed, the silicon nitride film 12 in the lower layer may also be etched by over etching to form an opening leading to the plug electrode 11. By this process, the opening of the silicon oxide film 14 is about 0.1 mu m in diameter.

Subsequently, as shown in FIG. 17, a polycrystalline silicon film serving as a storage electrode is deposited, and a crown-shaped storage electrode 15 is formed as in Example 1, and a capacitor dielectric film 16 and a plate electrode 17 are formed. do.

According to this embodiment, the silicon oxide film 14 on the wiring electrode 13 serving as the data line can be formed with an opening having a diameter smaller than or equal to the minimum dimension, so that the gap between the data line and the opening can be reduced, The short margin of the data line increases. In addition, in the present embodiment, a crown-shaped capacitor has been described as an example, but the present invention can also be applied to the capacitor structure described in Embodiment 2 or other known capacitor structures.

<Example 4>

This embodiment relates to a method of reducing the line width of a dynamic RAM, in particular, a data line, in the first embodiment. 18 is a sectional view of the dynamic RAM of the present embodiment.

In the drawing, the wiring electrode 37 serving as a data line is embedded in an opening formed in the silicon oxide film 35, and a spacer insulating film 36 made of a silicon nitride film is formed in the opening, and the line width of the wiring electrode 37 is equal to the above. It is determined by the spacer insulating film 36. The crown-shaped capacitor storage electrode 15 is formed on the silicon oxide film 38 on the wiring electrode 37 and the silicon oxide film 35, and is formed in the silicon oxide films 38 and 35 and the silicon nitride film 12 in common. The accumulation electrode 15 is connected to the plug electrode 11 via the opening of the plug electrode 11.

Next, this Example is demonstrated in more detail using sectional drawing of the manufacturing process shown in FIGS. 19-24.

First, as shown in FIG. 19, the manufacturing process until the formation of the MISFET and the plug electrode 11 on the silicon substrate is the same as that in FIG. 6 of the first embodiment, and the silicon nitride film 12 as the etching stopper is subjected to the LPCVD method. By a thickness of about 50 nm.

Subsequently, as shown in FIG. 20, a silicon oxide film 35 having a thickness of about 200 nm is deposited by CVD using TEOS, and a pattern of a wiring electrode is formed on the silicon oxide film 35 by photolithography and dry etching. An opening is formed, and the silicon nitride film 41 having a thickness of about 50 nm is deposited with good step coverage by the LPCVD method. Alternatively, a silicon oxide film may be used instead of the silicon nitride film.

Subsequently, as illustrated in FIG. 21, the silicon nitride films 41 and 12 are etched by anisotropic dry etching to form a spacer insulating film 36 on the sidewall of the silicon oxide film 35 and at the same time, the plug electrode 11. Expose

Subsequently, a tungsten film having a thickness of about 300 nm is deposited as shown in FIG. As the deposition method, the CVD method is preferable. Subsequently, the tungsten film on the silicon oxide film 35 is polished by the CMP method, and tungsten is embedded only in the opening of the silicon oxide film 35. At this time, an extra tungsten film is polished about 50 to 100 nm.

Subsequently, as shown in FIG. 23, the silicon oxide film 38 is deposited to a thickness of about 100 nm, and the openings common to the silicon oxide films 38 and 35 and the silicon nitride film 12 are formed by photolithography and dry etching. 42). Moreover, the effect can be further improved by combining with Example 3 at the time of formation of the said opening part.

Subsequently, as shown in FIG. 24, polycrystalline silicon serving as the storage electrode 15 is deposited to form a crown capacitor as in the first embodiment.

According to this embodiment, since the wiring width of the wiring electrode 37 serving as the data line can be reduced to a dimension smaller than or equal to the minimum dimension, a short margin between the opening for connecting the wiring electrode 37 and the storage electrode 15 is obtained. Can be increased.

In addition, in the present embodiment, a crown-shaped capacitor has been described as an example, but the present invention can also be applied to the capacitor structure described in Embodiment 2 or other known capacitor structures.

The present embodiment can also be applied to a memory cell having a structure not using a plug electrode on a silicon substrate as shown in FIG. 25 or a memory cell having a structure using a plug made of polycrystalline silicon.

In addition, the present invention is not limited to the dynamic RAM, but may be generally used for wiring used in the LSI. In this case, as the material of the wiring electrode 37, aluminum or an equivalent low resistance metal other than heat-resistant high melting point metal can be used.

<Example 5>

This embodiment relates to the microfabrication of a memory cell of a dynamic RAM, in particular a platinum electrode, using platinum as a capacitor electrode of a capacitor. Fig. 26 shows a manufacturing process of the dynamic RAM according to the present embodiment, in which platinum is used as a capacitor electrode of a capacitor in order to use a high-k dielectric BST film or a ferroelectric PZT film.

First, as shown in FIG. 26, the manufacturing process until the MISFET is formed on the silicon substrate and the plug electrode 11 and the wiring electrode 13 are formed is the same as the process up to FIG. 7 of the first embodiment. .

Subsequently, as shown in Fig. 27, a silicon oxide film 14 having a thickness of about 0.5 to 1 m is deposited at a temperature of about 400 deg. C by a CVD method using a known TEOS gas, and the surface is subjected to a known CMP method. To planarize. In addition, an opening is formed in the silicon oxide film 14 and the silicon nitride film 12 using photolithography and dry etching, and a titanium nitride film having a thickness of about 200 nm is deposited by CVD, followed by titanium nitride in the flat portion. The film is etched back by anisotropic dry etching to form the plug electrode 29.

Subsequently, as shown in Fig. 28, a platinum film 45 having a thickness of 100 to 300 nm is deposited by the sputtering method, and an amorphous silicon film 43 is deposited to a thickness of about 100 nm on top. The amorphous silicon film 43 is then patterned using photolithography and dry etching.

Then, as shown in FIG. 29, by annealing in a nitrogen atmosphere at a predetermined temperature, the amorphous silicon film 43 and the platinum film 30 are reacted to form a platinum silicide on a portion where the amorphous silicon film 43 is patterned. Form 44. The platinum film 30 in the portion without the amorphous silicon film 43 remains as it is.

Subsequently, as shown in FIG. 30, the platinum silicide 44 is removed by forming wet etching with an aqueous hydrofluoric acid solution to form the platinum electrode 30. Although omitted here, a wet etching stopper may be provided below the platinum film 30.

As shown in FIG. 31, the BST film 31 is deposited on the platinum electrode 30 by sputtering or CVD, and the platinum film 32 is deposited, and by photolithography and dry etching. Pattern. The subsequent manufacturing step may be the same as in Example 1.

According to this embodiment, since the platinum electrode can be processed into a fine pattern without directly etching the platinum film, the capacitor using the platinum film as the storage electrode can be miniaturized.

<Example 6>

This embodiment applies the present invention to a static RAM. FIG. 32 shows an equivalent circuit of a memory cell of a static RAM, in which a flip-flop is formed by cross-connecting a pair of inverters consisting of n-channel MISFETs Q1 and Q2 and p-channel MISFETs Q5 and Q6. Circuit and transfer transistors Q3 and Q4 connected to the flip-flop circuit. 33 and 34 show a plan view of a static RAM having a structure suitable for high integration in which p-channel MISFETs are formed in stacked polycrystalline silicon. 33 shows a portion of a MISFET formed on a silicon substrate, and FIG. 34 shows a portion of a TFT (Thin Film Transistor) formed in a polycrystalline silicon film and a portion of a wiring electrode, respectively.

In Fig. 33, the gate electrode of the driving MISFETs Q1 and Q2 is formed of a memory node consisting of high concentration n-type impurity regions 106 and 107 which are drains, respectively, through the plug electrode 117 of titanium nitride formed in the opening. Is connected to. In addition, plug electrodes 117 made of titanium nitride are formed in the openings in the highly-concentrated n-type impurity regions 108 and 109 serving as the source of the driving MISFET, and the ground wiring 116 is connected. The high concentration n-type impurity regions 106 and 107 in the storage node are also common high concentration impurity regions of the transfer MISFETs Q3 and Q4, and the gate electrodes 110 and 111 of the transfer MISFET are adjacent to each other. It is a common word line of memory cells. In addition, the plug electrodes 117 are formed in the openings in the high concentration n-type impurity regions 104 and 105 of the transfer MISFET, and the wiring electrodes 129 and 130 which become data lines through the openings 127 and 128; 34) is connected.

In addition, the gate electrodes 119 and 120 of the p-channel TFTs Q6 and Q5 serving as load elements are connected to the plug electrode 117 formed in the memory node in FIG. 34 through the openings 140 and 141. Further, drain regions 114 and 115 of the other TFTs are connected to the respective gate electrodes 119 and 120 through the openings 121 and 122. In addition, the source regions 125 and 126 of the TFTs Q5 and Q6 serve as common power wirings of adjacent memory cells.

Next, the present embodiment will be described in more detail using the cross-sectional view of FIG. The same figure is sectional drawing of the XX 'line in the top view of FIG.

The n-channel MISFET of the memory cell is formed on the silicon substrate surface. Plug electrodes 117 are formed on the high concentration n-type impurity regions 104 and 106 and the gate electrode 112. On the silicon oxide film 133, the wiring electrode 116 having the structure described in Embodiment 4 is formed. The material of the wiring electrode 116 is preferably tungsten. The wiring electrode 116 is a ground wiring for supplying a ground potential to the source of the driving MISFET.

The gate electrodes 119 and 120 of the TFT made of a p-type polycrystalline silicon film are formed on the wiring electrode 116 through the silicon oxide film 137. The gate insulating film 138 of the TFT is provided on the gate electrode 120. A channel region 123 of a TFT made of a polycrystalline silicon film, a source region 125 and a drain region 114 to which p-type impurities are added are formed on the gate insulating film 138. Here, the drain region 114 of one TFT is connected to the gate electrode 119 of the other TFT through an opening formed in part of the gate insulating film 138, and cross connection of the flip-flop circuit is achieved. The gate electrode is connected to the plug electrode 117 through an opening having a diameter smaller than that of the plug electrode 117.

According to this embodiment, since the short margin between the ground wiring of the memory cell and the gate electrode of the TFT can be increased, the area of the memory cell of the static RAM can be reduced. Further, since the p-channel TFT and the n-channel MISFET formed on the silicon substrate are connected by a plug electrode made of titanium nitride, an electrical resistance connection is obtained.

<Example 7>

In this embodiment, the present invention is applied to a static RAM in which an n-channel MISFET and a p-channel MISFET are formed on a silicon substrate. 36 and 37 are plan views of the static RAM according to the present embodiment, FIG. 36 shows the MISFET and the local wiring portion, and FIG. 37 shows the portion of the wiring electrode.

In FIG. 36, MISFETs Q1, Q2, Q3, Q4, Q5, and Q6 correspond to the equivalent circuit of FIG. The gate electrode 215 is a common gate electrode of Q1 and Q5. The gate electrode 216 is a common gate electrode of Q2 and Q6. Further, on the high concentration n-type impurity regions 206 and 207 of the n-channel MISFETs Q1, Q2, Q3 and Q4, and on the high concentration p-type impurity regions 210 and 211 of the p-channel MISFETs Q5 and Q6. Plug electrodes 217, 218, 219, 220 are formed. Also, plug electrodes 221 and 222 are formed on the gate electrodes 215 and 216. That is, the cross connection of the flip-flop circuit of the memory cell is formed by the plug electrodes 217, 218, 219, 220, 221, and 222 and local wirings 223 and 224 made of a tungsten film having a thickness of about 100 nm. . The plug electrode is made of titanium nitride, and is formed by the same method as in Example 1, and the height of the plug electrode is about 50 nm to 150 nm.

Further, high concentration n-type impurity regions 204 and 205 of MISFETs Q3 and Q4, high concentration n-type impurity regions 208 and 209 of MISFETs Q1 and Q2, and high concentration P-type impurity regions of MISFETs Q5 and Q6. The metal wirings 231, 232, 233, and 234 of the first layer shown in FIG. 37 are provided through the openings 225, 226, 227, 228, 229, and 230 in the 212 and 213. As shown in FIG. The metal wiring 233 is a ground wiring for feeding power to the sources of the driving MISFETs Q1 and Q2, and the metal wiring 234 is a power wiring for feeding power to the sources of the load MISFETs Q5 and Q6. The data line of the memory cell is formed by the metal wirings 237 and 238 of the second layer. The metal wires 231, 232, 233, 234, 237 and 238 are made of aluminum.

38 is a cross-sectional view of this embodiment. The n-channel MISFET and p-channel MISFET in the memory cell are formed in the p well 244 and n well 245 in the silicon substrate 201, respectively. In this embodiment, as in the first embodiment, silicon nitride films 239 and 240 can be formed on the sidewalls and the upper portions of the gate electrodes of the MISFET, and self-aligning contacts can be formed. In this case, when forming the plug electrode 217 formed on the gate electrode 216, photolithography and dry etching different from other plug electrodes may be used. Although not shown in the figure, the etching stopper of the silicon nitride film is also used for the isolation, thereby having a boundaryless structure.

According to this embodiment, local wiring can be miniaturized and a highly integrated static RAM can be provided.

<Example 8>

This embodiment further develops the static RAM cell of the seventh embodiment, and achieves cross connection of flip-flop circuits by four plug electrodes. 39 is a plan view of the static RAM according to the present embodiment, in which the wiring electrode portions are omitted as in the seventh embodiment. 40 is shown in FIG. 39 and 40, the plug electrode 217 on the high concentration n-type impurity region 206 of the driving MISFET is connected to a local wiring 221 made of tungsten having a thickness of about 100 nm at the top, and the local wiring 221 is It is simultaneously connected by a plug electrode 246 extending on the common gate electrode 216 of the other inverters Q2 and Q6 and onto the high concentration p-type impurity region 210 of the load MISFET Q5. The same applies to the plug electrode 247 of FIG. 39. In addition, the plug electrode is made of titanium nitride, and is formed by the same method as in Example 1.

According to this embodiment, local wiring can be further refined and a high density static RAM can be provided.

<Example 9>

This embodiment relates to another type of memory cell in a static RAM cell according to the present invention. 41 and 42 are plan views of memory cells of the static RAM according to the present embodiment. A part of the MISFET is shown in FIG. 41 and a part of the wiring electrode is shown in FIG. In FIG. 41, the plug electrodes 318, 319, 320, 321, and 322 are connected to each other without cross wiring by flip-flop circuits. These plug electrodes are made of titanium nitride and are formed by the same method as in Example 1. The wiring electrode is made of two layers of aluminum as in the seventh embodiment.

According to this embodiment, the manufacturing process of the static RAM can be simplified.

In the embodiment of the memory cell described above, the required area of the peripheral circuit can be reduced by using the plug electrodes of the common self matching structure as shown in the first embodiment for the peripheral circuits of the static RAM and the dynamic RAM.

In the above-described embodiment, the present invention is applied to a dynamic RAM or a static RAM. However, the present embodiment is applicable to a semiconductor device in which the static RAM and the dynamic RAM are mixed on the same silicon substrate or a semiconductor device in which the memory and the logic are mixed. As a result, the manufacturing cost can be reduced, the data transfer speed can be improved, and the chip area can be reduced.

As described above, according to the present invention, the plug electrode can be used to reduce the area required for the CMISFET of the peripheral circuit as well as the memory cells such as the dynamic RAM and the static RAM. In addition, even when the thermal process required for the formation of the memory cell is applied to the memory cell of the stacked structure in which the element is formed on the MISFET, the electrical characteristics of the connection between the plug electrode and the silicon substrate can be stabilized without being impaired.

Further, the short margin between the element on the top of the MISFET and the wiring layer located in the middle thereof can be increased. Therefore, a semiconductor device having a small chip area can be provided.

Further, according to the present invention, by using a low resistance metal material such as copper as the wiring layer formed on the capacitor in the memory cell region and the wiring layer on the peripheral circuit region, it is possible to provide a semiconductor memory device that can operate at higher speed. Can be.

In the embodiment described above, the present invention is applied to a dynamic RAM and a static RAM.

However, the present invention can be applied to semiconductor integrated circuit devices such as on-chip LSIs in which memory and logic (logic circuits) are mixed. In this case, the wiring layer of a logic part can be formed in the height in which the capacitor is formed. The logic section is constituted by a plurality of CMISFETs. In other words, the logic section consists of COS logic.

Claims (24)

A semiconductor memory device comprising a memory cell region including a first transistor provided on one surface of a semiconductor substrate, and a logic circuit region including a second transistor and a third transistor having different conductivity types. First wirings made of a first metal are formed in the memory cell region and the logic circuit region, respectively, on a main surface of the first insulating film on the first transistor, the second transistor, and the third transistor, The connection between the first wiring and the first, second and third transistors is made by a connecting body including a first conductor provided in an opening passing through the first insulating film. A semiconductor memory device, characterized in that. The method of claim 1, The semiconductor substrate is made of silicon, The property of the first conductor and the first metal is that there is no increase in contact resistance due to the reaction between the first conductor and the silicon, and the etching rate of the first conductor is higher than that of the first metal. A semiconductor memory device characterized in that it is slow. The semiconductor memory device according to claim 1 or 2, wherein the first conductor and the first metal are different high melting point metals. The semiconductor memory device according to any one of claims 1 to 3, wherein said first conductor is titanium nitride or titanium tungsten, and said first metal is tungsten. The semiconductor memory device according to claim 1, wherein the first conductor is connected to the silicon substrate via a silicide layer. The source region, the drain region, and the gate electrode of each of the first transistor, the second transistor, and the third transistor are connected to the first metal by a connector including the first conductor. A semiconductor memory device, characterized in that connected. In a semiconductor memory device in which a memory cell includes a first transistor provided on a main surface of a silicon substrate, and a first wiring made of a first metal is formed through a first insulating film and a second insulating film on the first transistor. A first element is formed on the first wiring through a third insulating film. A connection between the first element and the first transistor is achieved by a connecting body including a first conductor provided in an opening passing through the first insulating film, and a second conductor passing through the second insulating film and the third insulating film. felled A semiconductor memory device, characterized in that. The method of claim 7, wherein The first conductor and the second conductor are substantially cylindrical, The first conductor is electrically insulated from the gate electrode by fourth and fifth insulating layers formed on sidewalls and upper portions of the gate electrode of the first transistor, and a part of the first conductor is a gate electrode of the first transistor. It is disposed so as to overlap the sixth insulating film for phase and element separation, And the average diameter of the second conductor is smaller than the average diameter of the first conductor. The semiconductor memory device according to claim 1, wherein a width of the first wiring is smaller than an average diameter of the first conductor provided in the opening passing through the first insulating film. 8. The semiconductor memory device according to claim 1 or 7, wherein the first wiring is a data line of a dynamic random access memory cell, and the first element is a capacitor of a dynamic random access memory cell. 8. The semiconductor memory device according to claim 7, wherein the first element is a polycrystalline silicon transistor of a static random access memory cell, and the first wiring is a power supply wiring of the static random access memory. 12. The semiconductor device according to claim 11, wherein the first wiring is a local wiring for connecting gate electrodes or source / drain regions of transistors of different conductivity types of the static random access memory cell. A semiconductor device having a memory cell including a first transistor provided on a main surface of a silicon substrate, and a logic circuit including a second transistor and a third transistor having different conductivity types. On the main surface of the first insulating film on the first transistor, the second transistor, and the third transistor, a plurality of first wirings made of a first metal are formed in the memory cell region and the logic circuit region, respectively. The connection between the first wiring and the first, second and third transistors is achieved by a connector including a first conductor passing through the first insulating film, A second insulating film is provided on the first wiring, and a first element is provided on the main surface of the second insulating film of the memory cell region. The connection between the first element and the first transistor is achieved by a connector including a second conductor penetrating the first conductor and the second insulating film. A semiconductor device, characterized in that. The semiconductor device according to claim 13, wherein said second conductor is made of titanium nitride. The method of claim 1, A pair of inverters composed of the second and third transistors, a latch flip-flop circuit composed of the pair of inverters, a pair of signal lines connected to the flip-flop circuit, and the second or the second connected to the pair of signal lines First and second switching transistors consisting of a third transistor, The connecting body which cross-connects one gate and the other drain of each of the pair of inverters includes the first wiring and the first conductor. A semiconductor memory device, characterized in that. In a semiconductor integrated circuit device, wherein a first insulating film is provided on a main surface of a semiconductor substrate, and the first wiring is made of a conductor embedded in a first opening of the first insulating film. Sidewalls of other insulating layers are formed on sidewalls of the first opening of the first insulating layer, and the sidewalls determine a line width of the first wiring. A semiconductor integrated circuit device, characterized in that. The semiconductor integrated circuit device according to claim 16, wherein the first wiring is made of a high melting point metal. 17. The semiconductor integrated circuit device according to claim 16, wherein the cross-sectional shape of the first wiring has an inverted taper shape. 17. The semiconductor integrated circuit device according to claim 16, wherein said fourth insulating film is a silicon nitride film. The method of claim 16, A latch flip-flop circuit comprising a pair of inverters connected to a pair of signal lines in the semiconductor substrate, first and second switch transistors connected to each signal line, first power supply wiring, and second power supply wiring; And control lines connected to the first and second switch transistors, Any one of the signal line, the first or the second power supply wiring, and the first or the second control line includes at least the first wiring. The method of claim 16, On the main surface of the semiconductor substrate, a memory cell comprising one switch transistor and one charge storage capacitor connected to the switch transistor, a word line for selecting the switch transistor, and a data line for reading and writing information Dynamic random access memory is installed, And said data line comprises said first wiring. In the method of manufacturing a semiconductor integrated circuit device, Forming a MISFET in the semiconductor substrate; Depositing a first insulating film; Etching a desired region of the first insulating film and forming a first opening of a wiring pattern; Depositing a sixth insulating film and forming sidewall spacers by the seventh insulating film on the sidewalls of the first opening portions by anisotropic etching; And And a means for embedding a first conductor in said first opening. And a method for manufacturing a semiconductor integrated circuit device. In the method of manufacturing a semiconductor integrated circuit device, Forming a MISFET in the semiconductor substrate; Depositing a first insulating film on the MISFET; Depositing a platinum film on the first insulating film; Depositing amorphous silicon on the platinum film and dry etching a desired portion; Heat-treating to form platinum silicide in a portion where amorphous silicon exists on the platinum film; And Removing the platinum silicide by wet etching and leaving a platinum electrode in a desired portion And a method for manufacturing a semiconductor integrated circuit device. The method of claim 23, wherein And the platinum electrode is an electrode of a capacitor of a dynamic random access memory cell formed above the main surface of the semiconductor substrate.