KR20000061473A - Duty corrector - Google Patents

Abstract

PURPOSE: A duty rate corrector is provided to appropriate in low voltage source, to embody in simple construction and to cut down design area of circuit and electric power consumption. CONSTITUTION: A duty rate corrector is composed of a first input port(301), a second input port(302) and CMOS logic gate(303). A first signal(Vin1) having a prescribed duty rate is inputted to the first input port(301). A second signal(Vin2) delayed 180°phase in comparison with the first signal(Vin1) is inputted to the second input port(302). The CMOS logic gate(303) is triggered by rising edge of the first signal(Vin1) and generates an output signal(Vout) in high level. Also, the CMOS logic gate(303) is triggered by rising edge of the second signal(Vin2) and generates the output signal(Vout) in low level. Accordingly, the CMOS logic gate(303) always generates the output signal(Vout) having 50% duty rate through an output port(304), because it performs precharge and discharge operation between 180°phase regardless of duty rate of the first and second signal(Vin1, Vin2).

Description

Duty ratio adjustment circuit {DUTY CORRECTOR}

The present invention relates to a pulse generating circuit, and more particularly to a duty ratio adjusting circuit for adjusting the duty ratio of the pulse signal.

In general, a digital signal processor (DSP) or a microprocessor uses an output signal of PLL (Phase Locked Loop) or DL (DLL: Delay Locked Loop) as an input clock signal. In this case, the duty ratio of the input clock signal in the DSP or the microprocessor determines the performance of the entire chip. Accordingly, a duty rate corrector is used to maintain the duty ratio of the clock signal output from the PL or DL at 50%.

FIG. 1 is a duty ratio adjusting circuit of Dao-Long Chen, which is presented as a first embodiment of a conventional duty ratio adjusting circuit, published at the International Solid-state Conference (ISSC, 1997).

The first embodiment of the duty ratio adjustment circuit includes an input unit for outputting a first signal V1 having a duty ratio of about 50% from the first and second input signals Vin1 and Vin2 having a phase difference of 180 °. And a buffer unit 102 for adjusting the duty ratio of the first signal V1 according to the feedback control voltage CV and a pumping operation according to the output signal Vout of the buffer unit 102. And a low pass filter 106 for filtering the output of the charge pump 104 to feed back the control voltage V1 to the buffer unit 102.

The operation of the first embodiment of the duty ratio adjustment circuit configured as described above will be described with reference to the accompanying drawings.

The input unit 100 receives the first and second input signals Vin and Vin2 having a phase difference of 180 ° from each other, and receives the first signal V1 having a duty ratio of nearly 50% by using a conventional method. The buffer unit 102 generates an output signal Vout by adjusting the duty ratio of the first signal V1 according to the control voltage CV1 fed back from the low pass filter 106. At this time, when the duty ratio of the output signal Vout is less than 50%, the charge pump 104 and the low pass filter 106 are driven by the output signal Vout to form a feedback loop. As a result, the duty ratio of the first signal V1 is adjusted by the control voltage CV1 output from the low pass filter 106, and the adjustment operation is repeated until the duty ratio of the output signal Vout becomes 50%. When the duty ratio of the output signal Vout reaches 50%, the driving of the charge pump 104 and the low pass filter 106 is stopped.

However, since the first embodiment of the conventional duty ratio adjustment circuit uses a feedback loop, it takes too much time to generate an output signal having a duty ratio of 50%. However, in view of the fact that the duty ratio adjustment circuit is usually used for timing recovery such as PL, the above time delay results in an increase in the preamble period of the timing recovery. Thrown away.

In the first embodiment of the conventional duty ratio adjustment circuit, the intrinsic delay of the input signal is increased because the duty ratio is adjusted through several steps. When the intrinsic delay is larger than expected, the clock removed at the front end is increased. Skew of the signal is caused again. In addition, since the first embodiment of the conventional duty ratio adjusting circuit uses many circuits (elements) to adjust the duty ratio, the area of the system is increased and power consumption is increased.

FIG. 2 is a duty ratio adjustment circuit of Raghunand Bhagwans, published by the International Solid Society (ISSC, 1997) as a second embodiment of the conventional duty ratio adjustment circuit.

A second embodiment of the conventional duty ratio adjustment circuit includes a level shifter 200 which is triggered by a rising edge of the first input signal Vin1 and a falling edge of the second input signal Vin2 to generate an output signal Vout. Equi-Current Buffer Unit (202) for adjusting the duty ratio of the output signal (Vout) according to the external control signal (CS), and the output signal (V1) of the isocurrent buffer unit 202 And a loop filter 204 for feeding back the control voltage CV2 to the level shifter 200.

The operation of the second embodiment of the conventional duty ratio adjustment circuit configured as described above is as follows.

The first and second input signals Vin1 and Vin2 are clock signals output from a voltage controlled oscillator (VCO) and have different duty ratios. The phase of the first input signal Vin1 is faster than the second input signal Vin2 (Lead). Thus, the second embodiment of the conventional duty ratio adjustment circuit is an invention applicable when the duty ratios are different from each other and the phase of the second input signal Vin2 is slower than the phase of the first input signal Vin1.

When the first and second input signals Vin1 and Vin2 having different phases and duty ratios are input, the level shifter 200 receives rising edges of the first input signal Vin1 and falling edges of the second input signal Vin2. Is triggered to generate an output signal (Vout). That is, first, the output signal Vout is high level by the first input signal Vin1 having a high phase, and low level by the second input signal Vin2 which is relatively slow in phase. At this time, the time point at which the output signal Vout transitions to the low level is determined by the level of the control voltage CV2 fed back. That is, when the level of the control voltage CV2 is large, the interference by the second input signal Vin2 is increased so that the output signal Vout quickly transitions to a low level, and when the level of the control voltage CV2 is small, the input signal ( The interference by Vin2) is weakened, and the output signal Vout slowly transitions to a low beret.

The isocurrent buffer unit 202 is operated until the amount of current generated by the external control signal CS and the output signal Vout is equal, and the loop filter 204 is outputted from the isocurrent buffer unit 202. Filter the feedback signal to the level shifter 200 to feed back the control voltage (CV2). At this time, the isocurrent buffer unit 202 serves as a kind of comparator and charge pump.

By the way, the second embodiment of the conventional duty ratio adjustment circuit has a feedback structure as in the first embodiment. Therefore, the problems which the first embodiment has have remain. In addition, in the second embodiment of the conventional duty ratio adjustment circuit, the isocurrent buffer portion is composed of a plurality of transistors used as a cascade, which consumes a lot of power. In addition, since the second embodiment of the conventional duty ratio adjustment circuit uses a loop filter, the layout area is increased.

Accordingly, it is an object of the present invention to provide a duty ratio adjustment circuit suitable for a low voltage source and which can be implemented with a simple structure.

Another object of the present invention is to provide a duty ratio adjustment circuit that can significantly reduce the circuit design area and power consumption.

In order to achieve the above object, the duty ratio adjustment circuit according to the present invention includes a first input terminal through which a first signal having a predetermined duty ratio is input, and a second signal delayed by 180 ° out of the first signal. And a CMOS logic gate configured to receive the first and second signals and generate an output signal having a duty ratio of 50%.

1 shows a first embodiment of a conventional duty ratio adjustment circuit.

2 shows a second embodiment of a conventional duty ratio adjustment circuit.

3 is a configuration diagram of a duty ratio adjustment circuit according to the present invention;

4 is an input / output waveform diagram of each part in FIG. 3;

*** Explanation of symbols for the main parts of the drawing ***

10: first transmission gate 20: second transmission gate

301: first input terminal 302: second input terminal

303: CMOS logic gate 304: output terminal

As shown in FIG. 3, the duty ratio adjusting circuit according to the present invention includes a first input terminal 301 to which a first signal Vin1 having a predetermined duty ratio is input, and 180 degrees from the first signal Vin1. The phase delayed second signal (Vin2 is input) is triggered by the rising edge of the second input terminal (302) and the first, second signals (Vin1, Vin2) 50% through the output terminal 304 And a CMOS logic gate 303 for generating an output signal Vout having a duty ratio.

The CMOS logic gates 303 are connected in series between the power supply voltage Vcc and the ground voltage Vss, and are symmetrical with respect to the output terminal 304. The first and second transfer gates 10 and 20 are symmetrical to each other. It consists of. The first transfer gate 10 is triggered at the rising edge of the first signal Vin1, and the second transfer gate 20 is triggered at the rising edge of the second signal Vin2. The second signal Vin2 can be easily obtained through a voltage controlled oscillator VCO, a timing recovery circuit (or a clock divider circuit), a frequency synthesizer, or the like.

In addition, the present invention may further connect a phase delay unit for delaying the first signal Vin1 by 180 ° to provide an output of the phase delay unit directly to the second input terminal 302.

The operation of the duty ratio adjustment circuit of the present invention configured as described above is as follows.

When the first signal Vin1 having a predetermined duty ratio is input through the first input terminal 301, the CMOS logic gate 303 is triggered at the rising edge of the first signal Vin1, thereby outputting the output terminal 304. A high level output signal Vout is generated through. Subsequently, when the second signal Vin2 delayed 180 ° out of the first signal Vin1 is input through the first input terminal 301, the CNOS logic gate 303 is triggered at the rising edge of the second signal Vin2. The low level output signal Vout is generated through the output terminal 304. Accordingly, since the CMOS logic gate 303 performs precharge and discharge operations between 180 ° phase regardless of the duty ratio of the first and second signals Vin1 and Vin2. Generates an output signal Vout having a duty ratio of 50% at all times.

Then, the process will be described in more detail as follows.

4 illustrates an embodiment of a timing diagram for the first and second signals Vin1 and Vin2 and the output signal Vout. FIG. 4A is a timing diagram of the first signal Vin1 having a duty ratio of about 75%, and FIG. 4B is a pair of the first signal Vin1, and the second signal Vin2 having a 180 ° phase delay. 4C is a timing diagram of an output signal Vout having a duty ratio of 50%.

As shown in FIGS. 3 and 4, when the first signal Vin1 having a duty ratio of 75% is input through the first input terminal 301, the CNO logic gate at the rising edge of the first signal Vin1. The first transfer gate 10 of 303 is turned on to precharge the output terminal 304.

At this time, since the first transfer gate 10 is composed of NMOS and PMOS transistors, the precharge speed is very fast. Therefore, the output voltage Vout becomes high level as shown in FIG.

Next, when the second signal Vin2 as shown in FIG. 4C is input through the input terminal 302, the second transfer gate 20 is turned on at the rising edge of the second signal Vin2. As a result, the output terminal 304 is discharged (discharged) so that the output voltage Vout becomes a low level as shown in FIG.

Therefore, regardless of the duty ratios of the first and second signals Vin1 and Vin2, the first and second transfer gates 10 and 20 of the CMOS logic gate 303 are always free between 180 ° phase. By repeatedly performing the charge and discharge operations, an output signal Vout having a duty ratio of 50% is generated through the output terminal 304 as shown in FIG. In addition, although the present invention exemplifies only a signal having a duty ratio of 75%, an output signal having a duty ratio of 50% can always be generated even when signals having a predetermined duty ratio other than 50% are applied to the present invention. have.

In addition, the foregoing embodiments of the present invention are not limited to the claims by way of example only, and various alternatives, modifications, and changes will be apparent to those skilled in the art.

As described above, the duty ratio adjustment circuit according to the present invention has a very simple structure, and therefore, low power and fast operation characteristics can be obtained. Also, because it operates digitally, it consumes very little power, so you don't have to worry about power growth even if you add it to other similar designs.

In addition, since the duty ratio adjusting circuit according to the present invention forms the simplest CMO type gate structure, it can be used in a low voltage source and can reduce the layout area. Thus, it can be easily used in future designs.

And, the duty ratio adjustment circuit according to the present invention can be easily symmetrical layout. Therefore, the duty ratio adjustment circuit can be used in circuits in which PEL or DL is used, such as timing recovery, clock distribution, VCO, frequency synthesizer, and the like.

In addition, since the duty ratio adjustment circuit according to the present invention adopts a feedforward method having only two gates (inverter and PMOS transistor) at most, the operation delay is almost zero. In addition, the intrinsic delay is about a few hundred picoseconds (ps), which is very small as the time generated when passing through the general gate 1-2. Therefore, when the duty ratio adjustment circuit according to the present invention is added to a circuit in which the existing duty ratio adjustment circuit is designed, another duty ratio adjustment effect can be obtained.

Claims (4)

A first input terminal to which a first signal having a predetermined duty ratio is inputted; A second input terminal to which a second signal delayed by 180 degrees out of the first signal is input; And a CMOS logic gate configured to receive the first and second signals through the first and second input terminals and generate an output signal having a duty ratio of 50%. The duty ratio adjustment circuit of claim 1, wherein the CMOS logic gate comprises first and second transfer gates connected in series between a power supply voltage and a ground voltage and controlled by first and second signals. The duty ratio control circuit of claim 2, wherein the first and second transfer gates have a symmetrical structure around the output terminal, and each transfer gate includes an NMOS transistor and a PMOS transistor having a common source and a drain connected to each other. . 3. The duty ratio adjustment circuit of claim 2, wherein the first transmission gate is turned on at the rising edge of the first signal and the second transmission gate is turned on at the rising edge of the second signal.