KR20000060453A - Voltage down converting apparatus and method for semiconductor device - Google Patents

Abstract

PURPOSE: A voltage down converter and a method thereof for a semiconductor device are provided which can generate an internal voltage required in a semiconductor device as removing an excessive over shoot phenomenon and excluding the lowering of the current capability due to the oscillation. CONSTITUTION: A voltage down converter generates an internal voltage which has a lower level than an external voltage and is required in a semiconductor device from the external voltage. The voltage down converter comprises: a comparator(10) which compares a level of a reference voltage with a level of the internal voltage and outputs the comparison result in response to a control signal; a transmission switch(12) transmitting the comparison result or outputting the external voltage in response to the control signal; a first current supply part(16) supplying a first current in response to the comparison result; a second current supply part(18) supplying a second current in response to an output of the transmission switch; and an output load(20) outputting a voltage having a level corresponding to the first and the second currents as an internal voltage. The control signal is generated according as the internal voltage is required in the semiconductor device.

Description

Voltage level converting apparatus and method for semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to level conversion of voltage, and more particularly, to a voltage level conversion device capable of stably supplying an internal voltage required in a semiconductor device.

As a conventional voltage down converter, there exist an analog voltage level converter, a digital voltage level converter and a mixed mode voltage level converter. Here, the analog voltage level converter has a long response time and a lot of power consumption, and the digital voltage level converter has a short response time and low power consumption, but has oscillation problems. Therefore, a mixed mode voltage level converter is used to compensate for the disadvantages of the analog voltage level converter and the digital voltage level converter. Such mixed mode voltage level converters operate as analog voltage level converters at low frequency and small load currents and operate at high frequency and high load currents to help the digital voltage level converters lack the current capability of analog voltage level converters.

However, such a conventional mixed mode voltage level converter is still oscillated by the digital voltage level converter so that its current capability is lowered and the analog and digital voltage level converters operate simultaneously, causing excessive overshoot. There was this.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a voltage level converting apparatus capable of generating an internal voltage required for a semiconductor device while eliminating a drop in current capability due to oscillation and removing an excessive overshoot phenomenon.

Another object of the present invention is to provide a voltage level converting method performed in the voltage level converting apparatus.

1 is a circuit diagram of a preferred embodiment of the voltage level converting apparatus according to the present invention.

2 is a circuit diagram of a preferred embodiment of the present invention of the transfer switch shown in FIG.

FIG. 3 is a flowchart for describing a voltage level converting method according to the present invention performed in the apparatus shown in FIG. 1.

In order to achieve the above object, a voltage level converting apparatus according to the present invention for generating an internal voltage required by a semiconductor device from an external voltage and having a level lower than the external voltage, the level of the reference voltage and the internal voltage in response to a control signal. A comparator that compares and outputs the compared result, a transfer switch that transmits the compared result in response to the control signal or outputs the external voltage, and supplies a first current in response to the compared result. A first current supply part, a second current supply part supplying a second current in response to an output of the transfer switch, and an output load outputting a voltage having a level corresponding to the first and second currents as the internal voltage. And the control signal is generated in accordance with the request of the internal voltage to the semiconductor device It is preferred.

In order to achieve the above another object, a voltage level converting method according to the present invention for generating an internal voltage from an external voltage, which is required in a semiconductor device and has a level lower than the external voltage, includes: (a) initializing a level of the internal voltage; (B) continuously determining whether the semiconductor device requires the internal voltage; and (c) raising the level of the initialized internal voltage when the semiconductor device requires the internal voltage; It is determined whether the difference between the level of the internal voltage and the reference voltage is a predetermined level, and if the difference is greater than the predetermined level, step (d) proceeds to step (c); if the difference is the predetermined level, the level of the internal voltage is raised. (E) reducing the width and determining whether the level of the internal voltage and the reference voltage are the same; (f) proceeding to step (e), and if the level of the internal voltage and the reference voltage is the same, it is preferable that the step of stopping the increase of the level of the internal voltage (g).

Hereinafter, the configuration and operation of the voltage level converting apparatus according to the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram of a preferred embodiment of a voltage level converting apparatus according to the present invention, in which first and second currents, which may be implemented by a comparator 10, a transfer switch 12, and PMOS transistors MP1 and MP2, respectively. It consists of supplies 16 and 18, an output load 20 and a buffer 14.

Referring to FIG. 1, the comparator 10 compares the levels of the reference voltage Vref and the internal voltage IVC (Internal VCC) in response to a control signal C provided from the outside, and compares the result with the first current. Output to the supply unit 16. At this time, the control signal C is a signal generated from the outside corresponding to whether the semiconductor device requires the internal voltage IVC.

The transfer switch 12 transmits the result compared by the comparator 10 to the second current supply unit 18 in response to the control signal C or transmits an external voltage EVC (External VCC) to the second current supply unit 18. It plays a role of outputting. Looking at the configuration and operation of an embodiment according to the present invention of the transfer switch 12 as follows.

FIG. 2 is a circuit diagram of a preferred embodiment of the transfer switch 12 shown in FIG. 1 according to the present invention, including a delay unit 40, an exclusive inversion logic unit 42, a transfer gate 60 and a voltage supply unit 62. FIG. It consists of.

The delay unit 40 of the transfer switch 12 shown in FIG. 2 delays the control signal C by a predetermined time and outputs the delayed control signal to the exclusive inversion logic sum unit 42. The exclusive inversion AND unit 42 exclusively inverts the control signal delayed by the delay unit 40 and the control signal C input from the outside, and outputs the result of the exclusive inversion AND as the transmission control signal of the transmission gate 60. do. To this end, the exclusive inversion logic sum 42 includes an inverter 44 for inverting the control signal delayed by the delay unit 40, a NAND gate 48 for inverting AND of the output of the inverter 44 and the control signal C, Inverting logic of the inverter 46 for inverting the control signal C, the outputs of the NAND gate 50 and the NAND gates 48 and 50 that inversely AND the output of the inverter 46 and the output of the delay unit 40. A multiplied NAND gate 52 and an inverter 54 that inverts the output of the NAND gate 52 and outputs the inverted result as a transmission control signal.

The transmission gate 60 transmits the compared result input from the comparator 10 through the input terminal IN to the voltage supply part 62 in response to the transmission control signal which is the result of the exclusive inversion logic sum. To this end, the transfer gate 60 is a PMOS transistor MP3 and an inverter 56 having a gate connected to a transmission control signal that is an output of the inverter 54, a source and a drain connected between an input terminal IN and an output terminal OUT. An NMOS transistor MN1 having a gate connected to the output of the source, a source and a drain connected between the input terminal IN and the output terminal OUT.

In response to the transfer control signal, the voltage supply unit 62 transfers the output of the external voltage EVC or the transfer gate 60 to the gate of the PMOS transistor MP2 shown in FIG. 1 through the output terminal OUT. To this end, the voltage supply 62 has an inverter 56 which inverts the transmission control signal and a PMOS having a gate connected to the output of the inverter 56, a source and a drain connected between the external voltage EVC and the output terminal OUT. It consists of a transistor MP4.

Meanwhile, the first current supply unit 16 supplies the first current to the output load 20 in response to the result compared by the comparator 10. To this end, the first current supply unit 16 may be implemented as a PMOS transistor MP1 having a gate connected to the output of the comparator 10, a source and a drain connected between the external voltage EVC and the output load 20. Can be.

The second current supply unit 20 supplies the second current to the output load 20 in response to the output of the transfer switch 12. To this end, the second current supply unit 18 is implemented as a PMOS transistor MP2 having a gate connected to the output of the transfer switch 12, a source and a drain connected between the external voltage EVC and the output load 20. Can be. In this case, the second current supply unit 18 may supply the second current in response to a result of delaying the output of the transfer switch 12 by a predetermined time instead of the output of the transfer switch 12. That is, the voltage level converter shown in FIG. 1 may further provide a buffer 18 that buffers the output of the transfer switch 12 and outputs the buffered result to the gate of the PMOS transistor MP2.

The output load 20 transfers a voltage having a level corresponding to the first and second currents output from the first and second current supplies 16 and 18 to the semiconductor device (not shown) as the internal voltage IVC. Output To this end, the output load 20 may include a predetermined number of resistors and a capacitor.

FIG. 3 is a flowchart illustrating a method for converting a voltage level according to the present invention performed in the apparatus shown in FIG. 1. The reference voltage Vref and the internal voltage (Vref) may be determined depending on whether an internal voltage IVC is required in a semiconductor device. Comparing the levels of IVC) and rapidly or slowly raising the internal voltage corresponding to the compared result (steps 80 to 92).

First, when the semiconductor device does not require an internal voltage, the apparatus shown in Fig. 1 does not operate in response to a control signal C of, for example, a "high" logic level. However, the device shown in FIG. 1 starts to operate in response to the control signal C at the "low" logic level before requiring the internal voltage IVC in the semiconductor device. At this time, the comparator 10 adjusts the appropriate level by operating the first and second current supplies 16 and 18 when the level of the internal voltage IVC is lower than the level of the reference voltage Vref. That is, the level of the internal voltage IVC is initialized (step 80).

After the eighty-eighth step, the semiconductor device continuously determines whether the internal voltage IVC is required (step 82). If the semiconductor device requires an internal voltage, the level of the internal voltage IVC is lowered and the comparator 10 operates to operate the first and second current supplies 16 and 18 so that a large amount of first and As the second currents flow, the level of the initialized internal voltage IVC is quickly increased (step 84).

After step 84, it is determined whether the difference between the level of the internal voltage IVC and the reference voltage Vref is a predetermined level (step 86). If the level difference between the internal voltage IVC and the reference voltage Vref is greater than the predetermined level, the flow proceeds to step 84. That is, if the level of the internal voltage IVC is far below the level of the reference voltage Vref, the level of the internal voltage IVC is continuously increased. However, if the level difference between the internal voltage IVC and the reference voltage Vref is a predetermined level, the rising width of the level of the internal voltage IVC is reduced (step 88). That is, when the level of the internal voltage IVC approaches the level of the reference voltage Vref, the second current supply unit 18 stops the operation by the transfer switch 12 so that the second current is not supplied and the internal voltage ( Allow the IVC) level to rise slowly.

After operation 88, it is determined whether the level of the internal voltage IVC and the reference voltage Vref are the same (step 90). If the levels of the internal voltage IVC and the reference voltage Vref are not the same, the flow proceeds to step 88 and the level of the internal voltage IVC is continuously increased. However, if the levels of the internal voltage IVC and the reference voltage Vref are the same, the increase of the level of the internal voltage IVC is stopped (step 92). To this end, when the level of the internal voltage IVC and the reference voltage Vref are the same, the first current supply unit 16 stops in response to the output of the comparator 10 and the supply of the first current is stopped. . Therefore, the level of the internal voltage IVC is suppressed from rising sharply and excessive overshoot can be prevented. When the level of the internal voltage IVC rises to a desired level, the control signal C is generated at a "high" logic level, and the device shown in FIG. 1 again stops operating.

As described above, the voltage level converting apparatus and method for a semiconductor device according to the present invention excludes a decrease in current capability due to the oscillation of a conventional digital voltage level converting apparatus, and the analog and digital voltage level converting apparatuses operate simultaneously. Thereby, there is an effect that can stably generate an internal voltage having a level required by the semiconductor device from an external voltage while eliminating an overshoot phenomenon that can be induced.

Claims (4)

A voltage level converting apparatus for generating an internal voltage having a level lower than the external voltage, which is required in a semiconductor device from an external voltage, A comparator comparing the level of the reference voltage and the internal voltage in response to a control signal and outputting a result of the comparison; A transfer switch for transmitting the compared result or outputting the external voltage in response to the control signal; A first current supply unit supplying a first current in response to the compared result; A second current supply unit supplying a second current in response to an output of the transfer switch; And An output load that outputs a voltage having a level corresponding to the first and second currents as the internal voltage, And the control signal is generated in response to requesting the internal voltage from the semiconductor device. The method of claim 1, wherein the transfer switch A delay unit delaying the control signal and outputting a delayed control signal; Exclusive inversion-OR means for outputting a result of the exclusive inversion-OR of the delayed control signal and the control signal; A transmission gate for transmitting the compared result in response to the exclusive inverted OR result; And And a voltage supply unit configured to provide the external voltage as an output of the transfer switch in response to the result of the exclusive inversion logic sum. The apparatus of claim 1 or 2, wherein the voltage level converting device And a buffer for buffering an output of the transfer switch, And the second current supply unit supplies the second current in response to the output of the buffer instead of the output of the transfer switch. A voltage level converting method for generating an internal voltage from an external voltage having a level lower than the external voltage required in a semiconductor device, (a) initializing the level of the internal voltage; (b) continuously determining whether the semiconductor device requires the internal voltage; (c) raising the level of the initialized internal voltage when the semiconductor device requires the internal voltage; (d) determining whether the difference between the level of the internal voltage and the reference voltage is a predetermined level, and if the level is greater than the predetermined level, proceeding to step (c); (e) reducing the rising width of the level of the internal voltage if the difference is the predetermined level; (f) determining whether the level of the internal voltage and the reference voltage are the same, and if not, proceeding to step (e); And (g) if the level of the internal voltage and the reference voltage is the same, stopping the rise of the level of the internal voltage.